Patents by Inventor Qiuhua Han

Qiuhua Han has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220254852
    Abstract: The present disclosure provides a method for fabricating a displaying backplane, a displaying backplane and a displaying device, and relates to the technical field of displaying. The method includes forming a first active layer and a second active layer on a substrate base plate; forming a first grid insulating layer covering the first active layer and the second active layer; forming a first grid on the first grid insulating layer; performing ion implantation to the first no-channel regions, the second no-channel regions and the second channel region, to reduce oxygen-vacancy concentrations of the first no-channel regions, the second no-channel regions and the second channel region; and forming a second grid on the first grid insulating layer.
    Type: Application
    Filed: September 27, 2021
    Publication date: August 11, 2022
    Applicant: BOE Technology Group Co., Ltd.
    Inventors: Jing Wang, Hongwei Tian, Ming Liu, Jia Zhao, Qiuhua Meng, Ziang Han
  • Patent number: 11205596
    Abstract: A method of manufacturing a semiconductor device includes providing a substrate structure, which includes a substrate, one or more semiconductor fins on the substrate, a gate structure on each fin, an active region located in said fins, and an interlayer dielectric layer covering at the active region. The method includes forming a hard mask layer over the interlayer dielectric layer and the gate structure, and using an etch process with a patterned etch mask, forming a first contact hole extending through the hard mask layer and extending into a portion of the interlayer dielectric layer, using patterned a mask. The method further includes forming a sidewall dielectric layer on sidewalls of the first contact hole, and using an etch process with the sidewall dielectric layer as an etch mask, etching the interlayer dielectric layer at bottom of the first contact hole to form a second contact hole extending to the active region.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: December 21, 2021
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Qiuhua Han, Longjuan Tang
  • Patent number: 10707117
    Abstract: The present disclosure teaches interconnection structures and methods for manufacturing the same.
    Type: Grant
    Filed: November 6, 2018
    Date of Patent: July 7, 2020
    Assignees: Semiconductor Manufacturing (Shanghai) International Corporation, Semiconductor Manufacturing (Beijing) International Corporation
    Inventors: Qiuhua Han, Kai Yan, Duan Yi Wu
  • Patent number: 10403732
    Abstract: A method is provided for fabricating stripe structures. The method includes providing a substrate; and forming a to-be-etched layer on the substrate. The method also includes forming a hard mask pattern having a first stripe on the to-be-etched layer; and forming a photoresist pattern having a stripe opening on the to-be-etched layer and the hard mask pattern having the first stripe. Further, the method includes forming a polymer layer on a top surface and side surfaces of the photoresist pattern to reduce a width of the stripe opening; forming hard mask patterns having a second stripe by etching the hard mask pattern having the first stripe using the photoresist pattern having the polymer layer as an etching mask; and forming the stripe structures by etching the to-be-etching layer using the hard mask pattern having the second stripe as an etching mask until the substrate is exposed.
    Type: Grant
    Filed: February 29, 2016
    Date of Patent: September 3, 2019
    Assignee: Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Xiaoying Meng, Qiuhua Han
  • Publication number: 20190181038
    Abstract: The present disclosure teaches interconnection structures and methods for manufacturing the same.
    Type: Application
    Filed: November 6, 2018
    Publication date: June 13, 2019
    Applicants: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) Corporation
    Inventors: Qiuhua Han, Kai Yan, Duan Yi Wu
  • Patent number: 10050036
    Abstract: Various embodiments provide a semiconductor structure having a common gate and fabrication method of the semiconductor structure. In an exemplary method, after forming a first metal gate and a second metal gate, a conductive material layer can be formed at least at the boundary between the first metal gate and the second metal gate. Thus, one end of the conductive material layer can be connected to a first metal gate electrode, and the other end of the conductive material layer can be connected to a second metal gate electrode. The resistance between the first metal gate electrode and the second metal gate electrode can be effectively reduced. Gate voltages of an NMOS transistor and a PMOS transistor of the common gate can be the same.
    Type: Grant
    Filed: October 20, 2015
    Date of Patent: August 14, 2018
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Qiuhua Han, Xiaoying Meng
  • Publication number: 20180144990
    Abstract: A method of manufacturing a semiconductor device includes providing a substrate structure, which includes a substrate, one or more semiconductor fins on the substrate, a gate structure on each fin, an active region located in said fins, and an interlayer dielectric layer covering at the active region. The method includes forming a hard mask layer over the interlayer dielectric layer and the gate structure, and using an etch process with a patterned etch mask, forming a first contact hole extending through the hard mask layer and extending into a portion of the interlayer dielectric layer, using patterned a mask. The method further includes forming a sidewall dielectric layer on sidewalls of the first contact hole, and using an etch process with the sidewall dielectric layer as an etch mask, etching the interlayer dielectric layer at bottom of the first contact hole to form a second contact hole extending to the active region.
    Type: Application
    Filed: November 15, 2017
    Publication date: May 24, 2018
    Inventors: QIUHUA HAN, Longjuan Tang
  • Patent number: 9741820
    Abstract: The disclosed subject matter provides a p-channel metal-oxide-semiconductor (PMOS) and fabrication method thereof. The PMOS transistor is fabricated by a method including forming a dummy gate structure on a semiconductor substrate, forming a source region and a drain region in the semiconductor substrate on both sides of the dummy gate structure, forming an intermediate layer to cover the dummy gate structure and the semiconductor substrate, and forming a multiple-level etching stop layer including at least a first etching stop layer and a second etching stop layer. The fabrication method also includes performing a UV curing process after forming each of the first and second etching stop layers.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: August 22, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Qiuhua Han, Lihong Xiao
  • Patent number: 9704972
    Abstract: A method is provided for fabricating transistors. The method includes providing a semiconductor substrate. The substrate has a gate film and a mask film formed on a top surface. The mask film contains implanted carbon ions. The method further includes forming a mask layer by etching the mask film and then forming a gate layer by etching through the gate film using the mask layer as a mask until the substrate is exposed. The method also includes forming a first sidewall containing implanted carbon ions on the side surface of the gate layer and the mask layer; forming a stress layer in the substrate on both sides of the gate layer and the first sidewall; and forming a source region on one side of the gate layer and the first sidewall and a drain region on the other side of the gate layer and the first side wall.
    Type: Grant
    Filed: September 25, 2015
    Date of Patent: July 11, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Qiuhua Han, Jie Chen
  • Patent number: 9689132
    Abstract: A drainage ditch, including: a ditch body. The ditch body includes, from the top down: a separate layer, a first filter layer, a second filter layer, and a third filter layer. The separate layer is straw or stover; the first filter layer is crush stones having particle sizes of between 5 and 15 mm; the second filter layer is crush stones having particle sizes of between 20 mm and 40 mm; the third filter layer is stones having particle sizes of between 30 mm and 70 mm. The separate layer is covered by a plough layer.
    Type: Grant
    Filed: November 20, 2015
    Date of Patent: June 27, 2017
    Inventor: Qiuhua Han
  • Patent number: 9660058
    Abstract: A method of fabricating a fin for a FinFET device includes providing a semiconductor substrate, forming a patterned silicon germanium layer on the semiconductor substrate, epitaxially growing a silicon layer on a top surface and sidewalls of the patterned silicon germanium layer, forming a sacrificial layer covering the patterned silicon germanium layer, and removing the sacrificial layer and a portion of the silicon layer disposed on the top surface of the patterned silicon germanium layer until a top surface of the sacrificial layer is co-planar with the top surface of the patterned silicon germanium layer. The method further includes removing the patterned silicon germanium layer and removing the sacrificial layer to form the fin. The epitaxially formed fin does not have the issues of line width roughness and edge roughness to improve the performance of the FinFET device.
    Type: Grant
    Filed: February 2, 2015
    Date of Patent: May 23, 2017
    Assignees: Semiconductor Manufacturing International (Beijing) Corporation, Semiconductor Manufacturing International (Shanghai) Corporation
    Inventor: Qiuhua Han
  • Patent number: 9640657
    Abstract: Semiconductor devices and fabrication methods are provided. In an exemplary method, a semiconductor layer including a first opening can be provided. The first opening can be filled with a stress material. The stress material can then be etched to form a second opening having a width less than a width of the first opening to leave a stress material layer in the semiconductor layer and on each sidewall of the second opening. The semiconductor layer can be etched to form a fin structure on a sidewall surface of the stress material layer. A main gate structure can be formed on the sidewall surface of the fin structure. A back gate structure can be formed on the sidewall surface of the stress material layer.
    Type: Grant
    Filed: July 27, 2015
    Date of Patent: May 2, 2017
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Qiuhua Han
  • Publication number: 20160351686
    Abstract: The disclosed subject matter provides a p-channel metal-oxide-semiconductor (PMOS) and fabrication method thereof. The PMOS transistor is fabricated by a method including forming a dummy gate structure on a semiconductor substrate, forming a source region and a drain region in the semiconductor substrate on both sides of the dummy gate structure, forming an intermediate layer to cover the dummy gate structure and the semiconductor substrate, and forming a multiple-level etching stop layer including at least a first etching stop layer and a second etching stop layer. The fabrication method also includes performing a UV curing process after forming each of the first and second etching stop layers.
    Type: Application
    Filed: June 1, 2016
    Publication date: December 1, 2016
    Inventors: QIUHUA HAN, LIHONG XIAO
  • Patent number: 9508609
    Abstract: Various embodiments provide FinFETs and methods for forming the same. In an exemplary method, a semiconductor substrate having sacrificial layers formed thereon is provided. First sidewall spacers and second sidewall spacers are sequentially formed on both sides of each sacrificial layer. The sacrificial layers can be removed. A first width is measured as a distance between adjacent first sidewall spacers, and a second width is measured as a distance between adjacent second sidewall spacers. When the first width is not equal to the second width, the first sidewall spacers or the second sidewall spacers are correspondingly etched such that the first width is equal to the second width. The semiconductor substrate is etched using the first sidewall spacers and the second sidewall spacers as an etch mask, to form fins, such that a top of each fin has a symmetrical morphology.
    Type: Grant
    Filed: July 21, 2014
    Date of Patent: November 29, 2016
    Assignees: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (BEIJING) CORPORATION, SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Qiuhua Han
  • Publication number: 20160254359
    Abstract: A method is provided for fabricating stripe structures. The method includes providing a substrate; and forming a to-be-etched layer on the substrate. The method also includes forming a hard mask pattern having a first stripe on the to-be-etched layer; and forming a photoresist pattern having a stripe opening on the to-be-etched layer and the hard mask pattern having the first stripe. Further, the method includes forming a polymer layer on a top surface and side surfaces of the photoresist pattern to reduce a width of the stripe opening; forming hard mask patterns having a second stripe by etching the hard mask pattern having the first stripe using the photoresist pattern having the polymer layer as an etching mask; and forming the stripe structures by etching the to-be-etching layer using the hard mask pattern having the second stripe as an etching mask until the substrate is exposed.
    Type: Application
    Filed: February 29, 2016
    Publication date: September 1, 2016
    Inventors: XIAOYING MENG, QIUHUA HAN
  • Patent number: 9331079
    Abstract: A method of manufacturing a semiconductor device is provided. The method includes providing a semiconductor substrate, forming a plurality of fins on the semiconductor substrate, forming a plurality of shallow trench isolation (STI) structures on the semiconductor substrate on opposite sides of the fins, forming a dummy gate on the fins, forming gate spacers on opposite sides of the dummy gate, etching a first portion of the STI structures disposed outside a gate region, the first portion having a first predetermined thickness, forming an interlayer dielectric over the semiconductor substrate, removing the dummy gate, etching a second portion of the STI structures disposed in the gate region, the second portion having a second predetermined thickness, and forming a high-k dielectric layer and a metal gate in an area where the dummy gate is removed.
    Type: Grant
    Filed: April 23, 2015
    Date of Patent: May 3, 2016
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventor: Qiuhua Han
  • Patent number: 9312355
    Abstract: A method is provided for fabricating stripe structures. The method includes providing a substrate; and forming a to-be-etched layer on the substrate. The method also includes forming a hard mask pattern having a first stripe on the to-be-etched layer; and forming a photoresist pattern having a stripe opening on the to-be-etched layer and the hard mask pattern having the first stripe. Further, the method includes forming a polymer layer on a top surface and side surfaces of the photoresist pattern to reduce a width of the stripe opening; forming hard mask patterns having a second stripe by etching the hard mask pattern having the first stripe using the photoresist pattern having the polymer layer as an etching mask; and forming the stripe structures by etching the to-be-etching layer using the hard mask pattern having the second stripe as an etching mask until the substrate is exposed.
    Type: Grant
    Filed: June 4, 2014
    Date of Patent: April 12, 2016
    Assignee: SEMICONDUCTOR MANUFACTURING INTERNATIONAL (SHANGHAI) CORPORATION
    Inventors: Xiaoying Meng, Qiuhua Han
  • Publication number: 20160093718
    Abstract: A method is provided for fabricating transistors. The method includes providing a semiconductor substrate. The substrate has a gate film and a mask film formed on a top surface. The mask film contains implanted carbon ions. The method further includes forming a mask layer by etching the mask film and then forming a gate layer by etching through the gate film using the mask layer as a mask until the substrate is exposed. The method also includes forming a first sidewall containing implanted carbon ions on the side surface of the gate layer and the mask layer; forming a stress layer in the substrate on both sides of the gate layer and the first side-wall; and forming a source region on one side of the gate layer and the first sidewall and a drain region on the other side of the gate layer and the first side wall.
    Type: Application
    Filed: September 25, 2015
    Publication date: March 31, 2016
    Inventors: QIUHUA HAN, JIE CHEN
  • Publication number: 20160076214
    Abstract: A drainage ditch, including: a ditch body. The ditch body includes, from the top down: a separate layer, a first filter layer, a second filter layer, and a third filter layer. The separate layer is straw or stover; the first filter layer is crush stones having particle sizes of between 5 and 15 mm; the second filter layer is crush stones having particle sizes of between 20 mm and 40 mm; the third filter layer is stones having particle sizes of between 30 mm and 70 mm. The separate layer is covered by a plough layer.
    Type: Application
    Filed: November 20, 2015
    Publication date: March 17, 2016
    Inventor: Qiuhua HAN
  • Publication number: 20160043086
    Abstract: Various embodiments provide a semiconductor structure having a common gate and fabrication method of the semiconductor structure. In an exemplary method, after forming a first metal gate and a second metal gate, a conductive material layer can be formed at least at the boundary between the first metal gate and the second metal gate. Thus, one end of the conductive material layer can be connected to a first metal gate electrode, and the other end of the conductive material layer can be connected to a second metal gate electrode. The resistance between the first metal gate electrode and the second metal gate electrode can be effectively reduced. Gate voltages of an NMOS transistor and a PMOS transistor of the common gate can be the same.
    Type: Application
    Filed: October 20, 2015
    Publication date: February 11, 2016
    Inventors: QIUHUA HAN, XIAOYING MENG