Abstract: This application discloses a CIS pixel readout structure. An SF and an SG adopt an asymmetric spacer structure, so that the pitch from a lower end of a source metal plug of the SG to SG gate poly can be reduced while keeping the pitch from a lower end of a drain metal plug of the SF to SF gate poly unchanged, thus reducing the pitch from a drain connecting point of the SF to a source connecting point of the SG. Since a source of the SG is not connected with working voltage and it is not influenced by leakage, not only can GIDL current be maintained, but also parasitic resistance can be reduced. Without changing its effective size, it can reduce the parasitic resistance effect while reducing the area of a combined structure of the SF and the SG.

Abstract: This application discloses a CIS pixel readout circuit structure. An SG and an SF adopt different transverse thicknesses of spacers. The spacer of the SG adopts a smaller transverse thickness to reduce the parasitic resistance. The spacer of the SF adopts a larger transverse thickness to reduce the GIDL current. In the CIS pixel readout circuit structure according to this application, drain metal plugs are formed on outer sides of both left and right ends of an SF gate structure. The SF and the SG form a T-shaped combined compact structure to achieve equivalent parallel connection of two SF, thus effectively reducing the parasitic resistance of the share active area between the SG and the SF, and simultaneously saving the space area. This application further discloses a method for fabricating a CIS pixel readout circuit structure.

Abstract: The present disclosure discloses a method for manufacturing a NOR flash. The drain area groove and the peripheral isolation grooves are first formed and filled with the trench isolation oxide, followed by the formation of the source area groove, and then the SiH4 layer is deposited. Due to the poor filling property of SiH4, the air gap may be formed at the source area groove with a small gap, and at this time, the drain area groove in the drain area of the storage area and the peripheral isolation groove in the logic area both have been filled and thus are unaffected. The method for manufacturing a NOR flash of the present disclosure allows the formation of the source air gap of the NOR flash based on a post-source preparation process and good filling of the drain, reducing the coupling effect between the source polysilicon gates.

Abstract: Embodiments of the present disclosure provide a touch substrate, a touch display panel and a touch display apparatus. The touch display panel includes: a base substrate; a touch electrode layer on the base substrate and in a touch display region, the touch electrode layer including touch electrodes in the same layer and insulated from each other; and touch leads on the base substrate, each touch lead is electrically connected to a corresponding one touch electrode, some touch leads extend from the touch display region through the first bending region to the first binding region, and are bent to the back of the touch display panel in the first bending region, and the other touch leads extend from the touch display region through the second bending region to the second binding region, and are bent to the back of the touch display panel in the second bending region.

Abstract: A system and a method for implementing a squeeze treatment to apply a scale inhibitor in a wellbore are provided. An exemplary method includes mixing a scale inhibitor pill. The scale inhibitor pill includes polyamino polyether methylene phosphonic acid (PAPEMP) and amino trimethylene phosphonic acid (ATMP). Pre-flush chemicals are injected into the wellbore. The scale inhibitor pill is injected into the wellbore. An over flush is injected into the wellbore. The wellbore is shut in for a target period of time and normal production is resumed.

Abstract: Provided are a display substrate and a display device. The display substrate includes a base substrate, and a driving circuit layer and a light-emitting device layer on the base substrate. The display substrate includes a light-transmitting display area and a normal display area, the normal display area surrounds at least a portion of the light-transmitting display area. The normal display area includes multiple normal driving circuits and multiple dummy driving circuits; some dummy driving circuit are used for driving light-emitting devices located in the light-transmitting display area. The display substrate further includes multiple normal data lines coupled to the normal driving circuits; at least one normal data line is coupled to a data signal input terminal through a data lead; an orthographic projection of the data lead onto the base substrate at least partially overlaps an orthographic projection of the dummy driving circuit onto the base substrate.

Abstract: The present disclosure relates to the technical field of display, and provides a display panel and a display apparatus. The display panel includes a display area and a fan-out area located in the display area. The display panel further includes: a base substrate; a plurality of data lines located in the display area; a plurality of first data fan-out lines located in the fan-out area; and a plurality of second data fan-out lines located in the fan-out area.

Abstract: Disclosed are a display substrate and a display device. The display substrate includes: a display area and a bezel area, the display area including a first display area and a second display area; a plurality of light emitting devices, a plurality of pixel driving circuits, a plurality of data lines, and a plurality of first wires in the second display area and extending in a row direction, where all the first wires are located at a plurality of row gaps adjacent to the first display area respectively, each of the plurality of first wires is connected between one data line corresponding to the first display area and one first pixel driving circuit corresponding to the one data line.

Abstract: A method of treating a subterranean formation to protect against solid deposition and corrosion attack includes flowing a pre-flush fluid to a specified downhole location within the subterranean formation. A main treatment fluid is flowed to the specified downhole location. The main treatment fluid includes a scale inhibitor configured to inhibit formation of scale within the subterranean formation. At a subsurface level, an overflush foam is generated. The overflush foam includes an aqueous fluid and a gas. The overflush foam is shear thinning and non-Newtonian. The overflush foam is flowed to the specified downhole location.

Abstract: A system and method are provided for adding chemicals to a produced fluid in a wellbore. An exemplary system includes a gauge hanger and a permeable container. The permeable container includes a solid cylindrical body, end caps placed at each end of the solid cylindrical body, and holes disposed proximate to each end of the permeable container, wherein the holes allow the produced fluid to flow through the permeable container from one end of the permeable container to the opposite end of the permeable container. The system further includes a well treatment chemical disposed in the permeable container.

Abstract: A system and a method for implementing a squeeze treatment to apply a scale inhibitor in a wellbore are provided. An exemplary method includes mixing a scale inhibitor pill. The scale inhibitor pill includes polyamino polyether methylene phosphonic acid (PAPEMP) and amino trimethylene phosphonic acid (ATMP). Pre-flush chemicals are injected into the wellbore. The scale inhibitor pill is injected into the wellbore. An over flush is injected into the wellbore. The wellbore is shut in for a target period of time and normal production is resumed.

Abstract: A display substrate and a display device are provided. The display substrate includes a first display region and a first region at least partially surrounding the first display region; the first display region includes first light-emitting elements, the first region includes first pixel circuits and at least one first capacitance compensation structure, and the display substrate includes transparent wiring lines extending from the first region to the first display region; the first pixel circuit is electrically connected to the first light-emitting element through the transparent wiring line, and is configured to control a driving current flowing through the first pixel circuit, the transparent wiring line, and the first light-emitting element; and the first capacitance compensation structure is coupled to the transparent wiring line, and is configured to compensate for a parasitic capacitance caused by the transparent wiring line coupled to the first capacitance compensation structure.

Abstract: Disclosed are a display panel and a display apparatus, the display panel includes a display region, the display region includes a light transmitting display region and a conventional display region located on at least one side of the light transmitting display region, the conventional display region includes a first region, a second region, and a third region; at least one circuit unit of the first region in the conventional display region is connected with a light emitting device in the light transmitting display region, at least one circuit unit of the third region in the conventional display region includes a data connection line, a second high-voltage power supply line includes a first sub-high-voltage power supply line and a second sub-high-voltage power supply line connected with each other, the second sub-high-voltage power supply line is located on a side of the first sub-high-voltage power supply line away from the base substrate.

Abstract: The present disclosure relates to a display panel and a display device. The display panel includes a base substrate with a display area and a non-display area surrounding the display area, the display area including a first display sub-area and a second display sub-area; a plurality of first light emitting elements formed on the base substrate and located in the first display sub-area; and a plurality of first pixel circuits formed on the base substrate and located in at least one of the second display sub-area and the non-display area, where the first pixel circuits are electrically connected to the first pixel electrodes of the first light emitting elements through a conductive wire.

Abstract: The display substrate includes: a display area and a bezel area, the display area including a first display area and a second display area; first light emitting devices in the first display area and second light emitting devices in the second display area; first pixel drive circuits in the bezel area and second pixel drive circuits in the second display area, the first pixel drive circuits are connected to the first light emitting devices, and the second pixel drive circuits are connected to the second light emitting devices; and shift registers in the bezel area, one shift register is connected with the first pixel driving circuits connected with one row of the first light emitting devices and the second pixel driving circuits connected with one row of the second light emitting devices.

Abstract: The present invention relates, in part, to methods for using STING agonists to polarize pro-tumor macrophages in a subject with cancer into anti-tumor macrophages, for example to improve effectiveness of PARP inhibition.

Abstract: A display substrate and a display device. The display substrate a base substrate and a first display region, a second display region and N anode connection lines on the base substrate; the first display region includes M first pixel driving circuits, M first connection holes, N second pixel driving circuits, and N second connection holes, the second display region includes N anode connection holes; N anode connection lines connect the N second connection holes with the N anode connection holes; the N anode connection holes form a plurality of anode connection hole rows along a third direction, a plurality of the anode connection holes in each of the anode connection hole rows are arranged along the third direction, the plurality of the anode connection hole rows are arranged along a direction perpendicular to the third direction.

Abstract: A display substrate, comprising a substrate, a circuit structure layer, a light-emitting structure layer and multiple conductive layers. The circuit structure layer is arranged on one side of the substrate and comprises multiple first pixel circuits located in the second display region. The light-emitting structure layer is arranged on the side of the circuit structure layer away from the substrate, and comprises multiple first light-emitting elements in the first display region. The multiple conductive layers are arranged between the circuit structure layer and the light-emitting structure layer, and comprise multiple conductive wires. The multiple conductive wires of the at least one conductive layer comprise multiple first conductive wires and multiple second conductive wires. The first conductive wires extend in a first direction, and each of the second conductive wires at least comprises first parts extending in the first direction and second parts extending in a second direction.

Abstract: A display substrate and a display panel are provided.

Abstract: Provided is a pixel circuit. The pixel circuit includes a semiconductor layer on a side of a base substrate, wherein the semiconductor layer is configured to form an active layer of each of various transistors in the pixel circuit; a first metal layer on the side of the base substrate, wherein the first metal layer is configured to form a gate electrode of the transistor and a first capacitive electrode of a storage capacitor in the pixel circuit; and a second metal layer on the side of the base substrate, wherein the second metal layer is configured to form a second capacitive electrode of the storage capacitor.