Abstract: Methods may comprise providing a corrosion inhibitor composition comprising a dipyrazolopyridine of about 0.1 wt % to about 5 wt % concentration based on a total weight of the corrosion inhibitor composition; a long-chain amine of about 0.1 wt % to about 5 wt % concentration based on the total weight of the corrosion inhibitor composition; a thiourea of about 0.1 wt % to about 5 wt % concentration based on the total weight of the corrosion inhibitor composition; a thiazole of about 0.1 wt % to about 5 wt % concentration based on the total weight of the corrosion inhibitor composition; and a surfactant of about 0.1 wt % to about 5 wt % concentration based on the total weight of the corrosion inhibitor composition; contacting a metal surface with the corrosion inhibitor composition; and allowing the corrosion inhibitor composition to interact with the metal surface so as to inhibit corrosion of the metal surface.

Abstract: The application discloses a process integration method for improving leakage in MV devices, comprising: step I: forming gate structures, step II: depositing a first spacer material layer, step III: forming an additional spacer material layer, step IV: forming a first mask layer to cover an MV device formation region and open an LV device formation region, step V: performing an isotropic first etching to remove the additional spacer material layer from the LV device formation region, step VI: performing an anisotropic second etching to form a first layer of spacers of the low voltage region, step VII: forming a second mask layer to open the MV device formation region and to cover the LV device formation region, step VIII: performing an anisotropic third etching to form a first layer of spacers of the medium voltage region and additional spacers, and step IX: depositing and etching a second spacer material layer.

Abstract: A method for treating scale includes feeding a pre-flush fluid into a portion of a subterranean formation via a wellbore. The method includes feeding an inhibitor main pill fluid into the portion of the subterranean formation via the wellbore after the pre-flush fluid, wherein the inhibitor main pill fluid comprises a scale inhibitor. The method includes feeding an overflush fluid into the portion of the subterranean formation via the wellbore after the inhibitor main pill fluid, wherein the overflush fluid comprises one or more surfactant. The method includes shutting in the pre-flush fluid, the inhibitor main pill fluid, and the overflush fluid within the portion of the subterranean formation for a pre-determined period of time.

Abstract: The present disclosure provides a display substrate and a display device. A display region of the display substrate includes a first display region and a second display region arranged opposite to each other, a peripheral region includes a notch arranged between the first display region and the second display region. A scanning line in the display substrate includes a first scanning member, a second scanning member and a compensation scanning member, the first scanning member is arranged in the first display region, the second scanning member is arranged in the second display region, and at least a part of the compensation scanning member is arranged in the notch. The compensation scanning member is coupled to the first scanning member and the second scanning member. An orthogonal projection of the compensation scanning member onto the base substrate overlaps with an orthogonal projection of a peripheral power line onto the base substrate.

Abstract: Provided are a display panel and a display device. The display panel includes: light-emitting elements and pixel circuits. The pixel circuits include a plurality of groups of pixel circuits; at least one group of pixel circuits includes a plurality of first-type pixel circuits and a plurality of second-type pixel circuits; at least one second-type pixel circuit is connected to at least one second region light-emitting element through one conductive line; the conductive lines include a plurality of first conductive wires and a plurality of second conductive wires; and in at least one group of light-emitting elements and at least one group of pixel circuits, a plurality of first pixel circuits connected to a plurality of first light-emitting elements are closer to a second display region than each of a plurality of second pixel circuits connected to a plurality of second light-emitting elements.

Abstract: The present application discloses a high-voltage NMOSFET. The P-type well area is formed in the first active area, while the first and second source/drain areas are respectively formed in second and third active areas. The fourth active area is disposed to surround peripheral sides of first to third active areas. The P-type deep diffusion area and a substrate contact area are formed in the fourth active area. The P-type ion implantation area of P-type deep diffusion area is larger than the fourth active area. First and second protrusions of the P-type ion implantation area of the P-type deep diffusion area are provided in areas between the third as well as fourth side surfaces (which lie along the channel width direction) of first active area and corresponding portions of the fourth active area. The present application further discloses a method for manufacturing high-voltage NMOSFET.

Abstract: A display substrate and a display apparatus are provided. The display substrate includes a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, a circuit unit includes a pixel drive circuit and a control line, the pixel drive circuit includes a drive transistor, a first light emitting control transistor, and a second light emitting control transistor, a second electrode of the first light emitting control transistor is connected to a first electrode of the drive transistor, a first electrode of the second light emitting control transistor is connected to a second electrode of the drive transistor, the first light emitting control transistor and the second light emitting control transistor are connected to different control lines; the first light emitting control transistor and the second light emitting control transistor are respectively disposed at two sides of the drive transistor in a unit column direction.

Abstract: An optical lens group for augmented reality (AR) near-eye display includes a primary lens and an auxiliary lens. An image presented by a microdisplay is enlarged by the optical lens group to form a virtual image which can be observed by an eye of a user. A shape of an outermost surface of the optical lens group can be changed to meet requirements of different diopters. The optical lens group has a primary lens mainly used for image information transmission and image enlargement and an auxiliary lens close to at least one surface of the primary lens. The auxiliary lens is arranged on a lower side or an outer side of the primary lens without propagating any image light signal from a micro image display.

Abstract: Methods for treating a cancer comprising administering an ADAR1 inhibitor and a PARP inhibitor are described herein. PARP inhibition enhances tumor sensitivity to ADAR1 inhibition, leading to enhanced cancer cell death. The described combination therapy is effective for treating breast cancers characterized by a loss of p53 and BRCA1 or PTEN, which are typically resistant to PARP inhibition therapy alone.

Abstract: Provided are a display panel and a display apparatus. The display panel includes a base substrate, the base substrate includes a display region and a non-display region surrounding the display region, and the non-display region includes a first bezel region and a second bezel region having a binding region; blocking dams located in the non-display region and arranged surrounding the display region, the blocking dams include a first blocking dam and a second blocking dam, and the first blocking dam is located between the second blocking dam and the display region; and a first flat layer, a second flat layer and a third flat layer located on the base substrate; the second blocking dam includes the first flat layer and the third flat layer in the first bezel region, and the second blocking dam includes the second flat layer and the third flat layer in the second bezel region.

Abstract: The present disclosure discloses a method for fabricating an integrated structure of a metal-gate MOS transistor, which defines a high-resistance MOS device gate structure region in the high-resistance device area and a high-voltage MOS device gate structure region in the high-voltage device area through photolithography, wherein during gate polysilicon etching, the entire high-voltage MOS device gate structure region is retained without forming slots in the MOS device gate structure regions; spacers are formed through self-aligned etching, eliminating the need for a spacers process mask; and the same mask layer is used for both the high-resistance layer etching and the slot etching in the high-voltage MOS device gate structure region.

Abstract: An MV device is disclosed. A gate conductive material layer is segmented into a body gate conductive material layer and two edge gate conductive material layers along a channel length direction. The two edge gate conductive material layers are located on two sides of the body gate conductive material layer and are spaced apart from the body gate conductive material layer by dielectric segmentation structures. The lightly doped drain regions extend under the first side face and the second side face of the gate conductive material layer, to reach under the body gate conductive material layer, such that the channel region becomes located under the body gate conductive material layer; and the edge gate conductive material layers and the dielectric segmentation structures become located above the lightly doped drain regions. The present disclosure also discloses a method for manufacturing an MV device.

Abstract: A display substrate includes a display area and a non-display area that surrounds the display area. The display area includes a plurality of scanning lines extending in a first direction and a plurality of sub-pixels arranged in an array, and the display area includes a first display area and a second display area, wherein the first display area is located at the periphery of the second display area, and the second display area comprises a light-transmitting display area and a transition display area; the transition display area is located on a side face of the light-transmitting display area.

Abstract: The present application discloses a fabrication method for an integrated structure of transistors with different operating voltages. A high-voltage transistor area and a low-voltage transistor area are protected by a retained hard mask layer before a medium-voltage gate oxide layer is grown, so as to avoid additional growth of gate oxide layers above active areas of the high-voltage transistor area and the low-voltage transistor area, thereby avoiding the deterioration of a step height of the low-voltage transistor area due to the subsequent use of a large amount of acid to remove the gate oxide layer additionally grown above the active area of the low-voltage transistor area, and preventing the electrical property and the reliability of a low-voltage device from being subsequently influenced while avoiding the influence of the etching with the large amount of acid on the thickness of a high-voltage gate oxide layer which has already been grown.

Abstract: This application discloses a CIS pixel readout circuit structure. An SG and an SF adopt different transverse thicknesses of spacers. The spacer of the SG adopts a smaller transverse thickness to reduce the parasitic resistance. The spacer of the SF adopts a larger transverse thickness to reduce the GIDL current. In the CIS pixel readout circuit structure according to this application, drain metal plugs are formed on outer sides of both left and right ends of an SF gate structure. The SF and the SG form a T-shaped combined compact structure to achieve equivalent parallel connection of two SF, thus effectively reducing the parasitic resistance of the share active area between the SG and the SF, and simultaneously saving the space area. This application further discloses a method for fabricating a CIS pixel readout circuit structure.

Abstract: Precipitation or scaling may occur when combining produced water from multiple sources, such as when one produced water contains dissolved calcium ions and another produced water contains dissolved sulfate anions. The tendency toward precipitation or scaling may be decreased by treating the produced water containing dissolved sulfate anions. Such methods may comprise: providing a first produced water comprising dissolved sulfate anions; treating the first produced water with a metal salt capable of forming an insoluble metal sulfate, thereby forming a metal sulfate precipitate and a treated produced water; separating the metal sulfate precipitate from the treated produced water; and after separating the metal sulfate precipitate, mixing the treated produced water with at least one second produced water to obtain a mixed produced water, the at least one second produced water containing dissolved calcium ions, and the mixed produced water having a saturation ratio for calcium sulfate of less than 1.

Abstract: Systems and methods include scale control in oilfield produced waters. Thermodynamic data indicative of surface conditions and subterranean conditions of a subterranean region including a well is received, from probes. An acidity of a produced water stream to be disposed in the well is received from a pH meter. A supersaturation degree of the produced water stream to be disposed in the well is determined, by using the thermodynamic data. An amount of carbon dioxide to be injected in the produced water stream to neutralize a scaling risk is determined, by the one or more processors, by using the supersaturation degree and the acidity. An injection of the amount of the carbon dioxide in the produced water stream is triggered to neutralize the scaling risk.

Abstract: A display substrate includes a base substrate (100), a circuit structure layer (20), a light emitting structure layer (4), at least one conductive layer, and at least one capacitance compensation layer (51). The base substrate (100) includes a first display region (A1) and a second display region (A2) at least partially surrounding the first display region (A1). The capacitance compensation layer (51) is located in the first display region (A1) and on a side of the light emitting structure layer (4) close to the base substrate (100). The capacitance compensation layer (51) includes at least one compensation capacitance electrode plate (511). An anode (411) of at least one first light emitting element (13) is electrically connected with the compensation capacitance electrode plate (511) of the capacitance compensation layer (51).

Abstract: The technology relates to a method of treating inorganic scale in a well that is drilled in a heterogeneous reservoir matrix. A heterogeneous reservoir matrix has varying permeabilities. The varying permeabilities can cause a change in the shear rate as a fluid flows through it. A shear thinning nanofluid that includes a nanoparticle functionalized with a scale inhibitor and an aqueous solvent is injected into the heterogeneous reservoir matrix. The shear thinning behavior of the nanofluid causes a self-diversion of the nanofluid from a high permeability zone towards the low permeability zone due to a change in the viscosities. The self-diversion causes the scale inhibitor to be delivered to the low permeability zone.

Abstract: A display substrate includes a base substrate, multiple pixel circuits, multiple first light emitting elements, multiple second light emitting elements, and at least one first signal line extending along the first direction. The base substrate includes a first display area and at least one second display area. The first display area at least partially surrounds the second display area. A first signal line is located in the first display area, and is electrically connected with multiple pixels circuits of the first display area. The first signal line is partitioned into at least two first sub-signal lines by at least one second display area. Adjacent first sub-signal lines of the at least two first sub-signal lines are electrically connected by a first connector line. At least part of line segments of the first connector line are located between the multiple first pixel circuits.