Abstract: The present invention discloses a waveguide element manufacturing method based on an injection molding process, and a waveguide element produced by this method. The waveguide element includes: a bevel-toothed spectroscopic element, a primary mirror, and a compensation mirror; wherein, the bevel-toothed spectroscopic element is a bevel-toothed thin film formed by a plurality of transmission films and a plurality of spectroscopic films that are alternately arranged; the primary mirror, similar in size to a diopter lens, features a groove and a tooth tip structure on the bottom surface of the groove; the compensation mirror, matching the size of the groove, and has a tooth tip structure on the side facing the groove; and the compensation mirror causes the bevel-toothed spectroscopic element to be sandwiched between the tooth tip structure of the groove and the tooth tip structure of the compensation mirror.

Abstract: This invention relates to an optical lens assembly and glasses for users to achieve peripheral myopic defocus, which can present a positively defocused image in the user's peripheral field of vision while the user observes a real scene, and simultaneously achieving myopia control and refractive correction. The optical lens assembly consists of a first lens, a second lens, and a projector; the first lens has a plurality of radially distributed defocus units; the image light of the predetermined image enters a defocus unit after passing through the projector, propagates via total internal reflection and is reflected at the beam splitting exit surface located near the center of the first lens, and then exits as converging light, which can enter the human eye at the exit pupil and form a defocused image in the peripheral field of vision in front of the retina.

Abstract: A display substrate includes a first display region and a second display region located at at least one side of the first display region, a light transmittance of the first display region is greater than that of the second display region. The first display region is provided with first light emitting devices, the second display region is provided with first pixel driving circuits, second pixel driving circuits, and second light emitting devices. The first pixel driving circuit drives the first light emitting device, and the second pixel driving circuit drives the second light emitting device. The second display region further includes initialization signal lines respectively connected with the first pixel driving circuits and the second pixel driving circuits and apply initialization signals thereto. The first pixel driving circuit and the second pixel driving circuit are respectively connected to different initialization signal lines.

Abstract: A method for manufacturing an FDSOI device is provided. When a first doped epitaxial layer is formed, sidewalls of a PMOS gate structure include a first spacer and a second spacer. By providing two spacers, the distance between the first doped epitaxial layer and the PMOS gate structure is increased, a protective layer is formed in PMOS gate to cover the first doped epitaxial layer and fill the gap from removing the second spacer, thereby increasing the distance between the PMOS gate structure and the contact hole of the source or drain. This prevents bridging and shorting between the gate and the contact hole of the source or drain, thus ensuring product yield and reliability. Moreover, the second spacer is removed before forming a second doped epitaxial layer on the NMOS gate structure, so as not to increase the distance between the second doped epitaxial layer and the NMOS gate structure.

Abstract: A display substrate and a display device are provided. In the display substrate, a first signal line transmitting a first scan signal extends along a first direction and a second signal line transmitting a data signal extends along a second direction; the data writing transistor transmits the data signal to the driving transistor under control of the first scan signal, the first scan signal is transmitted on the first signal line, and the data signal is transmitted on the second signal line; the driving transistor controls magnitude of a driving current according to the data signal; the channel region at least partially overlaps with the gate electrode; a planar shape of the channel region of the driving transistor is a strip shape extending along the second direction; the light emitting device receives the driving current and is driven by the driving current to emit light.

Abstract: As integrated circuit densities increase, electromagnetic (EM) coupling between closely-spaced inductor-capacitor (LC) voltage-controlled oscillators (VCOs) can degrade phase noise performance in multi-lane transceivers. To address this, a reconfigurable multi-core LC VCO architecture is proposed that mitigates EM coupling through a programmable interconnection topology. Two or more parallel LC cores are coupled via transmission-gate switches, enabling multiple operating modes: single-core (low-power), multi-core direct connection (victim immunity), and multi-core cross-coupling connection (aggressor suppression). Parallel coupling of LC cores can preserve inductor Q-factor while achieving significant EM field cancellation. The architecture supports per-lane independent configuration in multi-lane transceiver systems, enabling simultaneous optimization of power consumption, phase noise, and chip-level EM compatibility.

Abstract: Embodiments of the present disclosure provide a touch substrate, a touch display panel and a touch display apparatus. The touch display panel includes: a base substrate; a touch electrode layer on the base substrate and in a touch display region, the touch electrode layer including touch electrodes in the same layer and insulated from each other; and touch leads on the base substrate, each touch lead is electrically connected to a corresponding one touch electrode, some touch leads extend from the touch display region through the first bending region to the first binding region, and are bent to the back of the touch display panel in the first bending region, and the other touch leads extend from the touch display region through the second bending region to the second binding region, and are bent to the back of the touch display panel in the second bending region.

Abstract: A semiconductor structure containing an RRAM and a method for preparing the same are provided, which integrate the fabrication of the RRAM into the front-end-of-line (FEOL) process. This requires only one additional photomask to create the bottom electrode of the RRAM compared to standard HKMG process. Furthermore, the top electrode of the RRAM is formed simultaneously with the high-resistance layer during the FEOL process. This approach significantly reduces the manufacturing cost of the RRAM while also minimizing device thickness and shrinking the overall device size.

Abstract: Provided are a method for constructing a sequencing library based on a DNA sample and use. The method includes: digesting the DNA sample with endonuclease to obtain a DNA sample with single-strand nicks; polymerizing the DNA sample with the single-strand nicks by using polymerase, dATP, dTTP, dGTP, and methylated dCTP to obtain a hybrid DNA, the hybrid DNA including two reversely complementary strands, where a 5?-end of each strand is an original sequence of the DNA sample, a 3?-end of each strand is a synthetic sequence, and all bases C in the 3?-end of each strand are methylated; subjecting the hybrid DNA to bisulfite treatment or other treatment to obtain converted hybrid DNA; and amplifying the converted hybrid DNA to obtain the sequencing library. Thus, the method can be used for whole genome bisulfite sequencing or multiplex PCR targeted sequencing and probe capture sequencing.

Abstract: A method is provided for reducing scale inhibitor demand for protecting an electrical submersible pump (ESP) for downhole service in a wellbore. The method includes performing an SIS treatment through the ESP. The ESP includes a motor comprising a housing that houses a motor stator and a pump intake coupled to a pump stage. The pump stage includes an impeller; and a diffuser. The pump stage is coupled to the motor stator. A hydrophobic coating substantially covers each surface of the motor, motor stator, housing, pump stage, impeller, and diffuser, that is in direct contact with fluids in the wellbore. The method further includes monitoring the concentration of the scale inhibitor in the produced fluids; and repeating the SIS treatment through the ESP when the scale inhibitor concentration falls below a minimum effective dose (MED), wherein the MED is decreased by the hydrophobic coating by about 20% to about 80%.

Abstract: A display panel has a display region and a peripheral region at least partially surrounding the display region, where the display region includes a secondary display region and a main display region located on at least one side of the secondary display region, and the secondary display region includes a light-transmitting region and a circuit region located on at least one side of the light-transmitting region. The display panel includes: a driving backplane, including multiple pixel circuits distributed in an array and multiple first reset signal lines; and multiple light-emitting devices, located on one side of the driving backplane, and including first light-emitting devices located in the main display region and the circuit region, and a second light-emitting device located in the light-transmitting region; the first light-emitting devices are connected to the first pixel circuits, and the second light-emitting device is connected to the second pixel circuit.

Abstract: A method and system for constructing sequencing library, includes: obtaining a transformed DNA sample with a universal sequence; performing amplification using a first specific primer located upstream of the target region and a first universal primer at least partially matching or overlapping the universal sequence; and performing amplification using a second specific primer, a second universal primer and a tagged primer. The second specific primer is located downstream of the first specific primer and upstream of the target region, the second universal primer overlaps at least a partial sequence of the second specific primer, and the tagged primer overlaps a partial sequence of the first universal primer. Alternatively, the second specific primer is located downstream of the target region, the second universal primer overlaps at least a partial sequence of the first specific primer, and the tagged primer overlaps a partial sequence of the second specific primer.

Abstract: A display substrate and a display device are provided. In the display substrate, the driving transistor includes an active pattern and a gate electrode, the active pattern includes a channel region, and an orthographic projection of the channel region on the base substrate at least partially overlaps with an orthographic projection of the gate electrode on the base substrate; the storage capacitor includes a first electrode plate and a second electrode plate. The first electrode plate is electrically connected with the gate electrode of the driving transistor; an orthographic projection of the second electrode plate on the base substrate at least partially overlaps with an orthographic projection of the first electrode plate on the base substrate, and does not overlap with an orthographic projection of the channel region of the driving transistor on the base substrate.

Abstract: The display substrate includes: a base substrate having a display region and a peripheral region surrounding the display region, the peripheral region including a pad region on one side of the display region; first selection units on the base substrate and in the peripheral region, each first selection unit including an input end and output ends; pads in the pad region; adapter lines in the display region, one end of each adapter line being connected to a corresponding pad, and the other end being connected to the input end of a corresponding first selection unit; first data lines in the display region; and data lead-in lines in the display region, one end of each data lead-in line being connected to the output end of the corresponding first selection unit, and the other end being connected to the corresponding first data line.

Abstract: The present disclosure provides a method of reducing damage to floating gate polysilicon during etching. The method includes: forming a floating gate thicker than 400 ? on a tunneling oxide layer, forming a first region including a portion of the floating gate from the bottom to the 400 ? thickness, and forming a second region including a portion of the floating gate above the 400 ? thickness; performing carbon-doping deposition into the first region of the floating gate, wherein a carbon doping process is arranged to be in gradually decreasing flow rate in a direction from the bottom of the floating gate up to the 400 ? thickness, and the second region is not subjected to carbon doping; forming a stack layer including silicon oxide, silicon nitride, and silicon oxide on the floating gate; and forming a control gate on the stack layer.

Abstract: A display substrate and a manufacturing method therefor, and a display apparatus.

Abstract: Disclosed are a display panel and a display apparatus, the display panel includes a display region, the display region includes a light transmitting display region and a conventional display region located on at least one side of the light transmitting display region, the conventional display region includes a first region, a second region, and a third region; at least one circuit unit of the first region in the conventional display region is connected with a light emitting device in the light transmitting display region, at least one circuit unit of the third region in the conventional display region includes a data connection line, a second high-voltage power supply line includes a first sub-high-voltage power supply line and a second sub-high-voltage power supply line connected with each other, the second sub-high-voltage power supply line is located on a side of the first sub-high-voltage power supply line away from the base substrate.

Abstract: A method for treating scale deposits. The method including feeding a scale inhibitor composition through a wellbore positioned in a portion of a subterranean formation to contact a scale deposit. The scale inhibitor composition includes a solvent, a scale inhibitor and an additive. The scale inhibitor is present in an amount from 25 wt. % to 75 wt. %, based on a total weight of the scale inhibitor composition, and the additive is present in an amount from 0.1 wt. % to 10 wt. %, based on the total weight of the scale inhibitor composition. The additive includes an amino polycarboxylic acid.

Abstract: A display substrate and a display device are provided. The display substrate includes a base substrate, a conductive structure and a first inorganic layer on the base substrate. The base substrate includes a first region and a second region; the conductive structure is in the first region and the second region; the first inorganic layer is on a side of the conductive structure away from the base substrate and in the first region and the second region. In at least a part of the first region, an insulating layer is disposed between the first inorganic layer and the conductive structure, and in at least a part of the second region, the first inorganic layer is in contact with a surface of the conductive structure.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The method comprises: providing a semiconductor structure including a first well region and a second well region, and forming a first and a second doping regions on an upper surface of the first well region; forming a groove on the first well region crossing from the first and to the second doping regions, with two sidewalls of the groove extending into the first and second doping regions; filing the groove to form a gate dielectric layer, and simultaneously forming a first dummy gate structure and a second dummy gate structure; simultaneously forming a first source region, a first drain region, a second source region, and a second drain region; replacing dummy gate layers within the first and second dummy gate structures with a first metal gate layer and a second metal gate layer, respectively; and forming electrodes.