Abstract: A method for treating scale deposits. The method including feeding a scale inhibitor composition through a wellbore positioned in a portion of a subterranean formation to contact a scale deposit. The scale inhibitor composition includes a solvent, a scale inhibitor and an additive. The scale inhibitor is present in an amount from 25 wt. % to 75 wt. %, based on a total weight of the scale inhibitor composition, and the additive is present in an amount from 0.1 wt. % to 10 wt. %, based on the total weight of the scale inhibitor composition. The additive includes an amino polycarboxylic acid.

Abstract: A display substrate and a display device are provided. The display substrate includes a base substrate, a conductive structure and a first inorganic layer on the base substrate. The base substrate includes a first region and a second region; the conductive structure is in the first region and the second region; the first inorganic layer is on a side of the conductive structure away from the base substrate and in the first region and the second region. In at least a part of the first region, an insulating layer is disposed between the first inorganic layer and the conductive structure, and in at least a part of the second region, the first inorganic layer is in contact with a surface of the conductive structure.

Abstract: A semiconductor device and a manufacturing method thereof are provided. The method comprises: providing a semiconductor structure including a first well region and a second well region, and forming a first and a second doping regions on an upper surface of the first well region; forming a groove on the first well region crossing from the first and to the second doping regions, with two sidewalls of the groove extending into the first and second doping regions; filing the groove to form a gate dielectric layer, and simultaneously forming a first dummy gate structure and a second dummy gate structure; simultaneously forming a first source region, a first drain region, a second source region, and a second drain region; replacing dummy gate layers within the first and second dummy gate structures with a first metal gate layer and a second metal gate layer, respectively; and forming electrodes.

Abstract: The present disclosure provides a method for manufacturing an embedded high-voltage HKMG semiconductor device. A hard mask layer is first formed before forming a well region of a first-conductivity-type doped device and a well region of a second-conductivity-type doped device, an opening in the hard mask layer is formed in the steps of forming the well region of the first-conductivity-type doped device and the well region of the second-conductivity-type doped device, and then the hard mask layer serves as a barrier layer to etch the medium-voltage device region, eliminating the need for defining an active area recess etching in the medium-voltage device region, thereby reducing the number of photomasks and lowering costs.

Abstract: A display substrate and a display device are provided. In the display substrate, the driving transistor includes an active pattern and a gate electrode, the active pattern includes a channel region, and an orthographic projection of the channel region on the base substrate at least partially overlaps with an orthographic projection of the gate electrode on the base substrate; the storage capacitor includes a first electrode plate and a second electrode plate. The first electrode plate is electrically connected with the gate electrode of the driving transistor; an orthographic projection of the second electrode plate on the base substrate at least partially overlaps with an orthographic projection of the first electrode plate on the base substrate, and does not overlap with an orthographic projection of the channel region of the driving transistor on the base substrate.

Abstract: A produced water stream that includes a kinetic hydrate inhibitor (KHI) flows towards a water oil separator (WOSEP). The WOSEP removes the large oil droplets and total suspended solids and discharges the produced water stream with or without an additional pretreatment step to a membrane separation unit. The membrane separation unit filters the produced water stream to form a permeate stream and a retentate stream. The retentate stream includes the concentrated KHI which can be recovered and regenerated for reuse as a treatment chemical in the produced water stream. In some cases, the retentate stream is filtered a second time using another membrane separation unit to increase the KHI recovery by concentrating it in a second retentate stream formed from the second filtration. The KHI can be reformulated using alcohols and/or water to regenerate the KHI molecules for reuse, which are chemically stable.

Abstract: A display substrate includes a first display region and a second display region located at at least one side of the first display region, a light transmittance of the first display region is greater than that of the second display region. The first display region is provided with first light emitting devices, the second display region is provided with first pixel driving circuits, second pixel driving circuits, and second light emitting devices. The first pixel driving circuit drives the first light emitting device, and the second pixel driving circuit drives the second light emitting device. The second display region further includes initialization signal lines respectively connected with the first pixel driving circuits and the second pixel driving circuits and apply initialization signals thereto. The first pixel driving circuit and the second pixel driving circuit are respectively connected to different initialization signal lines.

Abstract: Described herein is a composition which includes a foaming agent, and one or more of an iron sulfide dissolver and a corrosion inhibitor. The composition is capable of reducing a bulk density and hydrostatic pressure of a fluid in a low-pressure gas well. Also described herein are methods of removing an iron sulfide scale from a low-pressure gas well using the composition.

Abstract: Methods may comprise providing a corrosion inhibitor composition comprising a dipyrazolopyridine of about 0.1 wt % to about 5 wt % concentration based on a total weight of the corrosion inhibitor composition; a long-chain amine of about 0.1 wt % to about 5 wt % concentration based on the total weight of the corrosion inhibitor composition; a thiourea of about 0.1 wt % to about 5 wt % concentration based on the total weight of the corrosion inhibitor composition; a thiazole of about 0.1 wt % to about 5 wt % concentration based on the total weight of the corrosion inhibitor composition; and a surfactant of about 0.1 wt % to about 5 wt % concentration based on the total weight of the corrosion inhibitor composition; contacting a metal surface with the corrosion inhibitor composition; and allowing the corrosion inhibitor composition to interact with the metal surface so as to inhibit corrosion of the metal surface.

Abstract: The application discloses a process integration method for improving leakage in MV devices, comprising: step I: forming gate structures, step II: depositing a first spacer material layer, step III: forming an additional spacer material layer, step IV: forming a first mask layer to cover an MV device formation region and open an LV device formation region, step V: performing an isotropic first etching to remove the additional spacer material layer from the LV device formation region, step VI: performing an anisotropic second etching to form a first layer of spacers of the low voltage region, step VII: forming a second mask layer to open the MV device formation region and to cover the LV device formation region, step VIII: performing an anisotropic third etching to form a first layer of spacers of the medium voltage region and additional spacers, and step IX: depositing and etching a second spacer material layer.

Abstract: A method for treating scale includes feeding a pre-flush fluid into a portion of a subterranean formation via a wellbore. The method includes feeding an inhibitor main pill fluid into the portion of the subterranean formation via the wellbore after the pre-flush fluid, wherein the inhibitor main pill fluid comprises a scale inhibitor. The method includes feeding an overflush fluid into the portion of the subterranean formation via the wellbore after the inhibitor main pill fluid, wherein the overflush fluid comprises one or more surfactant. The method includes shutting in the pre-flush fluid, the inhibitor main pill fluid, and the overflush fluid within the portion of the subterranean formation for a pre-determined period of time.

Abstract: The present disclosure provides a display substrate and a display device. A display region of the display substrate includes a first display region and a second display region arranged opposite to each other, a peripheral region includes a notch arranged between the first display region and the second display region. A scanning line in the display substrate includes a first scanning member, a second scanning member and a compensation scanning member, the first scanning member is arranged in the first display region, the second scanning member is arranged in the second display region, and at least a part of the compensation scanning member is arranged in the notch. The compensation scanning member is coupled to the first scanning member and the second scanning member. An orthogonal projection of the compensation scanning member onto the base substrate overlaps with an orthogonal projection of a peripheral power line onto the base substrate.

Abstract: Provided are a display panel and a display device. The display panel includes: light-emitting elements and pixel circuits. The pixel circuits include a plurality of groups of pixel circuits; at least one group of pixel circuits includes a plurality of first-type pixel circuits and a plurality of second-type pixel circuits; at least one second-type pixel circuit is connected to at least one second region light-emitting element through one conductive line; the conductive lines include a plurality of first conductive wires and a plurality of second conductive wires; and in at least one group of light-emitting elements and at least one group of pixel circuits, a plurality of first pixel circuits connected to a plurality of first light-emitting elements are closer to a second display region than each of a plurality of second pixel circuits connected to a plurality of second light-emitting elements.

Abstract: The present application discloses a high-voltage NMOSFET. The P-type well area is formed in the first active area, while the first and second source/drain areas are respectively formed in second and third active areas. The fourth active area is disposed to surround peripheral sides of first to third active areas. The P-type deep diffusion area and a substrate contact area are formed in the fourth active area. The P-type ion implantation area of P-type deep diffusion area is larger than the fourth active area. First and second protrusions of the P-type ion implantation area of the P-type deep diffusion area are provided in areas between the third as well as fourth side surfaces (which lie along the channel width direction) of first active area and corresponding portions of the fourth active area. The present application further discloses a method for manufacturing high-voltage NMOSFET.

Abstract: A display substrate and a display apparatus are provided. The display substrate includes a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, a circuit unit includes a pixel drive circuit and a control line, the pixel drive circuit includes a drive transistor, a first light emitting control transistor, and a second light emitting control transistor, a second electrode of the first light emitting control transistor is connected to a first electrode of the drive transistor, a first electrode of the second light emitting control transistor is connected to a second electrode of the drive transistor, the first light emitting control transistor and the second light emitting control transistor are connected to different control lines; the first light emitting control transistor and the second light emitting control transistor are respectively disposed at two sides of the drive transistor in a unit column direction.

Abstract: An optical lens group for augmented reality (AR) near-eye display includes a primary lens and an auxiliary lens. An image presented by a microdisplay is enlarged by the optical lens group to form a virtual image which can be observed by an eye of a user. A shape of an outermost surface of the optical lens group can be changed to meet requirements of different diopters. The optical lens group has a primary lens mainly used for image information transmission and image enlargement and an auxiliary lens close to at least one surface of the primary lens. The auxiliary lens is arranged on a lower side or an outer side of the primary lens without propagating any image light signal from a micro image display.

Abstract: Methods for treating a cancer comprising administering an ADAR1 inhibitor and a PARP inhibitor are described herein. PARP inhibition enhances tumor sensitivity to ADAR1 inhibition, leading to enhanced cancer cell death. The described combination therapy is effective for treating breast cancers characterized by a loss of p53 and BRCA1 or PTEN, which are typically resistant to PARP inhibition therapy alone.

Abstract: Provided are a display panel and a display apparatus. The display panel includes a base substrate, the base substrate includes a display region and a non-display region surrounding the display region, and the non-display region includes a first bezel region and a second bezel region having a binding region; blocking dams located in the non-display region and arranged surrounding the display region, the blocking dams include a first blocking dam and a second blocking dam, and the first blocking dam is located between the second blocking dam and the display region; and a first flat layer, a second flat layer and a third flat layer located on the base substrate; the second blocking dam includes the first flat layer and the third flat layer in the first bezel region, and the second blocking dam includes the second flat layer and the third flat layer in the second bezel region.

Abstract: The present disclosure discloses a method for fabricating an integrated structure of a metal-gate MOS transistor, which defines a high-resistance MOS device gate structure region in the high-resistance device area and a high-voltage MOS device gate structure region in the high-voltage device area through photolithography, wherein during gate polysilicon etching, the entire high-voltage MOS device gate structure region is retained without forming slots in the MOS device gate structure regions; spacers are formed through self-aligned etching, eliminating the need for a spacers process mask; and the same mask layer is used for both the high-resistance layer etching and the slot etching in the high-voltage MOS device gate structure region.

Abstract: An MV device is disclosed. A gate conductive material layer is segmented into a body gate conductive material layer and two edge gate conductive material layers along a channel length direction. The two edge gate conductive material layers are located on two sides of the body gate conductive material layer and are spaced apart from the body gate conductive material layer by dielectric segmentation structures. The lightly doped drain regions extend under the first side face and the second side face of the gate conductive material layer, to reach under the body gate conductive material layer, such that the channel region becomes located under the body gate conductive material layer; and the edge gate conductive material layers and the dielectric segmentation structures become located above the lightly doped drain regions. The present disclosure also discloses a method for manufacturing an MV device.