Abstract: A system and method are provided for adding chemicals to a produced fluid in a wellbore. An exemplary system includes a gauge hanger and a permeable container. The permeable container includes a solid cylindrical body, end caps placed at each end of the solid cylindrical body, and holes disposed proximate to each end of the permeable container, wherein the holes allow the produced fluid to flow through the permeable container from one end of the permeable container to the opposite end of the permeable container. The system further includes a well treatment chemical disposed in the permeable container.

Abstract: An array substrate is provided. The array substrate includes a pixel driving circuit having a first reset transistor and a second reset transistor. At least a portion of a gate electrode of a first reset transistor in a present row of pixel driving circuits and at least a portion of a gate electrode of a second reset transistor in a previous row of pixel driving circuits are parts of a unitary structure. The gate electrode of the first reset transistor in the present row of pixel driving circuits and the gate electrode of the second reset transistor in the previous row of pixel driving circuits are arranged along a direction non-parallel to an extension direction of reset control signal lines.

Abstract: A display substrate and a display panel are provided. The display substrate includes a base substrate; a display region, on the base substrate and including a plurality of sub-pixels arranged in an array; each of the plurality of sub-pixels includes a light-emitting element and a pixel circuit that drives the light-emitting element to emit light, and the pixel circuit includes a driving sub-circuit, a data writing sub-circuit, a threshold compensation sub-circuit, and a reset sub-circuit; the reset sub-circuit includes a first reset transistor and a second reset transistor, the threshold compensation sub-circuit includes a threshold compensation transistor and a storage capacitor, an orthographic projection of the second reset transistor on the base substrate is between an orthographic projection of the first reset transistor on the base substrate and an orthographic projection of the threshold compensation transistor on the base substrate.

Abstract: Disclosed are a display substrate, a preparation method thereof, and a display device. The display substrate includes a display region and a bonding region on one side of the display region. The bonding region at least includes a lead area. The display region includes a plurality of data lines and a plurality of data fanout lines. The lead area includes a plurality of lead wires. Orthographic projections of the plurality of data lines and the plurality of data fanout lines on a plane of the display substrate are at least partially overlapped. A first end of at least one data fanout line is connected to the lead wire, and a second end of the at least one data fanout line extends in a direction away from the lead area, to be connected to the data line.

Abstract: Systems and methods for generating and using a water filtration media containing date seed powder are provided. The method of generating the date seed powder for use in a water treatment system includes drying the date seeds, cleaning and removing the date seed envelopes, grinding the date seeds, and segregating the date seed powder according to a predetermined particle size. The method of using the date seed powder to treat water includes using a treatment tank with a date seed media bed layer, introducing water, and filtering suspended solids from the water stream using the date seed media bed layer. The system utilizing the date seed media bed layer includes a treatment tank, a date seed media bed layer, water inlets and outlets, backwashing equipment, and media support screens.

Abstract: A display substrate and a display device are provided. The display substrate includes: display region and peripheral region surrounding display region; display region includes at least one group of pixel regions including first pixel region and two second pixel regions, first pixel region is between two second pixel regions along first direction; peripheral region includes fan-out region on a side of first pixel region in second direction, second direction intersects with first direction; in display substrate, at least part of first data line is in first pixel region, first data line includes a part extending along second direction; at least part of second data line is in second pixel region, second data line includes a part extending along second direction; connecting line is coupled to corresponding second data line, connecting line includes a portion in first pixel region, connecting line extends from first pixel region to fan-out region.

Abstract: A device for treating water supply wells includes a gauge hanger with an attachment piece at a bottom end of the gauge hanger and at least one permeable container connected to the gauge hanger via the attachment piece. The permeable container includes a top portion with top openings, a bottom portion with bottom openings, and a connecting portion connecting the top portion to the bottom portion. A method for treating a water supply well includes placing an encapsulated treatment chemical in at least one permeable container and placing a device in the water supply well where the device includes a gauge hanger and the at least one permeable container. The method may include treating a water supply by flowing produced fluid through the bottom openings and top openings of the permeable container which introduces the treatment chemical into the water supply.

Abstract: A method of treating a subterranean formation to protect against solid deposition and corrosion attack includes flowing a pre-flush fluid to a specified downhole location within the subterranean formation. A main treatment fluid is flowed to the specified downhole location. The main treatment fluid includes a scale inhibitor configured to inhibit formation of scale within the subterranean formation. At a subsurface level, an overflush foam is generated. The overflush foam includes an aqueous fluid and a gas. The overflush foam is shear thinning and non-Newtonian. The overflush foam is flowed to the specified downhole location.

Abstract: The present application discloses a method for making an active area air gap, comprising: step 1, performing word line etching to form a plurality of word line structures on a semiconductor substrate, wherein each word line structure spans each field oxide and each active area; step 2, forming a protective spacer on a side surface of the word line structure in a self-aligned manner; step 3, etching the field oxide by means of isotropic etching, so as to lower the top surfaces of the field oxides within and outside a coverage area of the word line structure and thus form an active area air gap between the active areas, wherein the word line structure spans the active area air gap; and step 4, removing the protective spacer.

Abstract: A system and method is provided for reducing scale inhibitor demand for protecting an electrical submersible pump (ESP) for downhole service in a wellbore. An exemplary system includes a motor including a housing that houses a motor stator. The system also includes a pump intake coupled to a pump stage, wherein the pump stage includes an impeller and a diffuser, wherein the pump stage is operatively coupled to the motor stator. A substantially hydrophobic coating substantially covers each surface of the motor, motor stator, housing, pump stage, impeller, and diffuser, that is in direct contact with fluids in the wellbore.

Abstract: A display substrate and a display device.

Abstract: A display substrate includes a first display region and a second display region located at at least one side of the first display region, a light transmittance of the first display region is greater than that of the second display region. The first display region is provided with first light emitting devices, the second display region is provided with first pixel driving circuits, second pixel driving circuits, and second light emitting devices. The first pixel driving circuit drives the first light emitting device, and the second pixel driving circuit drives the second light emitting device. The second display region further includes initialization signal lines respectively connected with the first pixel driving circuits and the second pixel driving circuits and apply initialization signals thereto. The first pixel driving circuit and the second pixel driving circuit are respectively connected to different initialization signal lines.

Abstract: Display substrate and display device are provided. The display substrate includes: a base and sub-pixels thereon, the sub-pixel includes a light-emitting element and a sub-pixel driving circuit including a driving transistor and a compensation transistor; the compensation transistor has a first electrode coupled to a second electrode of the driving transistor, and a second electrode coupled to a gate electrode of the driving transistor; the compensation transistor includes a gate electrode and an active layer including a channel portion; the display substrate includes a pixel definition layer and shielding patterns, at least a portion of the shielding pattern is located between the pixel definition layer and the gate electrode of the compensation transistor, and an orthographic projection of the shielding pattern onto the base at least partially overlaps with an orthographic projection of corresponding channel portion of the compensation transistor onto the base.

Abstract: This application discloses a CIS pixel readout structure. An SF and an SG adopt an asymmetric spacer structure, so that the pitch from a lower end of a source metal plug of the SG to SG gate poly can be reduced while keeping the pitch from a lower end of a drain metal plug of the SF to SF gate poly unchanged, thus reducing the pitch from a drain connecting point of the SF to a source connecting point of the SG. Since a source of the SG is not connected with working voltage and it is not influenced by leakage, not only can GIDL current be maintained, but also parasitic resistance can be reduced. Without changing its effective size, it can reduce the parasitic resistance effect while reducing the area of a combined structure of the SF and the SG.

Abstract: This application discloses a CIS pixel readout circuit structure. An SG and an SF adopt different transverse thicknesses of spacers. The spacer of the SG adopts a smaller transverse thickness to reduce the parasitic resistance. The spacer of the SF adopts a larger transverse thickness to reduce the GIDL current. In the CIS pixel readout circuit structure according to this application, drain metal plugs are formed on outer sides of both left and right ends of an SF gate structure. The SF and the SG form a T-shaped combined compact structure to achieve equivalent parallel connection of two SF, thus effectively reducing the parasitic resistance of the share active area between the SG and the SF, and simultaneously saving the space area. This application further discloses a method for fabricating a CIS pixel readout circuit structure.

Abstract: The present disclosure discloses a method for manufacturing a NOR flash. The drain area groove and the peripheral isolation grooves are first formed and filled with the trench isolation oxide, followed by the formation of the source area groove, and then the SiH4 layer is deposited. Due to the poor filling property of SiH4, the air gap may be formed at the source area groove with a small gap, and at this time, the drain area groove in the drain area of the storage area and the peripheral isolation groove in the logic area both have been filled and thus are unaffected. The method for manufacturing a NOR flash of the present disclosure allows the formation of the source air gap of the NOR flash based on a post-source preparation process and good filling of the drain, reducing the coupling effect between the source polysilicon gates.

Abstract: Embodiments of the present disclosure provide a touch substrate, a touch display panel and a touch display apparatus. The touch display panel includes: a base substrate; a touch electrode layer on the base substrate and in a touch display region, the touch electrode layer including touch electrodes in the same layer and insulated from each other; and touch leads on the base substrate, each touch lead is electrically connected to a corresponding one touch electrode, some touch leads extend from the touch display region through the first bending region to the first binding region, and are bent to the back of the touch display panel in the first bending region, and the other touch leads extend from the touch display region through the second bending region to the second binding region, and are bent to the back of the touch display panel in the second bending region.

Abstract: A system and a method for implementing a squeeze treatment to apply a scale inhibitor in a wellbore are provided. An exemplary method includes mixing a scale inhibitor pill. The scale inhibitor pill includes polyamino polyether methylene phosphonic acid (PAPEMP) and amino trimethylene phosphonic acid (ATMP). Pre-flush chemicals are injected into the wellbore. The scale inhibitor pill is injected into the wellbore. An over flush is injected into the wellbore. The wellbore is shut in for a target period of time and normal production is resumed.

Abstract: Provided are a display substrate and a display device. The display substrate includes a base substrate, and a driving circuit layer and a light-emitting device layer on the base substrate. The display substrate includes a light-transmitting display area and a normal display area, the normal display area surrounds at least a portion of the light-transmitting display area. The normal display area includes multiple normal driving circuits and multiple dummy driving circuits; some dummy driving circuit are used for driving light-emitting devices located in the light-transmitting display area. The display substrate further includes multiple normal data lines coupled to the normal driving circuits; at least one normal data line is coupled to a data signal input terminal through a data lead; an orthographic projection of the data lead onto the base substrate at least partially overlaps an orthographic projection of the dummy driving circuit onto the base substrate.

Abstract: The present disclosure relates to the technical field of display, and provides a display panel and a display apparatus. The display panel includes a display area and a fan-out area located in the display area. The display panel further includes: a base substrate; a plurality of data lines located in the display area; a plurality of first data fan-out lines located in the fan-out area; and a plurality of second data fan-out lines located in the fan-out area.