Abstract: An optical lens group for augmented reality (AR) near-eye display includes a primary lens and an auxiliary lens. An image presented by a microdisplay is enlarged by the optical lens group to form a virtual image which can be observed by an eye of a user. A shape of an outermost surface of the optical lens group can be changed to meet requirements of different diopters. The optical lens group has a primary lens mainly used for image information transmission and image enlargement and an auxiliary lens close to at least one surface of the primary lens. The auxiliary lens is arranged on a lower side or an outer side of the primary lens without propagating any image light signal from a micro image display.

Abstract: Methods for treating a cancer comprising administering an ADAR1 inhibitor and a PARP inhibitor are described herein. PARP inhibition enhances tumor sensitivity to ADAR1 inhibition, leading to enhanced cancer cell death. The described combination therapy is effective for treating breast cancers characterized by a loss of p53 and BRCA1 or PTEN, which are typically resistant to PARP inhibition therapy alone.

Abstract: Provided are a display panel and a display apparatus. The display panel includes a base substrate, the base substrate includes a display region and a non-display region surrounding the display region, and the non-display region includes a first bezel region and a second bezel region having a binding region; blocking dams located in the non-display region and arranged surrounding the display region, the blocking dams include a first blocking dam and a second blocking dam, and the first blocking dam is located between the second blocking dam and the display region; and a first flat layer, a second flat layer and a third flat layer located on the base substrate; the second blocking dam includes the first flat layer and the third flat layer in the first bezel region, and the second blocking dam includes the second flat layer and the third flat layer in the second bezel region.

Abstract: The present disclosure discloses a method for fabricating an integrated structure of a metal-gate MOS transistor, which defines a high-resistance MOS device gate structure region in the high-resistance device area and a high-voltage MOS device gate structure region in the high-voltage device area through photolithography, wherein during gate polysilicon etching, the entire high-voltage MOS device gate structure region is retained without forming slots in the MOS device gate structure regions; spacers are formed through self-aligned etching, eliminating the need for a spacers process mask; and the same mask layer is used for both the high-resistance layer etching and the slot etching in the high-voltage MOS device gate structure region.

Abstract: An MV device is disclosed. A gate conductive material layer is segmented into a body gate conductive material layer and two edge gate conductive material layers along a channel length direction. The two edge gate conductive material layers are located on two sides of the body gate conductive material layer and are spaced apart from the body gate conductive material layer by dielectric segmentation structures. The lightly doped drain regions extend under the first side face and the second side face of the gate conductive material layer, to reach under the body gate conductive material layer, such that the channel region becomes located under the body gate conductive material layer; and the edge gate conductive material layers and the dielectric segmentation structures become located above the lightly doped drain regions. The present disclosure also discloses a method for manufacturing an MV device.

Abstract: A display substrate includes a display area and a non-display area that surrounds the display area. The display area includes a plurality of scanning lines extending in a first direction and a plurality of sub-pixels arranged in an array, and the display area includes a first display area and a second display area, wherein the first display area is located at the periphery of the second display area, and the second display area comprises a light-transmitting display area and a transition display area; the transition display area is located on a side face of the light-transmitting display area.

Abstract: The present application discloses a fabrication method for an integrated structure of transistors with different operating voltages. A high-voltage transistor area and a low-voltage transistor area are protected by a retained hard mask layer before a medium-voltage gate oxide layer is grown, so as to avoid additional growth of gate oxide layers above active areas of the high-voltage transistor area and the low-voltage transistor area, thereby avoiding the deterioration of a step height of the low-voltage transistor area due to the subsequent use of a large amount of acid to remove the gate oxide layer additionally grown above the active area of the low-voltage transistor area, and preventing the electrical property and the reliability of a low-voltage device from being subsequently influenced while avoiding the influence of the etching with the large amount of acid on the thickness of a high-voltage gate oxide layer which has already been grown.

Abstract: This application discloses a CIS pixel readout circuit structure. An SG and an SF adopt different transverse thicknesses of spacers. The spacer of the SG adopts a smaller transverse thickness to reduce the parasitic resistance. The spacer of the SF adopts a larger transverse thickness to reduce the GIDL current. In the CIS pixel readout circuit structure according to this application, drain metal plugs are formed on outer sides of both left and right ends of an SF gate structure. The SF and the SG form a T-shaped combined compact structure to achieve equivalent parallel connection of two SF, thus effectively reducing the parasitic resistance of the share active area between the SG and the SF, and simultaneously saving the space area. This application further discloses a method for fabricating a CIS pixel readout circuit structure.

Abstract: Precipitation or scaling may occur when combining produced water from multiple sources, such as when one produced water contains dissolved calcium ions and another produced water contains dissolved sulfate anions. The tendency toward precipitation or scaling may be decreased by treating the produced water containing dissolved sulfate anions. Such methods may comprise: providing a first produced water comprising dissolved sulfate anions; treating the first produced water with a metal salt capable of forming an insoluble metal sulfate, thereby forming a metal sulfate precipitate and a treated produced water; separating the metal sulfate precipitate from the treated produced water; and after separating the metal sulfate precipitate, mixing the treated produced water with at least one second produced water to obtain a mixed produced water, the at least one second produced water containing dissolved calcium ions, and the mixed produced water having a saturation ratio for calcium sulfate of less than 1.

Abstract: Systems and methods include scale control in oilfield produced waters. Thermodynamic data indicative of surface conditions and subterranean conditions of a subterranean region including a well is received, from probes. An acidity of a produced water stream to be disposed in the well is received from a pH meter. A supersaturation degree of the produced water stream to be disposed in the well is determined, by using the thermodynamic data. An amount of carbon dioxide to be injected in the produced water stream to neutralize a scaling risk is determined, by the one or more processors, by using the supersaturation degree and the acidity. An injection of the amount of the carbon dioxide in the produced water stream is triggered to neutralize the scaling risk.

Abstract: A display substrate includes a base substrate (100), a circuit structure layer (20), a light emitting structure layer (4), at least one conductive layer, and at least one capacitance compensation layer (51). The base substrate (100) includes a first display region (A1) and a second display region (A2) at least partially surrounding the first display region (A1). The capacitance compensation layer (51) is located in the first display region (A1) and on a side of the light emitting structure layer (4) close to the base substrate (100). The capacitance compensation layer (51) includes at least one compensation capacitance electrode plate (511). An anode (411) of at least one first light emitting element (13) is electrically connected with the compensation capacitance electrode plate (511) of the capacitance compensation layer (51).

Abstract: The technology relates to a method of treating inorganic scale in a well that is drilled in a heterogeneous reservoir matrix. A heterogeneous reservoir matrix has varying permeabilities. The varying permeabilities can cause a change in the shear rate as a fluid flows through it. A shear thinning nanofluid that includes a nanoparticle functionalized with a scale inhibitor and an aqueous solvent is injected into the heterogeneous reservoir matrix. The shear thinning behavior of the nanofluid causes a self-diversion of the nanofluid from a high permeability zone towards the low permeability zone due to a change in the viscosities. The self-diversion causes the scale inhibitor to be delivered to the low permeability zone.

Abstract: A display substrate includes a base substrate, multiple pixel circuits, multiple first light emitting elements, multiple second light emitting elements, and at least one first signal line extending along the first direction. The base substrate includes a first display area and at least one second display area. The first display area at least partially surrounds the second display area. A first signal line is located in the first display area, and is electrically connected with multiple pixels circuits of the first display area. The first signal line is partitioned into at least two first sub-signal lines by at least one second display area. Adjacent first sub-signal lines of the at least two first sub-signal lines are electrically connected by a first connector line. At least part of line segments of the first connector line are located between the multiple first pixel circuits.

Abstract: The present application discloses a method for making an integrated structure of an MOS transistor having different operation voltages. The resulting integrated structure of an MOS transistor employs a hybrid gate solution. A resulting low voltage MOS transistor adopts a high-K metal gate, so that the gate leakage of the LV (low voltage) MOS transistor can be reduced and speed performance is maintained; and a resulting medium voltage MOS transistor and a high voltage MOS transistor adopt a poly gate, the gate oxide is a single oxide, and a high-K film (HK film) is not present, so that the resulting medium voltage MOS transistor and high voltage MOS transistor are highly reliable without any other reliability problems due to the introduction of a high-K film (HK film) and a gate metal film.

Abstract: Disclosed are a display substrate and a display device. The display substrate includes: a display area and a bezel area, the display area including a first display area and a second display area; a plurality of light emitting devices, a plurality of pixel driving circuits, a plurality of data lines, and a plurality of first wires in the second display area and extending in a row direction, where all the first wires are located at a plurality of row gaps adjacent to the first display area respectively, each of the plurality of first wires is connected between one data line corresponding to the first display area and one first pixel driving circuit corresponding to the one data line.

Abstract: This technology relates to a system and method of delaying CaCO3 scale formation in an oil production well using a phosphonate scale inhibitor and a chelating agent. The addition of a small concentration (less than 5 ppm) of a chelating agent to the phosphonate scale inhibitor delays the scale induction time and scaling time of CaCO3 scale.

Abstract: Embodiments of the present disclosure provide a touch substrate, a touch display panel and a touch display apparatus. The touch display panel includes: a base substrate; a touch electrode layer on the base substrate and in a touch display region, the touch electrode layer including touch electrodes in the same layer and insulated from each other; and touch leads on the base substrate, each touch lead is electrically connected to a corresponding one touch electrode, some touch leads extend from the touch display region through the first bending region to the first binding region, and are bent to the back of the touch display panel in the first bending region, and the other touch leads extend from the touch display region through the second bending region to the second binding region, and are bent to the back of the touch display panel in the second bending region.

Abstract: The present application discloses an MV device, wherein a first gate structure of the MV device is formed by stacking a first gate dielectric layer and a first gate conductive material layer. The first gate dielectric layer is divided into a body gate dielectric layer and an edge gate dielectric layer. The body gate dielectric layer is located in a middle region, and the edge gate dielectric layer surrounds the periphery of the body gate dielectric layer. A channel region is located in a surface of the semiconductor substrate between the lightly doped drain regions on the two sides of the first gate structure. In a channel length direction, the top of the channel region is covered by the body gate dielectric layer. The present application also discloses a method for manufacturing the MV device.

Abstract: Systems and methods include scale control in oilfield produced waters. Thermodynamic data indicative of surface conditions and subterranean conditions of a subterranean region including a well is received, from probes. An acidity of a produced water stream to be disposed in the well is received from a pH meter. A supersaturation degree of the produced water stream to be disposed in the well is determined, by using the thermodynamic data. An amount of carbon dioxide to be injected in the produced water stream to neutralize a scaling risk is determined, by the one or more processors, by using the supersaturation degree and the acidity. An injection of the amount of the carbon dioxide in the produced water stream is triggered to neutralize the scaling risk.

Abstract: A corrosion inhibitor composition includes a fatty acid ethoxylate, a thiourea, an arylthiourea, a thiazole, and two or more solvents. A metal article in contact with the composition has a corrosion rate of about 25 to about 45 mils penetration per year (mpy), as determined by an ASTM G111 standard test method. A method for inhibiting corrosion of a metal in contact with a corrosive fluid.