Abstract: A composition for inhibiting corrosion in gas wells includes a pyrazolopyridine derivative. The pyrazolopyridine derivative includes a pyridyl moiety, a first pyrazole moiety, a second pyrazole moiety, and a phenyl moiety. The first pyrazole moiety is bound to the pyridyl moiety. The second pyrazole moiety is bound to the pyridyl moiety. The phenyl moiety is bound to the pyridyl moiety. The composition can be flowed into a wellbore formed in a subterranean formation, thereby inhibiting corrosion in the wellbore.

Abstract: Systems and methods for generating and using a water filtration media containing date seed powder are provided. The method of generating the date seed powder for use in a water treatment system includes drying the date seeds, cleaning and removing the date seed envelopes, grinding the date seeds, and segregating the date seed powder according to a predetermined particle size. The method of using the date seed powder to treat water includes using a treatment tank with a date seed media bed layer, introducing water, and filtering suspended solids from the water stream using the date seed media bed layer. The system utilizing the date seed media bed layer includes a treatment tank, a date seed media bed layer, water inlets and outlets, backwashing equipment, and media support screens.

Abstract: A display panel includes: a drive backplane having a transparent region and a pixel region surrounding the transparent region, wherein a plurality of pixel circuits are provided in the pixel region, and the pixel circuits include a plurality of columns of first pixel circuits and a plurality of columns of second pixel circuits distributed along a row direction; and a light-emitting layer including a plurality of light-emitting devices, wherein the light-emitting devices include a plurality of first light-emitting devices located in the transparent region and a plurality of second light-emitting devices located in the pixel region, each of the first light-emitting devices is connected to one of the first pixel circuits via one of transparent electric conductors, and a deviation between delay time of a signal transmitted by any of the electric conductors and a standard delay time is not greater than a deviation threshold.

Abstract: The present disclosure relates to a terminal device, a display apparatus, a display panel, and a manufacturing method thereof, which is related to the field of display. The display panel includes a drive back plate, having a light transmitting region and a drive region at least partially surrounding the light transmitting region, wherein the drive region has a plurality of pixel circuits and at least includes first pixel circuits and second pixel circuits; a transfer layer, provided on a side of the drive back plate and including a plurality of layers of mutually insulated lead layers, wherein each of the lead layers includes a plurality of mutually insulated leads; each lead extends from the light transmitting region to the drive region and is connected to one of the first pixel circuits; a light emitting layer, provided on a side of the transfer layer away from the drive back plate.

Abstract: A polymeric scale inhibitor composition and a method for inhibiting metal sulfide scale formation in a well are provided. The composition includes 80-82 mol % of a first monomeric unit, where the first monomeric unit is 2-acrylamido-2-methylpropane sulfonic acid (AMPS). The composition also includes 2-18 mol % of a second monomeric unit selected from N-vinyl formamide, N-vinyl pyrrolidone, and diallyl dimethyl ammonium chloride. The composition further includes 2-18 mol % of a third monomeric unit selected from acrylic acid, methacrylic acid, esters of acrylic acid or methacrylic acid with an alcohol having 1 to 4 carbon atoms, and carboxyethyl acrylate. The polymeric scale inhibitors show superior adsorption characteristics on rocks and their subsequent release behavior allows for scale inhibition over extended time periods respectively at a significant volume of coreflood fluids. They are especially suited for downhole application via field scale squeeze treatments.

Abstract: The present application provides a displaying base plate and a displaying device, wherein the displaying base plate includes a transparent displaying region and an effective displaying region, the transparent displaying region includes a plurality of scanning lines, each of the scanning lines includes one or more first light emitting regions, a driving electrode of each of the first light emitting regions is connected to a corresponding driving circuit via a transparent trace, the transparent traces connected to the driving electrodes of a same one instance of the scanning lines are located in a same one layer, the plurality of scanning lines include at least a pair of neighboring first scanning line and second scanning line, and the transparent traces connected to the driving electrodes of the first scanning line and the transparent traces connected to the driving electrodes of the second scanning line are located in different layers.

Abstract: The present invention provides a manufacturing method for a semiconductor memory device. The method comprises: providing a substrate, wherein a gate structure of a memory transistor is formed on a memory area of the substrate, and a first layer used for forming a gate structure of a peripheral transistor is formed on a peripheral area of the substrate; performing lightly doped drain ion implantation on an upper part of a portion, on two sides of the gate structure of the memory transistor, of the memory area of the substrate by applying the first layer as a mask of the peripheral area; and etching the first layer to form the gate structure of the peripheral transistor. According to the present invention, an ion diffusion degree of source and drain electrodes of the memory area may be effectively increased, and the uniformity of a memory cell device is improved.

Abstract: The present disclosure relates to a display panel and a display device. The display panel includes a base substrate with a display area and a non-display area surrounding the display area, the display area including a first display sub-area and a second display sub-area; a plurality of first light emitting elements formed on the base substrate and located in the first display sub-area; and a plurality of first pixel circuits formed on the base substrate and located in at least one of the second display sub-area and the non-display area, where the first pixel circuits are electrically connected to the first pixel electrodes of the first light emitting elements through a conductive wire.

Abstract: The present disclosure provides a display panel and a display device, which belongs to the field of display technology. The display panel has a display area and a peripheral area, the display area includes a main display area and a transparent display area, and the display panel includes a first sub-pixel, a first pixel driving circuit and a transparent lead. The first sub-pixel is located in the transparent display area, and includes a first pixel electrode; the first pixel driving circuit is located in the peripheral area; and the transparent lead connects the first pixel electrode and the first pixel driving circuit, so that the first pixel driving circuit drives the first sub-pixel to emit light.

Abstract: A terminal resistance circuit, a chip and a chip communication device are provided. The terminal resistance circuit can be used for a high-speed differential I/O pair and includes two resistance circuits and a control circuit. An end of the two resistance circuits connected in series is connected to a first interface and another end is connected to a second interface. A conductor wire connected between the two resistance circuits has a target node thereon. The two resistance circuits are symmetrically arranged relative to the target node. The control circuit is connected to the two resistance circuits individually and used to control the two resistance circuits each to be in a turn-off state during powering-on of the chip. An abnormal operation caused by a short circuit between two interfaces of a I/O pair during the powering-on of the chip is avoided and the working stability of the chip is improved.

Abstract: A downhole injection system in selective communication with a wellhead assembly and a wellbore, the downhole injection system including a pumping chamber in selective communication with the wellhead assembly, the pumping chamber defining a wellhead pressure portion defining a wellhead pressure inlet in selective communication with the wellhead assembly and a wellhead pressure outlet in selective communication with the wellhead assembly, where the wellhead pressure portion is maintained at a wellhead pressure, and a chemical portion in selective communication with the wellbore, and a movable plate positioned within the pumping chamber, where the chemical portion is separated from the wellhead pressure portion by the movable plate.

Abstract: The present invention provides an ultra-thin optical component, including a mirror projection device and a reflector, where the mirror projection device is configured to refract image light symmetrically, then form a real image, and project the real image to the reflector, where the real image is located between a human eye and the reflector; and the reflector is configured to reflect the image light to the human eye. The present invention further provides a display device using the ultra-thin optical component and a virtual imaging method. By means of the ultra-thin optical component, the display device, and the imaging method in the present invention, an optical component is made thinner and lighter, and an image source display device is easier to configure and package, to achieve the appearance of ordinary glasses.

Abstract: The present invention provides a semiconductor structure for forming a CMOS image sensor. The semiconductor structure includes at least a photodiode formed in the substrate for collecting photoelectrons, and the photodiode has a pinning layer, a first doped region and a second doped region in order from top to bottom in a height direction of the substrate. The semiconductor structure further includes a third doped region located in the substrate corresponding to a laterally extending region of the second doped region. The first doped region has an ion doping concentration greater than the ion doping concentration of the second doped region, the ion doping concentration of the second doped region is greater than the ion doping concentration of the third doped region, and the third doped region is in contact with the second doped region after diffusion. The present invention also provides a method of manufacturing the above-described semiconductor structure.

Abstract: A free-form prism-lens group includes: a primary prism, a first auxiliary lens and a second auxiliary lens, the primary prism includes three optical surfaces, the first auxiliary lens is arranged adjacent to the primary prism and is not used for imaging the image light entering the first auxiliary lens; the second auxiliary lens is arranged adjacent to the primary prism and a gap with a predetermined thickness is arranged between the second auxiliary lens and the primary prism, the second auxiliary lens extends in a direction perpendicular to an optical axis to cover an effective aperture of the image light entering the second auxiliary lens from the primary prism.

Abstract: The present invention discloses a flash. A channel region comprises a first shallow trench formed in the surface area of a semiconductor substrate. A tunneling dielectric layer and a polysilicon floating gate are formed in the first shallow trench and extended to the outside of the first shallow trench. A control dielectric layer and a polysilicon control gate are sequentially formed on the two side surfaces in the width direction and the top surface of the polysilicon floating gate. A source region and a drain region are formed in a self-aligned manner in active regions on the two sides in the length direction of the polysilicon floating gate. The present invention further discloses a method for manufacturing a flash. The present invention can break through the limitation of the length of the channel on the size of the memory cell, thus reducing the area of the memory cell.

Abstract: The present disclosure provides a non-volatile flash memory device and a manufacturing method thereof. The non-volatile flash memory device comprises at least a plurality of memory cells in a memory area. The manufacturing method comprises: providing a substrate, and defining the memory area of the non-volatile flash memory device on the substrate; forming a plurality of stack gates of the plurality of memory cells on a substrate corresponding to the memory area, and the top of each stack gate is a memory control gate of the memory cell; etching the memory control gates to reduce the height of the memory control gates with the fluid photoresist filled among the plurality of stack gates of the plurality of memory cells as a mask; and removing the fluid photoresist.

Abstract: A freeform prism-lens group includes: a primary prism; a first auxiliary lens; and a beamsplitter film between the primary prism and the first auxiliary lens and having a predetermined beamsplitting ratio; wherein: the first auxiliary lens has a first optical surface substantially conforming to a neighboring freeform surface of the primary prism; and the first auxiliary lens has a second opposing optical surface distal from the primary prism that is planar, aspheric, or spherical with a curvature radius greater than 100 mm.

Abstract: The present invention provides a semiconductor structure for a split gate flash memory cell and a method of manufacturing the same. The split gate flash memory cell provided by the present invention at least includes a select gate and a floating gate formed on the substrate, one side of the select gate is formed with an isolation wall, and the floating gate is on the other side of the isolation wall. An ion implantation region is formed in an upper portion of the substrate below the isolation wall, wherein the ion implantation type of the ion implantation region is different from the ion implantation type of the substrate. The invention also provides a manufacturing method for manufacturing the above-mentioned split gate flash memory cell, and the manufacturing method provided by the invention can be compatible with the existing manufacturing process of the split gate flash memory cell without increasing the process cost and the process complexity.

Abstract: Treating carbon steel tubing includes contacting the carbon steel tubing with a first treatment solution including a salt; corroding the carbon steel tubing with the salt to yield a corroded surface on the carbon steel tubing; contacting the corroded surface on the carbon steel tubing with a second treatment solution comprising sulfide ions; and forming an iron sulfide layer on the corroded surface of the carbon steel tubing by chemically bonding the sulfide ions in the second treatment solution with iron in the carbon steel tubing. In some cases, the first treatment solution also includes sulfide ions, and the iron sulfide layer is formed by contacting the carbon steel tubing with the first treatment solution.

Abstract: Managing aggregated node group power states. A reflected energy device may transmit energy to one of multiple aggregated node groups. Each aggregated node group includes multiple device nodes. The aggregated node group may be moved from one location to another. The transmitted energy is reflected to detect occurrence of a state change condition. A communication device such as the reflected energy device or an anchor node then instructs device node(s) of the aggregated node group to enter a high power state and to enter a low power state.