Abstract: A decoder for decoding data transmitted between superconductor circuits. Interleaved data and clock pulses are applied to a clock input of a flip-flop circuit and one input of an AND gate. The output of the flip-flop circuit is a clock signal, and is applied to a delay circuit to be put in phase with the data pulses in the interleaved signal. The delayed clock signal is then applied to the other input of the AND gate, so that when a data pulse occurs in the interleaved signal it aligns with a clock pulse and is outputted from the AND gate. The clock signal from the flip-flop circuit is also sent to the input of the flip-flop circuit through a delay circuit that delays the signal more than one half of the clock period and less than one clock period. This delayed clock signal sets the flip-flop circuit to the “1” state after the data pulse in the interleaved signal are input to the flip-flop circuit so that the data pulses are not outputted from the flip-flop circuit.

Abstract: A clock recovery circuit (10) for a superconductor system that enables the phase of a system clock to be instantaneously reset without any pulse interaction. The clock recovery circuit (10) includes a Josephson transmission line oscillator loop (14) of length 2T, where T is equal to one clock period. First and second data inputs (16, 18) are for injecting a data pulse onto the oscillator loop (14). A pulse generator (24) is for injecting an initial clock pulse onto the oscillator loop (14) that is output as periodic clock signals. An output tap (12) is for outputting the data pulse from one of the first and second data inputs (16, 18), and the periodic clock signals in the absence of the data pulse. When the data pulse is input on one of first and second output taps (32, 34), the clock phase is instantaneously reset.

Abstract: A superconducting oscillator/counter analog-to-digital converter (50) that provides simultaneous in-phase and quadrature-phase of an RF input signal. The RF input signal is converted to a series of SFQ input pulses by a superconducting voltage controlled oscillator (12). A clock circuit (26) generates a series of SFQ clock pulses. The SFQ input pulses and the SFQ clock pulses are applied to a pulse repulsion circuit (52) that outputs the SFQ input pulses and the SFQ clock pulses spaced apart in time. In one embodiment, the pulse repulsion circuit (52) includes two Josephson transmission lines (60, 62), where the magnetic coupling between the lines (60, 62) provides the SFQ pulse repulsion.

Abstract: A superconducting self-clocked complementary SFQ logic family. The basic element of the circuit is a plurality of Josephson junctions and a control inductance coupled across a pair of voltage rails. An important aspect of the invention relates to the use of voltage biasing for the Josephson junctions, which provides several benefits. First, voltage biasing eliminates the need for biasing resistors as used in constant current mode devices. Such biasing resistors are known to be the dominant source of power dissipation in such logic circuits. Elimination of the biasing resistors thus reduce the power dissipation to the lowest possible value to that of the power dissipation of the switching devices themselves. In addition, the voltage biasing takes advantage of the voltage to frequency relationship of Josephson junctions and automatically establishes a global clock at the Josephson frequency without the need for extra circuitry; thus increasing the practical clock rate.

Abstract: A superconductor on-chip microstrip line (2, 4) to off-chip microstrip line (7) transition of low characteristic impedance (15, 20, 22) is realized that obtains a bandwidth of 200 GHz for MCM application while employing solder bump (15, 17) technology to connect the chips (3, 5) to the off-chip microstrip and substrate (6). Circular openings (20, 22) through the respective ground plane layers (10 & 16) of the off-chip and on-chip microstrips are provided in positions respectively underlying and overlying the solder bump (15) for the signal. The openings may be sized to provide a desired ratio of inductance to capacitance, the larger the size, the greater the ratio value. This technique may be used to match characteristic impedance to give broad bandwidth low impedance interconnections needed for direct SFQ chip-to-chip communication on a passive MCM.

Abstract: The self inductance associated with a capacitance A52 in a superconductor integrated circuit (FIG. 1) is reduced by adding a layer of superconductor metal (A54) overlying the capacitor, effectively producing a negative inductance to counteract the self-inductance of the capacitor leads, thereby reducing inductance of the circuit. As a result it possible to transfer a single flux quantum (“SFQ”) pulse through the capacitor. Capacitors (19 and 25 FIG. 5) of the foregoing type are incorporated in superconductor integrated circuit SFQ transmission lines (FIG. 5) to permit SQUID-to-SQUID transfer of SFQ pulses, while maintaining the circuit grounds of the respective SQUIDs in DC isolation. Bias current (10) may be supplied to multiple SQUIDs (1 & 3, 7 & 9 FIG. 5) serially, reducing the supply current required previously for operation of multiple SQUIDs.

Abstract: A crossbar switch includes a cross-point matrix with n input rows of cross-points and m output columns of cross-points. The crossbar switch further includes n decoders connected to the n input rows. Each of the n rows includes a single serial address input, a shift input and a data input. A serial address and data enter the address input and the data input in parallel. A shift sequence is transmitted on the single shift input. The data flows before the shift sequence on the shift input is complete. The data is shifted through the crossbar switch using a clock that is generated on-chip using a clock recovery circuit. The decoder converts a binary address input into a serial address and includes an N-bit counter with a plurality of toggle flip-flops. The crossbar switch is implemented using superconductor digital electronics such as rapid single flux quantum (RSFQ) logic.

Abstract: A rapid SFQ one-way buffer (13, 1, 4, 5, 15, 2 & 9), is combined with a Josephson transmission line (17,3, 19, 16, 21 & 4) that is lightly loaded (RL) to provide a superconductor driver capable of producing double flux quantum output pulses. Each SFQ pulse applied to the input of the one-way buffer propagates through the Josephson transmission line to generate a double flux quantum pulse at the transmission line output.

Abstract: A superconductor on-chip microstrip line (2, 4) to off-chip microstrip line (7) transition of low characteristic impedance (15, 20, 22) is realized that obtains a bandwidth of 200 GHz for MCM application while employing solder bump (15, 17) technology to connect the chips (3, 5) to the off-chip microstrip and substrate (6). Circular openings (20, 22) through the respective ground plane layers (10 & 16) of the off-chip and on-chip microstrips are provided in positions respectively underlying and overlying the solder bump (15) for the signal. The openings may be sized to provide a desired ratio of inductance to capacitance, the larger the size, the greater the ratio value. This technique may be used to match characteristic impedance to give broad bandwidth low impedance interconnections needed for direct SFQ chip-to-chip communication on a passive MCM.

Abstract: A rapid SFQ one-way buffer (13, 1, 4, 5, 15, 2 & 9), is combined with a Josephson transmission line (17,3, 19, 16, 21 & 4) that is lightly loaded (RL) to provide a superconductor driver capable of producing double flux quantum output pulses. Each SFQ pulse applied to the input of the one-way buffer propagates through the Josephson transmission line to generate a double flux quantum pulse at the transmission line output.

Abstract: The self inductance associated with a capacitance A52 in a superconductor integrated circuit (FIG. 1) is reduced by adding a layer of superconductor metal (A54) overlying the capacitor, effectively producing a negative inductance to counteract the self-inductance of the capacitor leads, thereby reducing inductance of the circuit. As a result it possible to transfer a single flux quantum (“SFQ”) pulse through the capacitor. Capacitors (19 and 25 FIG. 5) of the foregoing type are incorporated in superconductor integrated circuit SFQ transmission lines (FIG. 5) to permit SQUID-to-SQUID transfer of SFQ pulses, while maintaining the circuit grounds of the respective SQUIDs in DC isolation. Bias current (10) may be supplied to multiple SQUIDs (1 & 3, 7 & 9 FIG. 5) serially, reducing the supply current required previously for operation of multiple SQUIDs.

Abstract: An asynchronous SFQ logic cell that is amenable to being used in combinational logic circuits. Rather than encode each digital logic bit as one SFQ pulse, each logic bit is encoded as a series of SFQ pulses. As such, merge and join circuits can be used for elementary logic cells to form asynchronous combinational logic circuits in accordance with the present invention. Such circuits are relatively faster and denser as well as more compatible with existing synchronous SFQ logic circuits.

Abstract: An asynchronous SFQ logic cell that is amenable to being used in combinational logic circuits. Rather than encode each digital logic bit as one SFQ pulse, each logic bit is encoded as a series of SFQ pulses. As such, merge and join circuits can be used for elementary logic cells to form asynchronous combinational logic circuits in accordance with the present invention. Such circuits are relatively faster and denser as well as more compatible with existing synchronous SFQ logic circuits.

Abstract: A superconductor circuit (50) for providing active timing arbitration between SFQ pulses. The superconductor circuit (50) includes a first superconducting transmission line (52) having at least one inductor (54) for transmitting first input pulses, and a second superconducting transmission line (62) having at least one inductor (64) for transmitting second input pulses that are correlated to the first input pulses. The first and second superconducting transmission lines (52, 62) are coupled together in order to generate a flux attraction between the first and second input pulses for reducing relative timing uncertainty.

Abstract: The self inductance associated with a capacitance A52 in a superconductor integrated circuit (FIG. 1) is reduced by adding a layer of superconductor metal (A54) overlying the capacitor, effectively producing a negative inductance to counteract the self-inductance of the capacitor leads, thereby reducing inductance of the circuit. As a result it possible to transfer a single flux quantum (“SFQ”) pulse through the capacitor. Capacitors (19 and 25 FIG. 5) of the foregoing type are incorporated in superconductor integrated circuit SFQ transmission lines (FIG. 5) to permit SQUID-to-SQUID transfer of SFQ pulses, while maintaining the circuit grounds of the respective SQUIDs in DC isolation. Bias current (10) may be supplied to multiple SQUIDs (1& 3, 7 & 9 FIG. 5) serially, reducing the supply current required previously for operation of multiple SQUIDs.

Abstract: The level of bias current (12) required by a superconductor integrated circuit (2 & 4) is lowered by separating the circuit into portions having separate ground planes and supplying the bias current to the circuit portion (2) in one ground plane in series (10) with that for the circuit portion (4) in another ground plane. To maintain DC isolation between those circuit portions, SFQ pulses inputted (SFQ IN) move across the separate ground planes through a pair of inductively coupled SQUIDS (3 & 5) that define a DC transformer; and a combiner (7) reconstitutes and outputs the SFQ pulses. To provide inductive coupling the DC transformer includes a primary (25) and isolated secondary (5) winding.

Abstract: A superconducting A/D converter (10) has an error correction system (70) for eliminating non-linearities in a primary quantizer (30). The converter (10) includes a primary quantizer (30), a primary SFQ counter (50), and the error correction system (70). The primary quantizer (30) generates primary SFQ pulses based on an average voltage of an analog input signal. The primary SFQ counter (50) converts the primary SFQ pulses into a digital output signal based on a frequency of the primary SFQ pulses. The error correction system (70) corrects the digital output signal based on the analog input signal and the primary SFQ pulses. Using the primary SFQ pulses to correct the digital output signal allows the converter (10) to take into account the non-linearities of the primary quantizer (30).

Abstract: A receiver (50) for providing chip-to-chip communication in a superconductor integrated circuit. The receiver (50) includes a detector circuit (52) for asynchronously receiving an input current, a splitter circuit (60) connected to the detector circuit (52) for generating first and second signals, a delay circuit (62) receiving the second signal from the splitter circuit for generating a delayed signal and a register circuit (64) receiving the first signal from the splitter circuit (60) and the delayed signal from the delay circuit (62) for producing a single flux quantum (SFQ) pulse. The receiver (50) according to the present invention provides an asynchronous chip-to-chip communication between a multi-chip superconductive circuit having low input current without an external rf clock.

Abstract: A superconducting A/D converter (10) has an error correction system (70) for eliminating non-linearities in a primary quantizer (30). The converter (10) includes a primary quantizer (30), a primary SFQ counter (50), and the error correction system (70). The primary quantizer (30) generates primary SFQ pulses based on an average voltage of an analog input signal. The primary SFQ counter (50) converts the primary SFQ pulses into a digital output signal based on a frequency of the primary SFQ pulses. The error correction system (70) corrects the digital output signal based on the analog input signal and the primary SFQ pulses. Using the primary SFQ pulses to correct the digital output signal allows the converter (10) to take into account the non-linearities of the primary quantizer (30).

Abstract: The present invention is a superconductive logic gate assembly (50, 100), a superconductive NOR gate assembly (10), and a superconductive random access memory (150). A superconductive logic gate assembly in accordance with the invention includes a plurality of logic inputs (INPUTS 1-N), each logic input being coupled to a SQUID (16) and each SQUID including at least one resistance (22) which eliminates hysteresis in an output of the SQUID produced in responding to a change in signal level at the logic inputs to the SQUID, a DC bias (20) coupled to each SQUID, and an output circuit (14) coupled to each SQUID for providing a logic output (OUTPUT) in response to the logic inputs.