Abstract: The present invention is a superconductive logic gate assembly (50, 100), a superconductive NOR gate assembly (10), and a superconductive random access memory (150). A superconductive logic gate assembly in accordance with the invention includes a plurality of logic inputs (INPUTS 1-N) each logic input being coupled to a SQUID (16) and each SQUID including at least one resistance (22) which eliminates hysteresis in an output of the SQUID produced in responding to a change in signal level at the logic inputs to the SQUID, a DC bias (20) coupled to each SQUID, and an output circuit (14) coupled to each SQUID for providing a logic output (OUTPUT) in response to the logic inputs.

Abstract: A superconducting cell (10) is provided which has a storage loop (12), a read-out loop (14), and a direct coupling element between the storage loop (12) and read-out loop (14). The direct coupling element is preferably an inductor (30) common to the storage loop (12) and read-out loop (14). The superconducting cell (10) is preferably a vortex-transitional superconducting memory cell. In the superconducting cell (10) a first address line (18) is directly connected to the storage loop (12) and a second address line (16) is electromagnetically coupled to the storage loop (12). The storage loop (12) has a first switchable storage element (20) to switch the superconducting cell (10) into the storing state, when currents on the first and second address lines (18), (16) have the same polarity, and into the reading state, when currents on the first and second address lines (18), (16) have different polarity.