Patents by Inventor Quy Le

Quy Le has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250123614
    Abstract: In one example in accordance with the present disclosure, an electronic device is described. An example electronic device includes a processor and memory storing executable instructions that when executed cause the processor to receive an image of a polymer melt pool captured during crystallization of the polymer melt pool. The instructions also cause the processor to measure brightness of the polymer melt pool in the captured image. The instructions further cause the processor to determine crystallization information of the polymer melt pool based on the measured brightness of the polymer melt pool.
    Type: Application
    Filed: August 16, 2021
    Publication date: April 17, 2025
    Applicants: HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P., NANYANG TECHNOLOGICAL UNIVERSITY
    Inventors: Van Thai TRAN, Hejun DU, Jun ZENG, Kun ZHOU, How Wei Benjamin TEO, Kaijuan CHEN, Kim Quy LE
  • Publication number: 20250025557
    Abstract: Targeted therapeutics for the treatment of cancers expressing FOLR1, MEGF10, HPSE2, KLRF2, PCDH19, and/or FRAS1 are described. The targeted therapeutics can include a chimeric antigen receptor (CAR) expressed by an immune cell or an antibody-targeted therapeutic. The targeted therapeutics can be used to treat a variety of cancers including solid tumors and blood cancers, such as CBFA2T3-GLIS2 acute myeloid leukemia (C/G AML).
    Type: Application
    Filed: November 2, 2022
    Publication date: January 23, 2025
    Applicant: Fred Hutchinson Cancer Center
    Inventors: Soheil Meshinchi, Quy Le, Rhonda Ries, Sommer Castro
  • Patent number: 12061909
    Abstract: An execution unit circuit for use in a processor core provides efficient use of area and energy by reducing the per-entry storage requirement of a load-store unit issue queue. The execution unit circuit includes a recirculation queue that stores the effective address of the load and store operations and the values to be stored by the store operations. A queue control logic controls the recirculation queue and issue queue so that that after the effective address of a load or store operation has been computed, the effective address of the load operation or the store operation is written to the recirculation queue and the operation is removed from the issue queue, so that address operands and other values that were in the issue queue entry no longer require storage. When a load or store operation is rejected by the cache unit, it is subsequently reissued from the recirculation queue.
    Type: Grant
    Filed: May 4, 2023
    Date of Patent: August 13, 2024
    Assignee: International Business Machines Corporation
    Inventors: Salma Ayub, Sundeep Chadha, Robert Allen Cordes, David Allen Hrusecky, Hung Qui Le, Dung Quoc Nguyen, Brian William Thompto
  • Publication number: 20240165255
    Abstract: Methods and compositions for providing a cytotoxic effect against FOLR-1 expressing cancers using antibody conjugates with binding specificity for folate receptor alpha (FOLR1) and its isoforms and homologs are provided. Examples of FOLR-1 expressing cancers include leukemias, ovarian cancer, breast cancer, bladder cancer, and lung cancer, among other cancers described herein.
    Type: Application
    Filed: October 20, 2023
    Publication date: May 23, 2024
    Inventors: Soheil Meshinchi, Quy Le
  • Publication number: 20240009239
    Abstract: In various embodiments, the present disclosure provides chimeric antigen receptors (CARs) which bind to mesothelin. The mesothelin CARs comprise an extracellular region comprising a binding domain that specifically binds to at least a portion of mesothelin, a transmembrane region, and an intracellular region comprising an effector domain or a portion or variant thereof and a costimulatory domain or a portion or variant thereof. Recombinant host cells expressing the mesothelin CARs are also provided, as well as compositions and methods of treatment, prevention, and manufacture comprising the same.
    Type: Application
    Filed: November 3, 2021
    Publication date: January 11, 2024
    Applicant: FRED HUTCHINSON CANCER CENTER
    Inventors: Soheil Meshinchi, Quy Le, Rhonda Ries
  • Publication number: 20230273793
    Abstract: An execution unit circuit for use in a processor core provides efficient use of area and energy by reducing the per-entry storage requirement of a load-store unit issue queue. The execution unit circuit includes a recirculation queue that stores the effective address of the load and store operations and the values to be stored by the store operations. A queue control logic controls the recirculation queue and issue queue so that that after the effective address of a load or store operation has been computed, the effective address of the load operation or the store operation is written to the recirculation queue and the operation is removed from the issue queue, so that address operands and other values that were in the issue queue entry no longer require storage. When a load or store operation is rejected by the cache unit, it is subsequently reissued from the recirculation queue.
    Type: Application
    Filed: May 4, 2023
    Publication date: August 31, 2023
    Inventors: Salma Ayub, Sundeep Chadha, Robert Allen Cordes, David Allen Hrusecky, Hung Qui Le, Dung Quoc Nguyen, Brian William Thompto
  • Patent number: 11734010
    Abstract: An execution unit circuit for use in a processor core provides efficient use of area and energy by reducing the per-entry storage requirement of a load-store unit issue queue. The execution unit circuit includes a recirculation queue that stores the effective address of the load and store operations and the values to be stored by the store operations. A queue control logic controls the recirculation queue and issue queue so that that after the effective address of a load or store operation has been computed, the effective address of the load operation or the store operation is written to the recirculation queue and the operation is removed from the issue queue, so that address operands and other values that were in the issue queue entry no longer require storage. When a load or store operation is rejected by the cache unit, it is subsequently reissued from the recirculation queue.
    Type: Grant
    Filed: September 7, 2021
    Date of Patent: August 22, 2023
    Assignee: International Business Machines Corporation
    Inventors: Salma Ayub, Sundeep Chadha, Robert Allen Cordes, David Allen Hrusecky, Hung Qui Le, Dung Quoc Nguyen, Brian William Thompto
  • Patent number: 11490456
    Abstract: An Automated Analysis and Warning of Optical Transmission (AWOT) between BBU unit and RRU of radio transmitting station accurately and quickly identifies errors on an optical transmission line, thereby reducing costs in terms of labor and equipment, and at the same time reducing service downtime of mobile communication systems.
    Type: Grant
    Filed: December 30, 2020
    Date of Patent: November 1, 2022
    Assignee: VIETTEL GROUP
    Inventors: Tien Sang Nguyen, Ngoc Quy Le, Truong Giang Le, Xuan Thang Nguyen
  • Publication number: 20210406023
    Abstract: An execution unit circuit for use in a processor core provides efficient use of area and energy by reducing the per-entry storage requirement of a load-store unit issue queue. The execution unit circuit includes a recirculation queue that stores the effective address of the load and store operations and the values to be stored by the store operations. A queue control logic controls the recirculation queue and issue queue so that that after the effective address of a load or store operation has been computed, the effective address of the load operation or the store operation is written to the recirculation queue and the operation is removed from the issue queue, so that address operands and other values that were in the issue queue entry no longer require storage. When a load or store operation is rejected by the cache unit, it is subsequently reissued from the recirculation queue.
    Type: Application
    Filed: September 7, 2021
    Publication date: December 30, 2021
    Inventors: Salma Ayub, Sundeep Chadha, Robert Allen Cordes, David Allen Hrusecky, Hung Qui Le, Dung Quoc Nguyen, Brian William Thompto
  • Patent number: 11150907
    Abstract: An execution unit circuit for use in a processor core provides efficient use of area and energy by reducing the per-entry storage requirement of a load-store unit issue queue. The execution unit circuit includes a recirculation queue that stores the effective address of the load and store operations and the values to be stored by the store operations. A queue control logic controls the recirculation queue and issue queue so that that after the effective address of a load or store operation has been computed, the effective address of the load operation or the store operation is written to the recirculation queue and the operation is removed from the issue queue, so that address operands and other values that were in the issue queue entry no longer require storage. When a load or store operation is rejected by the cache unit, it is subsequently reissued from the recirculation queue.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: October 19, 2021
    Assignee: International Business Machines Corporation
    Inventors: Salma Ayub, Sundeep Chadha, Robert Allen Cordes, David Allen Hrusecky, Hung Qui Le, Dung Quoc Nguyen, Brian William Thompto
  • Publication number: 20210274596
    Abstract: An Automated Analysis and Warning of Optical Transmission (AWOT) between BBU unit and RRU of radio transmitting station accurately and quickly identifies errors on an optical transmission line, thereby reducing costs in terms of labor and equipment, and at the same time reducing service downtime of mobile communication systems.
    Type: Application
    Filed: December 30, 2020
    Publication date: September 2, 2021
    Applicant: VIETTEL GROUP
    Inventors: Tien Sang Nguyen, Ngoc Quy Le, Truong Giang Le, Xuan Thang Nguyen
  • Patent number: 10983800
    Abstract: A processor core having multiple parallel instruction execution slices and coupled to multiple dispatch queues provides flexible and efficient use of internal resources. The configuration of the execution slices is selectable so that capabilities of the processor core can be adjusted according to execution requirements for the instruction streams. A plurality of load-store slices coupled to the execution slices provides access to a plurality of cache slices that partition the lowest level of cache memory among the load-store slices.
    Type: Grant
    Filed: June 6, 2018
    Date of Patent: April 20, 2021
    Assignee: International Business Machines Corporation
    Inventors: Lee Evan Eisen, Hung Qui Le, Jentje Leenstra, Jose Eduardo Moreira, Bruce Joseph Ronchetti, Brian William Thompto, Albert James Van Norstrand, Jr.
  • Patent number: 10267359
    Abstract: An apparatus is provided including a shaft, wherein the shaft is stationary. A rotatable component is configured to rotate with respect to the shaft. A fluid is operable to flow between the shaft and the rotatable component. A limiter is at a first axial end of the shaft, and a cup is at a second axial end of the shaft. An axially extending grooved region is between the limiter and the rotatable component.
    Type: Grant
    Filed: June 16, 2016
    Date of Patent: April 23, 2019
    Assignee: Seagate Technology LLC
    Inventors: Alan Lyndon Grantz, Lynn Bich-Quy Le, Klaus Diete Kloeppel
  • Patent number: 10223125
    Abstract: An execution slice circuit for a processor core has multiple parallel instruction execution slices and provides flexible and efficient use of internal resources. The execution slice circuit includes a master execution slice for receiving instructions of a first instruction stream and a slave execution slice for receiving instructions of a second instruction stream and instructions of the first instruction stream that require an execution width greater than a width of the slices. The execution slice circuit also includes a control logic that detects when a first instruction of the first instruction stream has the greater width and controls the slave execution slice to reserve a first issue cycle for issuing the first instruction in parallel across the master execution slice and the slave execution slice.
    Type: Grant
    Filed: July 30, 2018
    Date of Patent: March 5, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffrey Carl Brownscheidle, Sundeep Chadha, Maureen Anne Delaney, Hung Qui Le, Dung Quoc Nguyen, Brian William Thompto
  • Patent number: 10157064
    Abstract: A method of managing instruction execution for multiple instruction streams using a processor core having multiple parallel instruction execution slices. An event is detected indicating that either resource requirement or resource availability for a subsequent instruction of an instruction stream will not be met by the instruction execution slice currently executing the instruction stream. In response to detecting the event, dispatch of at least a portion of the subsequent instruction is made to another instruction execution slice. The event may be a compiler-inserted directive, may be an event detected by logic in the processor core, or may be determined by a thread sequencer. The instruction execution slices may be dynamically reconfigured as between single-instruction-multiple-data (SIMD) instruction execution, ordinary instruction execution, wide instruction execution.
    Type: Grant
    Filed: February 27, 2017
    Date of Patent: December 18, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Lee Evan Eisen, Hung Qui Le, Jentje Leenstra, Jose Eduardo Moreira, Bruce Joseph Ronchetti, Brian William Thompto, Albert James Van Norstrand, Jr.
  • Publication number: 20180336038
    Abstract: An execution slice circuit for a processor core has multiple parallel instruction execution slices and provides flexible and efficient use of internal resources. The execution slice circuit includes a master execution slice for receiving instructions of a first instruction stream and a slave execution slice for receiving instructions of a second instruction stream and instructions of the first instruction stream that require an execution width greater than a width of the slices. The execution slice circuit also includes a control logic that detects when a first instruction of the first instruction stream has the greater width and controls the slave execution slice to reserve a first issue cycle for issuing the first instruction in parallel across the master execution slice and the slave execution slice.
    Type: Application
    Filed: July 30, 2018
    Publication date: November 22, 2018
    Inventors: Jeffrey Carl Brownscheidle, Sundeep Chadha, Maureen Anne Delaney, Hung Qui Le, Dung Quoc Nguyen, Brian William Thompto
  • Publication number: 20180336036
    Abstract: An execution unit circuit for use in a processor core provides efficient use of area and energy by reducing the per-entry storage requirement of a load-store unit issue queue. The execution unit circuit includes a recirculation queue that stores the effective address of the load and store operations and the values to be stored by the store operations. A queue control logic controls the recirculation queue and issue queue so that that after the effective address of a load or store operation has been computed, the effective address of the load operation or the store operation is written to the recirculation queue and the operation is removed from the issue queue, so that address operands and other values that were in the issue queue entry no longer require storage. When a load or store operation is rejected by the cache unit, it is subsequently reissued from the recirculation queue.
    Type: Application
    Filed: July 30, 2018
    Publication date: November 22, 2018
    Inventors: Salma Ayub, Sundeep Chadha, Robert Allen Cordes, David Allen Hrusecky, Hung Qui Le, Dung Quoc Nguyen, Brian William Thompto
  • Patent number: 10133576
    Abstract: An execution unit circuit for use in a processor core provides efficient use of area and energy by reducing the per-entry storage requirement of a load-store unit issue queue. The execution unit circuit includes a recirculation queue that stores the effective address of the load and store operations and the values to be stored by the store operations. A queue control logic controls the recirculation queue and issue queue so that that after the effective address of a load or store operation has been computed, the effective address of the load operation or the store operation is written to the recirculation queue and the operation is removed from the issue queue, so that address operands and other values that were in the issue queue entry no longer require storage. When a load or store operation is rejected by the cache unit, it is subsequently reissued from the recirculation queue.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: November 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Salma Ayub, Sundeep Chadha, Robert Allen Cordes, David Allen Hrusecky, Hung Qui Le, Dung Quoc Nguyen, Brian William Thompto
  • Patent number: 10133581
    Abstract: An execution slice circuit for a processor core has multiple parallel instruction execution slices and provides flexible and efficient use of internal resources. The execution slice circuit includes a master execution slice for receiving instructions of a first instruction stream and a slave execution slice for receiving instructions of a second instruction stream and instructions of the first instruction stream that require an execution width greater than a width of the slices. The execution slice circuit also includes a control logic that detects when a first instruction of the first instruction stream has the greater width and controls the slave execution slice to reserve a first issue cycle for issuing the first instruction in parallel across the master execution slice and the slave execution slice.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: November 20, 2018
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeffrey Carl Brownscheidle, Sundeep Chadha, Maureen Anne Delaney, Hung Qui Le, Dung Quoc Nguyen, Brian William Thompto
  • Publication number: 20180285118
    Abstract: A processor core having multiple parallel instruction execution slices and coupled to multiple dispatch queues provides flexible and efficient use of internal resources. The configuration of the execution slices is selectable so that capabilities of the processor core can be adjusted according to execution requirements for the instruction streams. A plurality of load-store slices coupled to the execution slices provides access to a plurality of cache slices that partition the lowest level of cache memory among the load-store slices.
    Type: Application
    Filed: June 6, 2018
    Publication date: October 4, 2018
    Inventors: Lee Evan Eisen, Hung Qui Le, Jentje Leenstra, Jose Eduardo Moreira, Bruce Joseph Ronchetti, Brian William Thompto, Albert James Van Norstrand, JR.