Patents by Inventor Ra-Min Tain
Ra-Min Tain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180332700Abstract: A circuit board includes a first dielectric layer, a first circuit layer, a second circuit layer, a plurality of conductive vias, a second dielectric layer, a patterned seed layer, and a plurality of bonding layers. The first circuit layer is disposed in the first dielectric layer. The second circuit layer is disposed on the first dielectric layer. The conductive vias are disposed in the first dielectric layer and connect the first circuit layer to the second circuit layer. The second dielectric layer is disposed on the first dielectric layer and the second circuit layer and has a plurality of openings to expose a plurality of parts of the second circuit layer. The patterned seed layer is disposed on the exposed parts of second circuit layer and sidewalls of the openings. The bonding layers are respectively disposed on the patterned seed layer and made of porous copper.Type: ApplicationFiled: May 9, 2017Publication date: November 15, 2018Inventors: Ra-Min TAIN, Kai-Ming YANG, Chien-Tsai LI
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Publication number: 20180096889Abstract: An interconnection structure and a manufacturing method thereof are provided. The method includes the following steps. First, a substrate having a first surface and a second surface opposite to each other is provided. Then, a conductive through via extended from the first surface to the second surface is formed in the substrate. Then, a portion of the substrate is removed from the first surface to expose a portion of the conductive through via. Then, a dielectric layer is formed on the substrate, and the dielectric layer covers the exposed conductive through via. Then, an opening is formed in the dielectric layer, wherein the opening exposes a portion of the conductive through via, and the top surface of the conductive through via protrudes from the bottom surface of the opening. Then, a conductive layer is formed in the opening.Type: ApplicationFiled: November 22, 2017Publication date: April 5, 2018Applicant: Unimicron Technology Corp.Inventors: Dyi-Chung Hu, Yin-Po Hung, Ra-Min Tain, Yu-Hua Chen
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Patent number: 9859159Abstract: An interconnection structure and a manufacturing method thereof are provided. The interconnection structure includes a substrate, a conductive through via, a dielectric layer, and a conductive layer. The substrate has a first surface and a second surface opposite to each other. The conductive through via is disposed in the substrate and extended from the first surface beyond the second surface. The dielectric layer is disposed on the substrate, wherein the dielectric layer has an opening exposing a portion of the conductive through via. The top surface of the conductive through via protrudes from the bottom surface of the opening. The conductive layer is disposed in the opening and connected to the conductive through via.Type: GrantFiled: March 10, 2015Date of Patent: January 2, 2018Assignee: Unimicron Technology Corp.Inventors: Dyi-Chung Hu, Yin-Po Hung, Ra-Min Tain, Yu-Hua Chen
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Publication number: 20170110393Abstract: A circuit board includes a composite layer of a non-conductor inorganic material and an organic material, a plurality of conductive structures, a first built-up structure, and a second built-up structure. The composite layer of the non-conductor inorganic material and the organic material has a first surface and a second surface opposite to each other and a plurality of openings. The conductive structures are respectively disposed in the openings of the composite layer of the non-conductor inorganic material and the organic material. The first built-up structure is disposed on the first surface of the composite layer of the non-conductor inorganic material and the organic material and electrically connected to the conductive structures. The second built-up structure is disposed on the second surface of the composite layer of the non-conductor inorganic material and the organic material and electrically connected to the conductive structures.Type: ApplicationFiled: December 28, 2016Publication date: April 20, 2017Applicant: Unimicron Technology Corp.Inventors: Ra-Min Tain, Kai-Ming Yang, Wang-Hsiang Tsai, Tzyy-Jang Tseng
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Publication number: 20170025342Abstract: A chip package structure including a molding compound, a carrier board, a chip, a plurality of conductive pillars and a circuit board is provided. The carrier board includes a substrate and a redistribution layer. The substrate has a first surface and a second surface. The redistribution layer is disposed on the first surface. The chip and the conductive pillars are disposed on the redistribution layer. The molding compound covers the chip, the conductive pillars, and the redistribution layer. The circuit board is connected with the carrier board, wherein the circuit board is disposed on the molding compound, such that the chip is located between the substrate and the circuit board, and the chip and the redistribution layer are electrically connected with the circuit board through the conductive pillars. Heat generated by the chip is transmitted through the substrate from the first surface to the second surface to dissipate.Type: ApplicationFiled: October 6, 2016Publication date: January 26, 2017Applicant: Unimicron Technology Corp.Inventors: Tzyy-Jang Tseng, Yu-Hua Chen, Ra-Min Tain
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Publication number: 20160268206Abstract: An interconnection structure and a manufacturing method thereof are provided. The interconnection structure includes a substrate, a conductive through via, a dielectric layer, and a conductive layer. The substrate has a first surface and a second surface opposite to each other. The conductive through via is disposed in the substrate and extended from the first surface beyond the second surface. The dielectric layer is disposed on the substrate, wherein the dielectric layer has an opening exposing a portion of the conductive through via. The top surface of the conductive through via protrudes from the bottom surface of the opening. The conductive layer is disposed in the opening and connected to the conductive through via.Type: ApplicationFiled: March 10, 2015Publication date: September 15, 2016Inventors: Dyi-Chung Hu, Yin-Po Hung, Ra-Min Tain, Yu-Hua Chen
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Publication number: 20160190050Abstract: A method for manufacturing an interposer includes the following steps. Conductive beads is filled in a blind via of a substrate and a solder layer of each conductive bead is melted so as to form a solder post in the blind via. A metal ball of each conductive bead is inlaid in the corresponding solder post such that the solder post and the metal balls inlaid therein construct a conductive though via. Two surfaces of the substrate are planarized such that two ends of the conductive through via are exposed to the two surfaces of the substrate respectively and are flush with the two surfaces of the substrate respectively. A redistribution layer is manufactured at each surface of the substrate such that the two ends of each conductive through via connect the redistribution layers respectively. Besides, an interposer and a chip package structure applied the interposer are also provided.Type: ApplicationFiled: December 28, 2014Publication date: June 30, 2016Inventors: Ra-Min Tain, Dyi-Chung Hu, Yu-Hua Chen
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Patent number: 9368442Abstract: A method for manufacturing an interposer includes the following steps. Conductive beads is filled in a blind via of a substrate and a solder layer of each conductive bead is melted so as to form a solder post in the blind via. A metal ball of each conductive bead is inlaid in the corresponding solder post such that the solder post and the metal balls inlaid therein construct a conductive though via. Two surfaces of the substrate are planarized such that two ends of the conductive through via are exposed to the two surfaces of the substrate respectively and are flush with the two surfaces of the substrate respectively. A redistribution layer is manufactured at each surface of the substrate such that the two ends of each conductive through via connect the redistribution layers respectively. Besides, an interposer and a chip package structure applied the interposer are also provided.Type: GrantFiled: December 28, 2014Date of Patent: June 14, 2016Assignee: Unimicron Technology Corp.Inventors: Ra-Min Tain, Dyi-Chung Hu, Yu-Hua Chen
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Patent number: 9111774Abstract: A wafer stack includes: a first wafer having a first substrate and a first device layer having therein at least a chip; a second wafer having a second substrate disposed above the first wafer; and at least a first metal post existing in the first device layer, and arranged between the first and the second substrates, without being electrically connected to the chip.Type: GrantFiled: February 22, 2013Date of Patent: August 18, 2015Assignee: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: Chi-Shih Chang, Ra-Min Tain, Shyi-Ching Liau, Wei-Chung Lo, Rong-Shen Lee
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Patent number: 8810031Abstract: An electronic device having a stacked structure is provided. The electronic device includes a first electronic layer, a second electronic layer disposed on the first electronic layer, and at least a post. The first electronic layer has a first interface, and including a first substrate and a first device layer disposed on the first substrate. The first interface is located between the first substrate and the first device layer, and the first device layer has a surface opposite to the first interface. The post is arranged in the first device layer, and extending from the first interface to the surface of the first device layer.Type: GrantFiled: December 30, 2010Date of Patent: August 19, 2014Assignee: Industrial Technology Research InstituteInventors: Chi-Shih Chang, Ra-Min Tain, Shyi-Ching Liau, Wei-Chung Lo, Rong-Shen Lee
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Patent number: 8674491Abstract: A semiconductor device including a silicon substrate, a plurality of silicon nanowire clusters, a first circuit layer and a second circuit layer. The silicon substrate has a first surface, a second surface opposite to the first surface and a plurality of through holes. The silicon nanowire clusters are disposed in the through holes of the silicon substrate, respectively. The first circuit layer is disposed on the first surface and connected to the silicon nanowire clusters. The second circuit layer is disposed on the second surface and connected to the silicon nanowire clusters.Type: GrantFiled: May 9, 2011Date of Patent: March 18, 2014Assignee: Industrial Technology Research InstituteInventors: Chun-Kai Liu, John H. Lau, Ming-Ji Dai, Ra-Min Tain
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Patent number: 8673658Abstract: A fabricating method and a testing method of a semiconductor device and a mechanical integrity testing apparatus are provided. An object includes a wafer, an insulating layer, and a plurality of conductive posts is provided. A surface of the wafer has a plurality of first blind holes outside chip regions and a plurality of second blind holes inside the chip regions. The insulating layer is between the conductive posts and the walls of the first blind holes and between the conductive posts and the walls of the second blind holes. A mechanical integrity test is performed to test a binding strength between the insulating layer, the conductive posts, and the walls of the first blind holes. The conductive posts in the chip regions are electrically connected to an element after the conductive posts in the first blind holes are qualified in the mechanical integrity test.Type: GrantFiled: February 19, 2013Date of Patent: March 18, 2014Assignee: Industrial Technology Research InstituteInventors: Ming-Che Hsieh, John H. Lau, Ra-Min Tain
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Publication number: 20140056001Abstract: A light emitting diode (LED) light bulb module includes an LED light bulb unit having a first connector; an LED supporting device unit having a second connector which is configured to electrically coupled to the first connector, and a third connector which is configured to electrically coupled to a power supply source; and a thermal insulating structure configured to thermally decouple the LED light bulb unit and the LED supporting device unit. The LED light bulb unit and the LED supporting device unit can be either physically joined or detached from each other, and ideally, two separated heat sink apparatuses, each dedicated to the LED light bulb unit and the LED supporting device unit, respectively may be used.Type: ApplicationFiled: August 24, 2012Publication date: February 27, 2014Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTEInventors: LU-CHEN HSU, CHE-MIN KUNG, RA MIN TAIN
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Patent number: 8552554Abstract: A heat dissipation structure for an electronic device includes a body having a first surface and a second surface opposite to the first surface. A silicon-containing insulating layer is disposed on the first surface of the body. A chemical vapor deposition (CVD) diamond film is disposed on the silicon-containing insulating layer. A first conductive pattern layer is disposed on the silicon-containing insulating layer, wherein the first conductive pattern layer is enclosed by and spaced apart from the CVD diamond film. A method for fabricating a heat dissipation structure for an electronic device and an electronic package having the heat dissipation structure are also disclosed.Type: GrantFiled: December 20, 2011Date of Patent: October 8, 2013Assignee: Industrial Technology Research InstituteInventors: Ra-Min Tain, Ming-Ji Dai, Yon-Hua Tzeng
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Patent number: 8546924Abstract: Package structures for integrating thermoelectric components with stacking chips are presented. The package structures include a chip with a pair of conductive through vias. Conductive elements are disposed one side of the chip contacting the pair of conductive through vias. Thermoelectric components are disposed on the other side of the chip, wherein the thermoelectric component includes a first type conductive thermoelectric element and a second type conductive thermoelectric element respectively corresponding to and electrically connecting to the pair of conductive through vias. A substrate is disposed on the thermoelectric component, wherein the thermoelectric component, the pair of conductive through vias and the conductive element form a thermoelectric current path. Therefore, heat generated from the chip is transferred outward through a thermoelectric path formed from the thermoelectric components, the conductive through vias and the conductive elements.Type: GrantFiled: August 3, 2010Date of Patent: October 1, 2013Assignee: Industrial Technology Research InstituteInventors: Chih-Kuang Yu, Chun-Kai Liu, Ra-Min Tain
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Patent number: 8536701Abstract: An electronic device packaging structure is provided. The semiconductor device includes a semiconductor base, an emitter, a collector, and a gate. The emitter and the gate are disposed on a first surface of the semiconductor base. The collector is disposed on a second surface of the semiconductor base. A first passivation layer is located on the first surface of the semiconductor base surrounding the gate. A first conductive pad is disposed on the first passivation layer. A second conductive pad is disposed on the collector on the second surface. At least one conductive through via structure penetrates the first passivation layer, the first and second surfaces of the semiconductor base, and the collector to electrically connect the first and second conductive pads.Type: GrantFiled: March 5, 2012Date of Patent: September 17, 2013Assignee: Industrial Technology Research InstituteInventors: Ra-Min Tain, Ming-Ji Dai, John H. Lau
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Publication number: 20130234325Abstract: By adding particles of high thermal conductivity and low thermal expansion coefficient into the copper as a composite material and filling with the composite material into the through-via hole, the mismatch of the coefficient of thermal expansion and the stress of the through-silicon via are lowered and the thermal conductivity of the through-silicon via is increased.Type: ApplicationFiled: April 30, 2013Publication date: September 12, 2013Applicant: Industrial Technology Research InstituteInventors: Ming-Ji Dai, Ra-Min Tain, Chun-Hsien Chien, Heng-Chieh Chien, Sheng-Tsai Wu
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Patent number: 8519524Abstract: A chip stacking structure including a carrier, a first redistribution layer, a second redistribution layer, at least one first chip, at least one second chip, and at least one conductor is provided. The carrier has a first surface and a second surface opposite to each other. The carrier has at least one through hole. The first and second redistribution layers are disposed on the first and second surfaces of the carrier, respectively. The first and second chips are disposed on the first and second surfaces of the carrier and electrically connected with the first and second redistribution layers, respectively. The conductor is disposed on one of the first and second chips. The conductor is disposed in the through hole. The first and second chips are electrically connected by the conductor. A gap is formed between the conductor and an inner wall of the carrier which surrounds the through hole.Type: GrantFiled: August 16, 2012Date of Patent: August 27, 2013Assignee: Industrial Technology Research InstituteInventors: Sheng-Tsai Wu, John H. Lau, Heng-Chieh Chien, Ra-Min Tain, Ming-Ji Dai, Yu-Lin Chao
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Patent number: 8507909Abstract: A measuring apparatus including a first chip, a first circuit layer, a first heater, a first stress sensor and a second circuit layer is provided. The first chip has a first through silicon via, a first surface and a second surface opposite to the first surface. The first circuit layer is disposed on the first surface. The first heater and the first stress sensor are disposed on the first surface and connected to the first circuit layer. The second circuit layer is disposed on the second surface. The first heater comprises a plurality of first switches connected in series to generate heat.Type: GrantFiled: November 30, 2011Date of Patent: August 13, 2013Assignee: Industrial Technology Research InstituteInventors: Ra-Min Tain, Ming-Ji Dai, Shyh-Shyuan Sheu, Chih-Sheng Lin, Shih-Hsien Wu
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Measuring apparatus that includes a chip having a through silicon via, a heater, and a stress sensor
Patent number: 8502224Abstract: A measuring apparatus including a first chip, a first circuit layer, a first heater, a first stress sensor and a second circuit layer is provided. The first chip has a first through silicon via, a first surface and a second surface opposite to the first surface. The first circuit layer is disposed on the first surface. The first heater and the first stress sensor are disposed on the first surface and connected to the first circuit layer. The second circuit layer is disposed on the second surface.Type: GrantFiled: December 8, 2010Date of Patent: August 6, 2013Assignee: Industrial Technology Research InstituteInventors: Ra-Min Tain, John H. Lau, Ming-Che Hsieh, Wei Li, Ming-Ji Dai