Abstract: A virtual GPIO interface is provided that receives a transmit set of GPIO signals from a processor. The virtual GPIO interface transmits a portion of the transmit set of GPIO signals over GPIO pins in a conventional fashion. However, the virtual GPIO interface provides a remaining portion of the transmit set of GPIO signals to a finite state machine that serializes the GPIO signals in the remaining portion into frames of virtual GPIO signals. A modified UART interface transmits the frames over a UART transmit pin responsive to cycles of a UART oversampling clock.

Abstract: Systems, methods, and apparatus for communication over to serial bus in accordance with an I3C protocol are described. A method performed at a master device includes causing a line driver to enter a high-impedance mode of operation, and receiving data from the serial bus. When a data line of the serial bus is in a high voltage state while a last bit of a data byte is being transmitted, the line may be configured for an open-drain mode of operation, and transmitting a START condition on the serial bus while the last bit of the data byte is being transmitted.

Abstract: Systems, methods and apparatus are described that offer improved performance of a sensor bus. A first command is transmitted to devices coupled to a serial bus operated in a first mode in accordance with a first protocol to cause the serial bus to be operated in a second mode. After communicating in accordance with a second protocol while the serial bus is operated in the second mode, a second command is transmitted to the plurality of devices in accordance with the first protocol to terminate the second mode. In the second mode, extra symbols inserted into a sequence of symbols transmitted on the serial bus prevent the occurrence of an unintended signaling state on the serial bus. Pulses transmitted on a wire of the serial bus in the second mode may have their duration limited such that a filter of a second device suppresses the limited-duration pulses.

Abstract: System, methods and apparatus offer improved performance for a communication interface that provides for the coexistence of devices on a serial bus. A bus master coupled to a serial bus configures a transceiver for communicating on the serial bus when the serial bus is operated in a high data rate mode of operation on the serial bus, and while the serial bus is operated in the high data rate mode of operation, transmits a first command addressed to an invalid slave device address, and transmits a second command addressed to a valid slave device address. The second command may be defined for transmission when the serial bus is operated in a low data rate mode of operation.

Abstract: Systems, methods and apparatus are described that offer improved performance of a sensor bus. A first command is transmitted to devices coupled to a serial bus operated in a first mode in accordance with a first protocol to cause the serial bus to be operated in a second mode. After communicating in accordance with a second protocol while the serial bus is operated in the second mode, a second command is transmitted to the plurality of devices in accordance with the first protocol to terminate the second mode. In the second mode, extra symbols inserted into a sequence of symbols transmitted on the serial bus prevent the occurrence of an unintended signaling state on the serial bus. Pulses transmitted on a wire of the serial bus in the second mode may have their duration limited such that a filter of a second device suppresses the limited-duration pulses.

Abstract: Systems, methods, and apparatus for communication virtualized general-purpose input/output (GPIO) signals over a serial communication link A method performed at a transmitting device coupled to a communication link includes encoding virtual GPIO signals or messages into a data packet, determining a maximum latency requirement for transmitting the data packet over the communication link, providing a command code header indicating a packet type to be used for transmitting the data packet over the communication link, and transmitting the command code header and the data packet over the communication link in a packet selected to satisfy the maximum latency requirement. A protocol for transmitting the data packet may be determined based on the maximum latency requirement and one or more attributes of protocols available for use on the communication link. In one example, the communication link includes a serial bus and the available protocols include I2C, I3C, and/or RFFE protocols.

Abstract: In an aspect, an integrated circuit obtains a set of general purpose input/output (GPIO) signals for one or more peripheral devices, obtains a first virtual GPIO packet that includes the set of GPIO signals independent of a central processing unit, and transmits the first virtual GPIO packet to the one or more peripheral devices over an I3C bus independent of the central processing unit. The integrated circuit may further obtain a set of configuration signals for configuring one or more GPIO pins of the one or more peripheral devices, obtain a second virtual GPIO packet that includes the set of configuration signals independent of the central processing unit, and transmit the second virtual GPIO packet to the one or more peripheral devices over the I3C bus independent of the central processing unit.

Abstract: Disclosed are methods and apparatus for transmitting sensor timing correction messages with a host controller. The methods and apparatus determine synchronization messages that are transmitted to a sensor coupled with the host controller via an interface, where the messages indicate a beginning of a synchronization period for synchronizing timing of the host controller and the sensor. Additionally, a delay time message is determined that indicates a time delay between the beginning of the synchronization period and an actual transmission time of the synchronization message. The synchronization message is transmitted with the delay time message in an information message to the sensor, where information message is configured to allow the sensor to correct timing of a sensor timer by accounting for the delay time.

Abstract: Disclosed are methods and apparatus for synchronizing a controller and sensors in a system. A timestamp is provided in a host controller of an interface event on an interface coupled with host controller through detecting a message from a sensor on the interface that identifies the issuance of the interface event caused by the sensor at a first time. In response, the controller issues first and second events on the interface at respective second and third times, while concurrently counting cycles of a clock in the controller after each issuance. The controller also receives a first and second sensor counts representing the internal sensor clock times noted for the first and second events. The controller may then accurately calculate the timestamp of the interface event corresponding to the first time based on both internal controller counts and the sensor counts without needing a timestamp from the sensor directly.

Abstract: Disclosed aspects relate to methods and apparatus for correcting a first sensor clock of a first sensor. The disclosed methods and apparatus effectuate receiving first and seconds signals in a sensor from a processor at known different times related to the timing of the processor clock. Based on the measured time interval between the times of the first and second signals as determined by the sensor, a clock correction factor may be determined in the sensor for correcting the timing of the sensor clock to be synchronized with the processor clock.

Abstract: System, methods and apparatus are described that offer improved performance of an Inter-Integrated Circuit (I2C) bus. A method of testing a spike filter in a legacy I2C device includes generating a command to be transmitted on a serial bus in accordance with an I2C protocol, where the command includes an address corresponding to the legacy slave device, merging the command with a sequence of pulses to obtain a test signal, transmitting the test signal on the serial bus, and determining the efficacy of a spike filter in the first slave device based on whether the legacy slave device acknowledges the test signal. Each pulse in the sequence of pulses has a duration that is less than 50 ns. The spike filter is expected to suppress pulses that have a duration of less than 50 ns.

Abstract: A system including a switch and a control circuit. The switch is configured to receive a first voltage. The control circuit is configured to, during a rising portion of a half cycle of the first voltage, (i) turn on the switch in response to the first voltage reaching a first value, and (ii) turn off the switch in response to the first voltage reaching a second value, where the second value is greater than the first value. The control circuit is further configured to, during a falling portion of the half cycle of the first voltage, (i) turn on the switch in response to the first voltage reaching the second value, and (ii) turn off the switch in response to the first voltage reaching the first value.

Abstract: In one embodiment, a dimmer circuit is coupled to an electronic load and receives an alternating current (AC) signal. A phase control circuit turns the dimmer circuit on for a first portion of the AC signal to turn on the electronic load. The dimmer circuit turns off during a second portion of the AC signal to turn off the electronic load. A switch is coupled to the phase control circuit. The switch is controlled to couple the phase control circuit to ground when the dimmer circuit is off where the switch is part of a power supply supplying power to the electronic load.

Abstract: System, methods and apparatus are described that facilitate a device to encode/decode data in a data communications interface coupled to a plurality of wires. The device determines a value of a sequence of data bits allocated to a frame, converts the value into a sequence of symbols associated with the frame, and transmits the sequence of symbols to a receiver. The device performs the converting by calculating base-N coefficients of a base-N number polynomial for the frame based on the value, where N is greater than 2, calculating base-2 coefficients of a base-2 number polynomial for each symbol according to a respective base-N coefficient corresponding to each symbol, determining changes of states of the plurality of wires for each symbol according to the base-2 coefficients respectively calculated for each symbol, and generating the sequence of symbols based on the changes of states of the plurality of wires for each symbol.

Abstract: Aspects of the invention are related to a method for synchronizing a first sensor clock of a first sensor. The exemplary method comprises: correcting the first sensor clock for a first time, transferring data from the first sensor, and correcting the first sensor clock for a second time, wherein a time interval between two corrections of the first sensor clock is selected such that the first sensor clock is sufficiently aligned with a processor clock of a processor over the time interval.

Abstract: Embodiments of the invention provide for a sensor system with enhanced low-power features. Embodiments can include transmission of sensor data from a transmitter unit to a receiver unit. The sensor data can flag the sensor data with a particular header ID, enabling the receiver unit to route the sensor data to a low-power processing unit within the receiver unit without using the receiver unit's higher-power application processer. Embodiments can also utilize a proprietary encryption engine to provide a supplementary encryption layer to any encryption utilized in the wireless protocol. The transmitter unit can also compress and batch the sensor data for sending, to further increase power savings.

Abstract: A device is provided comprising a shared bus including a first and a second line, a first subset of devices and a second subset of devices coupled to the shared bus. The first subset of devices may be configured to operate according to a first protocol mode. The second subset of devices may be configured to operate according to a second protocol mode, wherein the second protocol mode is distinct from the first protocol mode. A first device within the first subset of devices may include a receiver circuit adapted to adjust a signal transition occurring on the first line while the second line is in a first logical state so that the signal transition instead occurs when the second line is in a second logical state. The signal transition is adjusted only if it occurs within a threshold amount of time from a second transition on the second line.

Abstract: Methods, systems, computer-readable media, and apparatuses for assessing a fitness state of a user via a mobile device are presented. In some implementations, a first physiological measurement of the user during a first level of a physical activity is obtained via one or more sensors. A second physiological measurement during a second level of the physical activity is obtained via the one or more sensors. A transient physiological measurement based on the first physiological measurement and the second physiological measurement is determined. The physical activity is classified based on one or more motion measurements obtained via the one or more sensors. A fitness profile indicative of a fitness state of the user is generated based at least in part on the determined transient physiological measurement and the classified physical activity.

Abstract: A virtual GPIO interface is provided that receives a transmit set of GPIO signals from a processor. The virtual GPIO interface transmits a portion of the transmit set of GPIO signals over GPIO pins in a conventional fashion. However, the virtual GPIO interface provides a remaining portion of the transmit set of GPIO signals to a finite state machine that serializes the GPIO signals in the remaining portion into frames of virtual GPIO signals. A modified UART interface transmits the frames over a UART transmit pin responsive to cycles of a UART oversampling clock.

Abstract: Disclosed is an apparatus and method for automatically configuring a mobile device for collecting and inferring heart rate data of a user. The method may include capturing heart rate data for a user with a heart rate sensor that is coupled with a mobile device. The method may also include monitoring a activity state of the user from activity data captured by the mobile device, and detecting a constant activity state of the user. The method may also include inferring heart rate data for the user from the captured heart rate data during a period in which the user remains in the constant activity state. The method may also include providing the inferred heart rate data, as captured heart rate data, to a heart rate calculator during the period in which the user remains in the constant activity state.