Patents by Inventor Rafael C. Camarota

Rafael C. Camarota has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10963411
    Abstract: Programmable devices and methods of operation are disclosed. In some embodiments, a programmable device may include programmable logic selectively coupled to a plurality of input/output (I/O) interface circuits by a programmable interconnect fabric and a network-on-chip (NoC) interconnect system. The programmable logic may include configurable logic elements, programmable interconnects, and dedicated circuitry. The programmable interconnects may form part of the programmable interconnect fabric. In some embodiments, the programmable interconnect fabric selectively routes non-packetized data between the programmable logic and a first group of I/O interface circuits, and the NoC interconnect system selectively routes packetized data between the programmable logic and a second group of I/O interface circuits. The NoC interconnect system may operate according to a data packet protocol, and the second group of I/O interface circuits may include memory controllers compatible with the data packet protocol.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: March 30, 2021
    Assignee: XILINX, INC.
    Inventors: Martin L. Voogel, Trevor J. Bauer, Rafael C. Camarota
  • Patent number: 10929331
    Abstract: Examples described herein generally relate to a layered boundary interconnect in an integrated circuit (IC) and methods for operating such IC. In an example, an IC includes a programmable logic region, a plurality of input/output circuits, a plurality of hard block circuits, and a programmable native transmission network. The programmable native transmission network is connected to and between the plurality of input/output circuits and the plurality of hard block circuits. The plurality of hard block circuits is connected to and between the programmable native transmission network and the programmable logic region.
    Type: Grant
    Filed: April 18, 2019
    Date of Patent: February 23, 2021
    Assignee: XILINX, INC.
    Inventor: Rafael C. Camarota
  • Publication number: 20210050853
    Abstract: Examples generally relate a programmable device having a unified programmable computational memory (PCM) and configuration network. In an example, a programmable device includes a die that includes a PCM integrated circuit having a PCM tile. The PCM tile includes a configuration memory (CM) and combinational logic (CL). The CM is capable of storing configuration data received via a node in the PCM tile. The CL is configured to receive internal control signal(s) and first and second input signals and to output a result signal. The CL is capable of outputting the result signal resulting from a logic function that is responsive to the internal control signal(s) and a signal of a group of signals including the first and second input signals. The CL is configured to receive the first input signal via the node in the PCM tile.
    Type: Application
    Filed: May 26, 2020
    Publication date: February 18, 2021
    Inventor: Rafael C. CAMAROTA
  • Patent number: 10784121
    Abstract: Methods and apparatus are described for adding one or more features (e.g., high bandwidth memory (HBM)) to an existing qualified stacked silicon interconnect (SSI) technology programmable IC die (e.g., a super logic region (SLR)) without changing the programmable IC die (e.g., adding or removing blocks). One example integrated circuit (IC) package generally includes a package substrate; at least one interposer disposed above the package substrate and comprising a plurality of interconnection lines; a programmable IC die disposed above the interposer; a fixed feature die disposed above the interposer; and an interface die disposed above the interposer and configured to couple the programmable IC die to the fixed feature die using a first set of interconnection lines routed through the interposer between the programmable IC die and the interface die and a second set of interconnection lines routed through the interposer between the interface die and the fixed feature die.
    Type: Grant
    Filed: August 15, 2016
    Date of Patent: September 22, 2020
    Assignee: XILINX, INC.
    Inventor: Rafael C. Camarota
  • Patent number: 10763862
    Abstract: Examples described herein provide for a boundary logic interface (BLI) to a programmable logic region in an integrated circuit (IC), and methods for operating such IC. An example IC includes a programmable logic region and boundary logic interfaces. The programmable logic region includes columns of interconnect elements disposed between columns of logic elements. The boundary logic interfaces are at respective ends of and communicatively connected to the columns of interconnect elements. The boundary logic interfaces are outside of a boundary of the programmable logic region. A first boundary logic interface (BLI) of the boundary logic interfaces is configured to be communicatively connected to an exterior circuit. The first BLI includes an interface configured to communicate a signal between the exterior circuit and the programmable logic region.
    Type: Grant
    Filed: February 26, 2019
    Date of Patent: September 1, 2020
    Assignee: XILINX, INC.
    Inventors: Rafael C. Camarota, Ui S. Han, Weiguang Lu
  • Publication number: 20200274536
    Abstract: Examples described herein provide for a boundary logic interface (BLI) to a programmable logic region in an integrated circuit (IC), and methods for operating such IC. An example IC includes a programmable logic region and boundary logic interfaces. The programmable logic region includes columns of interconnect elements disposed between columns of logic elements. The boundary logic interfaces are at respective ends of and communicatively connected to the columns of interconnect elements. The boundary logic interfaces are outside of a boundary of the programmable logic region. A first boundary logic interface (BLI) of the boundary logic interfaces is configured to be communicatively connected to an exterior circuit. The first BLI includes an interface configured to communicate a signal between the exterior circuit and the programmable logic region.
    Type: Application
    Filed: February 26, 2019
    Publication date: August 27, 2020
    Applicant: Xilinx, Inc.
    Inventors: Rafael C. Camarota, Ui S. Han, Weiguang Lu
  • Publication number: 20200264901
    Abstract: Examples described herein provide for an integrated circuit (IC) having a programmable logic region that is capable of being configured via a programmable network. In an example, an IC includes a programmable logic region, a controller, and a programmable network. The programmable network is connected between the controller and the programmable logic region. The controller is programmed to configure the programmable logic region via the programmable network. In some examples, the programmable logic region can be configured faster, among other benefits.
    Type: Application
    Filed: February 14, 2019
    Publication date: August 20, 2020
    Applicant: Xilinx, Inc.
    Inventors: Rafael C. Camarota, David P. Schultz
  • Patent number: 10673440
    Abstract: Examples generally relate a programmable device having a unified programmable computational memory (PCM) and configuration network. In an example, a programmable device includes a die that includes a PCM integrated circuit having a PCM tile. The PCM tile includes a configuration memory (CM) and combinational logic (CL). The CM is capable of storing configuration data received via a node in the PCM tile. The CL is configured to receive internal control signal(s) and first and second input signals and to output a result signal. The CL is capable of outputting the result signal resulting from a logic function that is responsive to the internal control signal(s) and a signal of a group of signals including the first and second input signals. The CL is configured to receive the first input signal via the node in the PCM tile.
    Type: Grant
    Filed: August 13, 2019
    Date of Patent: June 2, 2020
    Assignee: XILINX, INC.
    Inventor: Rafael C. Camarota
  • Patent number: 10621132
    Abstract: Embodiments herein describe techniques for assigning address ranges to ports in switches forming a packet protocol switch network in an integrated circuit. Instead of relying on a designer to provide the addresses, the integrated circuit can include an address bus which is incremented as addresses are assigned to the ports. In one embodiment, the port addresses are assigned from a root device and defines the address range of each branch port and the address of each endpoint in the network. As the address bus reaches an endpoint, an adder in the endpoint increments the value of the address bus (e.g., the current address). The address bus may use serial or parallel data communication to assign the addresses. In another embodiment, instead of using a separate address bus, a data bus typically used for packet communication assigns the addresses to the ports in the network.
    Type: Grant
    Filed: May 5, 2017
    Date of Patent: April 14, 2020
    Assignee: XILINX, INC.
    Inventors: Rafael C. Camarota, Ian A. Swarbrick, Kin Yip Sit
  • Patent number: 10502785
    Abstract: A network on a chip (NoC) testing interface (NTI) includes a plurality of switches whose ports are coupled to respective endpoints. In one embodiment, the ports and endpoints are coupled to a shared bus that starts and terminates at a root device. The endpoints are assigned unique address which the NTI uses to select one of the endpoints so that test data is forwarded to a device under test (DUT) coupled to the endpoint. In one embodiment, the endpoints include selection logic for determining whether the endpoint has been selected, and if so, forwarding test data to the DUT. For example, if the endpoint receives a data vector on the bus which has an address that matches the unique address of the endpoint, the selection logic forwards the test data contained in subsequently received data vectors to the DUT until a different address is received.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: December 10, 2019
    Assignee: XILINX, INC.
    Inventor: Rafael C. Camarota
  • Patent number: 10177107
    Abstract: Methods and apparatus are described for strategically arranging conductive elements (e.g., solder balls) of an integrated circuit (IC) package (and the corresponding conductive pads of a circuit board for electrical connection with the IC package) using a plurality of different pitches. One example integrated circuit (IC) package generally includes an integrated circuit die and an arrangement of electrically conductive elements coupled to the integrated circuit die. In at least one region of the arrangement, the conductive elements are disposed with a first pitch in a first dimension of the arrangement and with a second pitch in a second dimension of the arrangement, and the second pitch is different from the first pitch. The pitch of a given region may be based on mechanical, PCB routing, and/or signal integrity considerations.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: January 8, 2019
    Assignee: XILINX, INC.
    Inventor: Rafael C. Camarota
  • Patent number: 10069497
    Abstract: A circuit for implementing a scan chain in programmable resources of an integrated circuit is described. The circuit comprises a programmable element configured to receive an input signal and generate an output signal based upon the input signal; a selection circuit configured to receive the output signal generated by the programmable element at a first input and to receive a scan chain input signal at a second input, wherein the selection circuit generates a selected output signal in response to a selection circuit control signal; and a register configured to receive the selected output signal of the selection circuit.
    Type: Grant
    Filed: June 23, 2016
    Date of Patent: September 4, 2018
    Assignee: XILINX, INC.
    Inventors: Benjamin S. Devlin, Rafael C. Camarota
  • Patent number: 9911465
    Abstract: Methods and apparatus are described for adding one or more features (e.g., HBM) to a qualified SSI technology programmable IC region by providing an interface (e.g., an HBM buffer region with a switch network) between the added feature device and the programmable IC region. One example IC package generally includes a package substrate; at least one interposer disposed above the package substrate; a programmable IC region disposed above the interposer; at least one fixed feature die disposed above the interposer; and an interface region disposed above the interposer and configured to couple the programmable IC region to the fixed feature die via a first set of interconnection lines routed through the interposer between a first plurality of ports of the interface region and the fixed feature die and a second set of interconnection lines routed between a second plurality of ports of the interface region and the programmable IC region.
    Type: Grant
    Filed: November 8, 2016
    Date of Patent: March 6, 2018
    Assignee: XILINX, INC.
    Inventors: Rafael C. Camarota, Sagheer Ahmad, Martin Newman
  • Publication number: 20180047663
    Abstract: Methods and apparatus are described for adding one or more features (e.g., high bandwidth memory (HBM)) to an existing qualified stacked silicon interconnect (SSI) technology programmable IC die (e.g., a super logic region (SLR)) without changing the programmable IC die (e.g., adding or removing blocks). One example integrated circuit (IC) package generally includes a package substrate; at least one interposer disposed above the package substrate and comprising a plurality of interconnection lines; a programmable IC die disposed above the interposer; a fixed feature die disposed above the interposer; and an interface die disposed above the interposer and configured to couple the programmable IC die to the fixed feature die using a first set of interconnection lines routed through the interposer between the programmable IC die and the interface die and a second set of interconnection lines routed through the interposer between the interface die and the fixed feature die.
    Type: Application
    Filed: August 15, 2016
    Publication date: February 15, 2018
    Applicant: Xilinx, Inc.
    Inventor: Rafael C. Camarota
  • Publication number: 20180033753
    Abstract: Methods and apparatus are described for strategically arranging conductive elements (e.g., solder balls) of an integrated circuit (IC) package (and the corresponding conductive pads of a circuit board for electrical connection with the IC package) using a plurality of different pitches. One example integrated circuit (IC) package generally includes an integrated circuit die and an arrangement of electrically conductive elements coupled to the integrated circuit die. In at least one region of the arrangement, the conductive elements are disposed with a first pitch in a first dimension of the arrangement and with a second pitch in a second dimension of the arrangement, and the second pitch is different from the first pitch. The pitch of a given region may be based on mechanical, PCB routing, and/or signal integrity considerations.
    Type: Application
    Filed: August 1, 2016
    Publication date: February 1, 2018
    Applicant: Xilinx, Inc.
    Inventor: Rafael C. Camarota
  • Patent number: 9882562
    Abstract: An integrated circuit (IC) die and integrated circuit (IC) chip packages having such dies are described that leverage the symmetry of the arrangement of micro-bumps to advantageously reduce interposer cost and size requirements. In one example, an integrated circuit (IC) die is provided. The IC die includes a die body, a plurality of programmable tiles disposed in the die body, and a plurality of micro-bumps disposed in the die body. The die body includes a front face connecting a bottom exterior surface and a top exterior surface. A centerline of the die body is perpendicular to the front face and bifurcates the top exterior surface. At least two of the programmable tiles are of a common type. The micro-bumps adjacent the front face and coupled to the common type of programmable tiles have a substantially symmetrical orientation relative to a symmetry axis. The symmetry axis being one of (a) collinear with the centerline of the die body, or (b) parallel to the centerline of the die body.
    Type: Grant
    Filed: December 7, 2016
    Date of Patent: January 30, 2018
    Assignee: XILINX, INC.
    Inventors: Martin L. Voogel, Rafael C. Camarota, Henri Fraisse
  • Publication number: 20170373692
    Abstract: A circuit for implementing a scan chain in programmable resources of an integrated circuit is described. The circuit comprises a programmable element configured to receive an input signal and generate an output signal based upon the input signal; a selection circuit configured to receive the output signal generated by the programmable element at a first input and to receive a scan chain input signal at a second input, wherein the selection circuit generates a selected output signal in response to a selection circuit control signal; and a register configured to receive the selected output signal of the selection circuit.
    Type: Application
    Filed: June 23, 2016
    Publication date: December 28, 2017
    Applicant: Xilinx, Inc.
    Inventors: Benjamin S. Devlin, Rafael C. Camarota
  • Patent number: 9547034
    Abstract: An apparatus for a monolithic integrated circuit die is disclosed. In this apparatus, the monolithic integrated circuit die has a plurality of modular die regions. The modular die regions respectively have a plurality of power distribution networks for independently powering each of the modular die regions. Each adjacent pair of the modular die regions is stitched together with a respective plurality of metal lines.
    Type: Grant
    Filed: July 3, 2013
    Date of Patent: January 17, 2017
    Assignee: XILINX, INC.
    Inventor: Rafael C. Camarota
  • Patent number: 9204542
    Abstract: An apparatus includes a package substrate for a first SSIT product with a first top die configuration, wherein the package substrate is compatible with a second SSIT product with a second top die configuration, and wherein the first top die configuration is different from the second top die configuration.
    Type: Grant
    Filed: January 7, 2013
    Date of Patent: December 1, 2015
    Assignee: XILINX, INC.
    Inventors: Tien-Yu Lee, Rafael C. Camarota
  • Patent number: 9083340
    Abstract: An integrated circuit comprises a memory matrix including: a first memory cell array; a first multiplexer (MUX) coupled to an input of the first memory cell array; a second MUX coupled to an output of the first memory cell array; a second memory cell array; a third MUX coupled to an input of the second memory cell array; and a fourth MUX coupled to an output of the second memory cell array. The second MUX is coupled to the fourth MUX. The fourth MUX is configured to pass a selected one of: (1) an output from the third MUX, (2) an output from the second memory cell array, or (3) an output from the second MUX.
    Type: Grant
    Filed: May 15, 2014
    Date of Patent: July 14, 2015
    Assignee: XILINX, INC.
    Inventors: Ephrem C. Wu, Hongbin Ji, Rafael C. Camarota