Abstract: For a programmable Logic Array (PLA) having a nominal operating voltage, a method for ensuring reliable operation of the PLA during a configuration memory read operation comprises steps of (a) providing an intentionally weak pass gate for memory cells in the configuration memory, too weak to flip latches of the memory cells with nodes of the cells powered at the nominal operating voltage; and (b) powering the nodes of the cells with a voltage-controlled source, allowing voltage for the nodes to be reduced during write so latches may be flipped by the weak passgate, and allowing voltage to return to the nominal higher value during read, such that the weak pass gates cannot flip latches. A memory cell with such a weak passgate and operating characteristics is taught, a configuration memory using such cells, and a Programmable Logic Array with such a configuration memory.

Abstract: A method for testing a programmable logic device having defined programmable function blocks with programmable interconnects follows steps of (a) configuring, by programming, two or more similar groups of the function blocks and interconnects into identical state machines; (b) operating the programmed state machines by clock and reset signals to generate individual original signatures on global interconnect lines; and (c) comparing the original signatures of the two or more state machines for fault detection. Original signatures from different programmed groups of function blocks and interconnects at different dedicated test output blocks are compressed and passed to signature analysis circuitry where a final signature is analyzed as in indicator of faults. A microcontroller is taught for configuring and performing tests.

Abstract: For a programmable Logic Array (PLA) having a nominal operating voltage, a method for ensuring reliable operation of the PLA during a configuration memory read operation comprises steps of (a) providing an intentionally weak pass gate for memory cells in the configuration memory, too weak to flip latches of the memory cells with nodes of the cells powered at the nominal operating voltage; and (b) powering the nodes of the cells with a voltage-controlled source, allowing voltage for the nodes to be reduced during write so latches may be flipped by the weak passgate, and allowing voltage to return to the nominal higher value during read, such that the weak pass gates cannot flip latches. A memory cell with such a weak passgate and operating characteristics is taught, a configuration memory using such cells, and a Programmable Logic Array with such a configuration memory.

Abstract: An improved programmable logic device that generates output signals skewed in time includes a set of I/O cells and first and second logic circuits. Each logic circuit generates a logic output signal on a respective output line coupled to at least one of the I/O cells. A first delay element coupled to the output line of the first logic circuit is programmably operable to delay the output signal of the first logic circuit relative to the output signal of the second logic circuit in response to a first delay control signal. A second delay element coupled to the output line of the second logic circuit is programmably operable to delay the output signal of the second logic circuit relative to the output signal of the first logic circuit in response to a second delay control signal. Control circuitry generates the first and second delay control signals so as to prevent simultaneous switching of the logic output signals of the first and second logic circuits.

Abstract: A memory system with an operating voltage of Vcc has a memory cell with first and second inverters connected input to output to make a latch defining a Q node and a QB node, and powered by a single voltage controlled Vmm line. There is a passgate transistor connected source to drain from a BIT line to the first inverter, the passgate having a strength low enough that, with Vmm substantially equal to Vcc and the gate of the passgate energized at Vcc by a WORD signal, no signal on the BIT line can flip the latch. Circuitry is provided for reducing the voltage of Vmm during a write cycle, so a signal on the BIT line may flip the latch. In preferred embodiments the memory system is applied to Programmable Logic Arrays.

Abstract: A method for minimizing instantaneous currents ina signal bus is disclosed. The method involves providing a programmable delay element in each of the signal buffers driving the signal on the bus. The programmable delay element in each signal buffer is selectable enabled to include a predetermined time delay. The method involves programming the delay elements in a selected group of the signal buffers t includde the predetermined time delay, so that the selected group of signal buffers each generate an output signal switching after the predetermined delay relative to the switching of output signals generated by other signal buffers.

Abstract: An improved programmable logic device includes a set of I/O cells, a set of logic blocks, and a routing pool that provides connections among the logic blocks and the I/O cells. At least one of the logic blocks includes a programmable logic array that generates product term output signals on product term output lines. A first product term summing circuit has input terminals, at least one of which is coupled to a product term output line. The first product term summing circuit generates an output signal at an output terminal in response to at least one product term output signal. Likewise, a second product term summing circuit has input terminals, at least one of which is coupled to a product term output line. The second product term summing circuit generates an output signal at an output terminal in response to at least one product term output signal.

Abstract: A programmable integrated circuit device includes a plurality of output terminals, each output terminal for use in transmitting a respective output signal. Timing control circuitry is connected to the output terminals. The timing control circuitry is operable to delay the output signal on each output terminal and is further operable to control a slew rate of the output signal on each output terminal.

Abstract: A circuit for providing programmable voltage output levels in a logic device includes a pull-up device for driving an output pad with either a first voltage output level or a second voltage output level. A charge pump generates a pumped voltage. A first clamp regulator, coupled to the charge pump and the pull-up device, receives a first reference signal. The first clamp regulator, in response to the first reference signal, generates a first voltage from which the first voltage output level is derived. A second clamp regulator, coupled to the pull-up device, receives a second reference signal. In response to the second reference signal, the second clamp regulator generates a second voltage from which the second voltage output level is derived. A passgate multiplexer is coupled to the first and second clamp regulators. The passgate multiplexer receives at least one output voltage select signal.

Abstract: An apparatus and method for reprogramming a reconfigurable-logic array is provided whereby a portion of the array can be reconfigured without disrupting the operation of the entire array. Avoiding total disruption of array operation typically requires that the configuration control signals, which determine the configuration of the array, remain substantially non-disrupted during a reprogramming operation. In one embodiment, the reprogramming operates by unique decoding in which an electrical path is established only between the particular storage elements being reprogrammed, thereby avoiding disruption of the configuration control signals provided by other storage elements. In other embodiments, buffers and/or read-modify-write techniques are used to minimize disruption of configuration control signals of storage elements not being reprogrammed.

Abstract: An apparatus and method for reprogramming a reconfigurable-logic array is provided whereby a portion of the array can be reconfigured without disrupting the operation of the entire array. Avoiding total disruption of array operation typically requires that the configuration control signals, which determine the configuration of the array, remain substantially non-disrupted during a reprogramming operation. In one embodiment, the reprogramming operates by unique decoding in which an electrical path is established only between the particular storage elements being reprogrammed, thereby avoiding disruption of the configuration control signals provided by other storage elements. In other embodiments, buffers and/or read-modify-write techniques are used to minimize disruption of configuration control signals of storage elements not being reprogrammed.

Abstract: The present invention provides circuitry for compensating the slew rate of an output buffer so as to reduce the magnitude of the variation in slew rate and ground bounce due to temperature and processing variations. The circuitry includes structure at the gate of each transistor that supplies or sinks current to charge or discharge capacitance at the output buffer output that slows down the turn on of the output transistors as temperature or process shifts in a way that would tend to increase the current carrying capability of the output transistor. The structure includes a transmission gate having its source connected to the gate of the output transistor, its drain connected to a capacitor, and its gate connected such that it is conducting.

Abstract: The present invention is directed to various configuration features of a logic array that includes a plurality of individually configurable logic cells arranged in a matrix. These features include reconfiguration logic for reconfiguring logic cells in a selected portion of the matrix using a window-based protocol. The array also includes configuration data storage means for storing configuration data utilizable for configuring the logic elements, wherein each logic element includes a working data storage register, and reset circuitry for modifying the configuration data without modifying the working data. The array further includes read disable circuitry and write disable circuitry for disabling read access and write access, respectively, to the configuration data. The array further includes a comparison protocol mechanism for checking the configuration data against data on the array pins.

Abstract: The present invention provides power up detect circuit for generating a reset signal for a logic circuit that includes N-channel transistors having a threshold value Vnth and P-channel transistors having a threshold value Vpth. The power-up detect circuit includes comparison means having first and second inputs; clamping means for clamping the first comparison means input at X*Vnth above ground potential; and monitoring means connected to the second comparison means input and responsive to ramp up of a power supply voltage for holding the second comparison means input at X*Vpth less than the power supply voltage whereby the comparison means output switches from an inactive state to an active state when the power supply to ground potential reaches (X*Vnth)+(X*Vpth).

Abstract: The present invention provides a configurable logic array that includes a plurality of individually configurable logic cells arranged in a matrix that includes a plurality of rows of logic cells and a plurality of columns of logic cells. The array further includes at least one horizontally aligned local bus running between adjacent rows of logic cells, the logic cells in the adjacent rows being connectable thereto, and at least one vertically aligned local bus running between adjacent columns of logic cells, the logic cells in the adjacent columns being connectable thereto. The array also includes means for configuring the array such that any logic cell A in the array can write to a local bus which can be linked through the array's bussing network so that logic cell A can be read by any other logic cell B; correspondingly, logic cell B can write to a local bus which is linked through the same components such that data written by logic cell B can be read by logic cell A.

Abstract: A low transistor count programmable bussing resource for a programmable logic array allows the use of the bussing resources as inputs or outputs to a cell in the array and allows connections between different buses without effecting the normal use of the cell. The bussing resource allows efficient routing of signals between cells and is symmetric to allow rotation of logic macros built using combinations of cells and buses.

Abstract: An improved programmable logic cell for use in a programmable logic array comprising cells which are arranged in a two-dimensional matrix of rows and columns and are interconnected by a two-dimensional array of direct connections between a cell and its four nearest neighbors, one to its left (or to the West), and one to its right (or to the East), one above it (or to the North) and one below it (or to the South). Each cell receives input(s) from each of its nearest neighbors and additional input(s) (from a bus, pin, or neighbor) and may be programmed to generate a variety of logical functions at its outputs which connect to the cell's four nearest neighbors. The core of the improved logic cell comprises two upstream gates, the outputs of which feed two downstream gates, one of which is an exclusive-OR gate which feeds a downstream register.

Abstract: A programmable logic array comprising cells and a bus network in which the cells are arranged in a two-dimensional matrix of rows and columns and are interconnected by the bus network. The cells are also interconnected by a two-dimensional array of direct connections between a cell and its four nearest neighbors, one to its left (or to the West), one to its right (or to the East), one above it (or to the North) and one below it (or to the South). Each cell comprises eight inputs, eight outputs, means for multiplexing the eight inputs onto two leads and logic means that operate in response to the signals on the two leads to produce output signals which are applied to the eight outputs. The bus network comprises a local, a turning and an express bus for each row and column of the array and repeater means for partitioning said buses of a given row or column so as to form bus segments. The bus network provides for transfer of data to the cells of the array without using the cells as individual wires.

Abstract: A programmable logic array comprising cells and a bus network in which the cells are arranged in a two-dimensional matrix of rows and columns and are interconnected by the bus network. The cells are also interconnected by a two-dimensional array of direct connections between a cell and its four nearest neighbors, one to its left (or to the West), one to its right (or to the East), one above it (or to the North) and one below it (or to the South). Each cell comprises eight inputs, eight outputs, means for multiplexing the eight inputs onto two leads and logic means that operate in response to the signals on the two leads to produce output signals which are applied to the eight outputs. The bus network comprises a local, a turning and an express bus for each row and column of the array and repeater means for partitioning said buses of a given row or column so as to form bus segments. The bus network provides for transfer of data to the cells of the array without using the cells as individual wires.

Abstract: Disclosed is a memory cell which includes a plurality of pass gates in the read word and write word lines. The pass gates are connected in series and each pass gate is controlled by a separate line, namely, by a write word line or a read word line. By use of two or more pass gates in this manner, logical functions, such as logical AND functions are performed within the memory cell.