Abstract: An apparatus for a monolithic integrated circuit die is disclosed. In this apparatus, the monolithic integrated circuit die has a plurality of modular die regions. The modular die regions respectively have a plurality of power distribution networks for independently powering each of the modular die regions. Each adjacent pair of the modular die regions is stitched together with a respective plurality of metal lines.

Abstract: An apparatus includes a package substrate for a first SSIT product with a first top die configuration, wherein the package substrate is compatible with a second SSIT product with a second top die configuration, and wherein the first top die configuration is different from the second top die configuration.

Abstract: An integrated circuit comprises a memory matrix including: a first memory cell array; a first multiplexer (MUX) coupled to an input of the first memory cell array; a second MUX coupled to an output of the first memory cell array; a second memory cell array; a third MUX coupled to an input of the second memory cell array; and a fourth MUX coupled to an output of the second memory cell array. The second MUX is coupled to the fourth MUX. The fourth MUX is configured to pass a selected one of: (1) an output from the third MUX, (2) an output from the second memory cell array, or (3) an output from the second MUX.

Abstract: An integrated circuit (IC) structure can include a first die and a second die. The second die can include a first base unit and a second base unit. Each of the first base unit and the second base unit is self-contained and no signals pass between the first base unit and the second base unit within the second die. The IC structure can include an interposer. The interposer includes a first plurality of inter-die wires coupling the first die to the first base unit, a second plurality of inter-die wires coupling the first die to the second base unit, and a third plurality of inter-die wires coupling the first base unit to the second base unit.

Abstract: An apparatus for a monolithic integrated circuit die is disclosed. In this apparatus, the monolithic integrated circuit die has a plurality of modular die regions. The modular die regions respectively have a plurality of power distribution networks for independently powering each of the modular die regions. Each adjacent pair of the modular die regions is stitched together with a respective plurality of metal lines.

Abstract: A multi-port memory cell is disclosed that includes first and second cross-coupled inverter circuits. The input node of each inverter circuit is coupled to the output node of the other inverter circuit to receive the inverted output of the other inverter circuit. The multi-port memory cell includes a first pair of access transistors of a first type, each coupled to the input node of a respective one of the first and second inverter circuits. The multi-port memory cell also includes a second pair of access transistors of the second type, each coupled to the input of a respective one of the first and second inverter circuits. The multi-port cell exhibits advantages in layout compactness and SEU tolerance.

Abstract: An embodiment of an interposer is disclosed. In such an embodiment, there is a first printed circuit region and a second printed circuit region. The second printed circuit region is proximate to the first printed circuit region with a seam region between the first printed circuit region and the second printed circuit region. The seam region includes a first die seal and a second die seal spaced apart from one another with a scribe line located between the first die seal and the second die seal.

Abstract: A method of characterizing a die can include correlating, using a processor, a static voltage profile of a die under test in wafer form with a plurality of test static voltage profiles. The plurality of test static voltage profiles can be associated with dynamic performance profiles. The method further can include predicting dynamic performance of the die under test according to the dynamic performance profile associated with a test static voltage profile that is correlated with the static voltage profile.

Abstract: An integrated circuit (IC) structure can include a first die and a second die. The second die can include a first base unit and a second base unit. Each of the first base unit and the second base unit is self-contained and no signals pass between the first base unit and the second base unit within the second die. The IC structure can include an interposer. The interposer includes a first plurality of inter-die wires coupling the first die to the first base unit, a second plurality of inter-die wires coupling the first die to the second base unit, and a third plurality of inter-die wires coupling the first base unit to the second base unit.

Abstract: An apparatus for interconnecting a first die and a second die of a multi-die device includes a master circuit block that interfaces with the first die of the multi-die device, a slave circuit block that interfaces with the second die of the multi-die device, a first memory in the slave circuit block, a second memory in the master circuit block, and a plurality of ?bumps between the first die and the second die, wherein the master circuit block and the slave circuit block are configured to identify one of the ?bumps as a faulty ?bump, and store a first value that corresponds with the identified faulty ?bump in the first memory.

Abstract: An apparatus for interconnecting a first die and a second die of a multi-die device includes a master circuit block that interfaces with the first die of the multi-die device, a slave circuit block that interfaces with the second die of the multi-die device, a first memory in the slave circuit block, a second memory in the master circuit block, and a plurality of ?bumps between the first die and the second die, wherein the master circuit block and the slave circuit block are configured to identify one of the ?bumps as a faulty ?bump, and store a first value that corresponds with the identified faulty ?bump in the first memory.

Abstract: A programmable logic integrated circuit has user-accessible nonvolatile memory for use by the programmable logic. In a specific embodiment, the programmable logic integrated circuit has a programmable logic array portion and a nonvolatile memory array portion. The nonvolatile memory array portion is segregated into a boot data part and a user data partition. The boot data partition holds data for configuring the programmable logic portion on power up, and the user data partition is for use by the programmable logic. A user can store and retrieve data from the user data partition. A built-in oscillator can be programmably connected from the nonvolatile memory portion to the PLD portion.

Abstract: A programmable logic device for transferring JTAG scan data to a target device is disclosed. The programmable logic device includes a JTAG logic that communicates with a JTAG scan chain and interprets user-defined instructions received from the JTAG scan chain to generate control signals used by a target device interface and the target device interface, which transmits output data to a target device and receives input data from the target device in response to the control signals.

Abstract: An input buffer is configurable for use as a standard buffer with a single switching threshold, selectable to be one of at least two different switching thresholds, or used as a Schmitt trigger circuit with hysteresis, which uses at least two switching thresholds from among the at least two different switching thresholds. The integrated circuit may be a programmable logic device (PLD) or field programmable gate array (FPGA), but in other embodiments, the integrated circuit may be other types of devices such a microprocessors, ASICs, or memories.

Abstract: A programmable logic device for transferring JTAG scan data to a target device is disclosed. The programmable logic device includes a JTAG logic that communicates with a JTAG scan chain and interprets user-defined instructions received from the JTAG scan chain to generate control signals used by a target device interface and the target device interface, which transmits output data to a target device and receives input data from the target device in response to the control signals.

Abstract: A programmable logic integrated circuit has user-accessible nonvolatile memory for use by the programmable logic. In a specific embodiment, the programmable logic integrated circuit has a programmable logic array portion and a nonvolatile memory array portion. The nonvolatile memory array portion is segregated into a boot data part and a user data partition. The boot data partition holds data for configuring the programmable logic portion on power up, and the user data partition is for use by the programmable logic. A user can store and retrieve data from the user data partition. A built-in oscillator can be programmably connected from the nonvolatile memory portion to the PLD portion.

Abstract: Volatility of a programmable logic device (PLD) or field programmable gate array (FPGA) is selectable to be volatile or nonvolatile. In the volatile mode, configuration or other data of the integrated circuit are lost once power is removed from the integrated circuit. In the nonvolatile mode, configuration or other data is retained even when power is removed from the integrated circuit. Upon power-up, in nonvolatile mode, the integrated circuit does not need external data. In an embodiment, the mode, whether volatile or nonvolatile, may be selected during manufacturing. In other embodiment, the mode may be selected by other means, such as by the user.

Abstract: An input buffer is configurable for use as a standard buffer with a single switching threshold, selectable to be one of at least two different switching thresholds, or used as a Schmitt trigger circuit with hysteresis, which uses at least two switching thresholds from among the at least two different switching thresholds. The integrated circuit may be a programmable logic device (PLD) or field programmable gate array (FPGA), but in other embodiments, the integrated circuit may be other types of devices such a microprocessors, ASICs, or memories.

Abstract: A programmable logic core (PLC) can be integrated into custom ICS such as ASICs and SOCs. An example PLC for integration into a custom IC includes a Multi Scale Array (MSA) that consists of an array of configurable ALUs, an Application Circuit Interface (ACI) that provides signal interface between the MSA and application circuitry, and a PLC Adapter that initiates and loads the PLC configuration data and interfaces.

Abstract: An improved programmable logic device includes a set of I/O cells, a set of logic blocks, and a routing pool that provides connections among the logic blocks and the I/O cells. At least one of the logic blocks includes a programmable logic array that generates product term output signals on product term output lines. A first product term summing circuit has input terminals, at least one of which is coupled to a product term output line. The first product term summing circuit generates an output signal at an output terminal in response to at least one product term output signal. Likewise, a second product term summing circuit has input terminals, at least one of which is coupled to a product term output line. The second product term summing circuit generates an output signal at an output terminal in response to at least one product term output signal.