Patents by Inventor Rahmi Hezar
Rahmi Hezar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8654867Abstract: A method for generating an amplified radio frequency (RF) signal is provided. In-phase (I) and quadrature (Q) signals are received and interleaved so as to generate a time-interleaved signal. Delayed time-interleaved signals are then generated from the time interleaved signal, and each of the delayed time-interleaved signals is amplified so as to generate a plurality of amplified signals. The amplified signals are then combined with a transformer, where the delayed time-interleaved signals are arranged to generate a filter response with the transformer.Type: GrantFiled: December 7, 2011Date of Patent: February 18, 2014Assignee: Texas Instruments IncorporatedInventors: Rahmi Hezar, Lei Ding, Joonhoi Hur, Baher S. Haroun
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Publication number: 20130241663Abstract: A method is provided. An input signal is received, and a noise-shaped signal is generated from the input signal. The noise-shaped signal is formed from a plurality of noise-shaping levels. A pulse stream is generated from the noise-shaped signal over a plurality of periods, where each period has a plurality of frames. The pulse stream also includes a plurality of pulse sets, where each pulse set is associated with at least one of the noise-shaping levels, and, for each pulse set having a total pulse width for its period that is less than its period and greater than zero, each pulse set includes at least one pulse in each frame for its period.Type: ApplicationFiled: March 15, 2012Publication date: September 19, 2013Applicant: Texas Instruments IncorporatedInventors: Lei Ding, Rahmi Hezar, Joonhoi Hur, Baher S. Haroun
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Publication number: 20130241758Abstract: A system for processing a signal includes a detector configured to detect a two-level stream of bits; a converter configured to generate a three-level control signal based on two adjacent values within the two-level stream of bits; and a switch configured to determine which of three different paths to couple a current source to based on a value of the three-level control signal. Thus, based on adjacent values of the output stream a three-level control signal is generated which controls coupling of the current source to one of three different paths. This type of three-level digital-to-analog converter can be, for example, part of the feedback loop of an analog-to-digital converter. Similar techniques can also be utilized in a multi-segment digital-to-analog converter in which each segment of the DAC is controlled by a 3-level control signal and the DAC is implement using PMOS devices.Type: ApplicationFiled: May 6, 2013Publication date: September 19, 2013Applicant: Texas Instruments IncorporatedInventors: Rahmi Hezar, Baher Haroun, Halil Kiper, Mounir Fares, Ajay Kumar
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Publication number: 20130234795Abstract: A method is provided. A first enable signal is asserted so as to enable a first driver, where the first driver has a first output and a first parasitic capacitance. A second enable signal is asserted so as to enable a second driver, where the second driver has a second output and a second parasitic capacitance. The first and second outputs are coupled together by a switching network when the second driver is enabled. Pulses from complementary first and second radio frequency (RF) signals are applied to the first driver, where there is a first set of free-fly intervals between consecutive pulses from the first and second RF signals, and pulses from complementary third and fourth RF signals are applied to the second driver, wherein there is a second set of free-fly interval between consecutive pulses from the third and fourth RF signals.Type: ApplicationFiled: March 9, 2012Publication date: September 12, 2013Applicant: Texas Instruments IncorporationInventors: Joonhoi Hur, Lei Ding, Rahmi Hezar, Baher S. Haroun
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Patent number: 8519791Abstract: A method is provided. A first enable signal is asserted so as to enable a first driver, where the first driver has a first output and a first parasitic capacitance. A second enable signal is asserted so as to enable a second driver, where the second driver has a second output and a second parasitic capacitance. The first and second outputs are coupled together by a switching network when the second driver is enabled. Pulses from complementary first and second radio frequency (RF) signals are applied to the first driver, where there is a first set of free-fly intervals between consecutive pulses from the first and second RF signals, and pulses from complementary third and fourth RF signals are applied to the second driver, wherein there is a second set of free-fly interval between consecutive pulses from the third and fourth RF signals.Type: GrantFiled: March 9, 2012Date of Patent: August 27, 2013Assignee: Texas Instruments IncorporatedInventors: Joonhoi Hur, Lei Ding, Rahmi Hezar, Baher S. Haroun
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Publication number: 20130210376Abstract: A radio frequency (RF) transmitter is provided. The RF transmitter includes first and second drivers that are configured to receive first and second sets of complementary RF signals. Restoration circuits are coupled to the first and second drivers, and a bridge circuit is coupled to the first and second restoration circuits. By having the restoration circuits and the bridge circuit, a common mode impedance and a differential impedance can be provided, where the common mode impedance is lower than the differential impedance.Type: ApplicationFiled: February 9, 2012Publication date: August 15, 2013Applicant: Texas Instruments IncorporatedInventors: Joonhoi Hur, Rahmi Hezar, Lei Ding, Baher S. Haroun
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Patent number: 8483856Abstract: A circuit includes a digital oscillator, a phase lock loop (PLL), a digital signal generator, a correction circuit and a digital-to-analog converter DAC (DAC). The digital oscillator can output a reference clock signal. The PLL can output a system clock signal based on the reference clock signal. The digital signal generator can output a digital signal based on the system clock signal. The correction circuit can output a pre-distorted signal based on the reference clock signal, the system clock signal and the digital signal. The DAC can output an analog signal based on the pre-distorted signal and the system clock signal.Type: GrantFiled: May 19, 2010Date of Patent: July 9, 2013Assignee: Texas Instruments IncorporatedInventors: Rahmi Hezar, Baher Haroun
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Patent number: 8471747Abstract: A method is provided. A noise shaped signal having a plurality of instants is generated with each instant being associated with at least one of a plurality of output levels. A next phase is selected for each instant, where each next phase is a circularly shifted phase based at least in part on a previous phase for the associated output level for its instant. A plurality of PWM signals is then generated using the phase for each instant, and an amplified signal is generated from the plurality of PWM signals.Type: GrantFiled: December 12, 2011Date of Patent: June 25, 2013Assignee: Texas Instruments IncorporatedInventors: Lei Ding, Rahmi Hezar, Joonhoi Hur, Baher S. Haroun
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Publication number: 20130156089Abstract: A method for transmitting radio frequency (RF) signals is provided. In-phase (I) and quadrature (Q) signals are received and filtered using sigma-delta modulation. I and Q pulse width modulation signals are generated from the filtered I and Q signals and interleaved so as to generate a time-interleaved signal. The time-interleaved signal is then amplified to generate the RF signals.Type: ApplicationFiled: December 15, 2011Publication date: June 20, 2013Applicant: Texas Instruments IncorporatedInventors: Rahmi Hezar, Lei Ding, Joonhoi Hur, Baher S. Haroun
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Publication number: 20130148760Abstract: A method for generating an amplified radio frequency (RF) signal is provided. In-phase (I) and quadrature (Q) signals are received and interleaved so as to generate a time-interleaved signal. Delayed time-interleaved signals are then generated from the time interleaved signal, and each of the delayed time-interleaved signals is amplified so as to generate a plurality of amplified signals. The amplified signals are then combined with a transformer, where the delayed time-interleaved signals are arranged to generate a filter response with the transformer.Type: ApplicationFiled: December 7, 2011Publication date: June 13, 2013Applicant: Texas Instruments IncorporatedInventors: Rahmi Hezar, Lei Ding, Joonhoi Hur, Baher Haroun
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Publication number: 20130147533Abstract: A method is provided. A noise shaped signal having a plurality of instants is generated with each instant being associated with at least one of a plurality of output levels. A next phase is selected for each instant, where each next phase is a circularly shifted phase based at least in part on a previous phase for the associated output level for its instant. A plurality of PWM signals is then generated using the phase for each instant, and an amplified signal is generated from the plurality of PWM signals.Type: ApplicationFiled: December 12, 2011Publication date: June 13, 2013Applicant: Texas Instruments IncorporatedInventors: Lei Ding, Rahmi Hezar, Joonhoi Hur, Baher S. Haroun
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Patent number: 8456341Abstract: A system for processing a signal includes a detector configured to detect a two-level stream of bits; a converter configured to generate a three-level control signal based on two adjacent values within the two-level stream of bits; and a switch configured to determine which of three different paths to couple a current source to based on a value of the three-level control signal. Thus, based on adjacent values of the output stream a three-level control signal is generated which controls coupling of the current source to one of three different paths. This type of three-level digital-to-analog converter can be, for example, part of the feedback loop of an analog-to-digital converter. Similar techniques can also be utilized in a multi-segment digital-to-analog converter in which each segment of the DAC is controlled by a 3-level control signal and the DAC is implement using PMOS devices.Type: GrantFiled: June 3, 2011Date of Patent: June 4, 2013Assignee: Texas Instruments IncorporatedInventors: Rahmi Hezar, Baher Haroun, Halil Kiper, Mounir Fares, Ajay Kumar
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Patent number: 8373504Abstract: A class D power amplifier (PA) is provided. The PA generally comprises a driver, output capacitor, a matching network, and a cancellation circuit. The driver has an input, an output, and a parasitic capacitance, and the input of the driver is configured to receive complementary first and second radio frequency (RF) signals, where there is a free-fly interval between consecutive pulses from the first and second RF signals. The output capacitor and cancellation circuit are each coupled to the output of the driver such that the cancellation circuit provides harmonic restoration at least during the free-fly interval, and the matching network is coupled to the output capacitor.Type: GrantFiled: May 12, 2011Date of Patent: February 12, 2013Assignee: Texas Instruments IncorporatedInventors: Baher Haroun, Joonhoi Hur, Lei Ding, Rahmi Hezar
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Publication number: 20120306678Abstract: A system for processing a signal includes a detector configured to detect a two-level stream of bits; a converter configured to generate a three-level control signal based on two adjacent values within the two-level stream of bits; and a switch configured to determine which of three different paths to couple a current source to based on a value of the three-level control signal. Thus, based on adjacent values of the output stream a three-level control signal is generated which controls coupling of the current source to one of three different paths. This type of three-level digital-to-analog converter can be, for example, part of the feedback loop of an analog-to-digital converter. Similar techniques can also be utilized in a multi-segment digital-to-analog converter in which each segment of the DAC is controlled by a 3-level control signal and the DAC is implement using PMOS devices.Type: ApplicationFiled: June 3, 2011Publication date: December 6, 2012Inventors: Rahmi Hezar, Baher Haroun, Halil Kiper, Mounir Fares, Ajay Kumar
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Publication number: 20120286868Abstract: A class D power amplifier (PA) is provided. The PA generally comprises a driver, output capacitor, a matching network, and a cancellation circuit. The driver has an input, an output, and a parasitic capacitance, and the input of the driver is configured to receive complementary first and second radio frequency (RF) signals, where there is a free-fly interval between consecutive pulses from the first and second RF signals. The output capacitor and cancellation circuit are each coupled to the output of the driver such that the cancellation circuit provides harmonic restoration at least during the free-fly interval, and the matching network is coupled to the output capacitor.Type: ApplicationFiled: May 12, 2011Publication date: November 15, 2012Applicant: Texas Instruments IncorporatedInventors: Baher Haroun, Joonhoi Hur, Lei Ding, Rahmi Hezar
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Patent number: 8144043Abstract: A signal converting system is described that has a multi-segment digital to analog converter coupled to one or more error shaping loops. Each error shaping loop includes a quantizer with a feedback loop configured to generate a control signal responsive to a stream of symbols and to an error signal. Each error shaping loop also includes an inter-symbol-interference (ISI) shaping loop coupled to receive the control signal and to produce an ISI portion of the error signal that is responsive to inter-symbol transition rate.Type: GrantFiled: April 28, 2010Date of Patent: March 27, 2012Assignee: Texas Instruments IncorporatedInventors: Lars Risbo, Rahmi Hezar, Burak Kelleci, Anker Bjoern-Josefsen
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Publication number: 20110285433Abstract: A circuit includes a digital oscillator, a phase lock loop (PLL), a digital signal generator, a correction circuit and a digital-to-analog converter DAC (DAC). The digital oscillator can output a reference clock signal. The PLL can output a system clock signal based on the reference clock signal. The digital signal generator can output a digital signal based on the system clock signal. The correction circuit can output a pre-distorted signal based on the reference clock signal, the system clock signal and the digital signal. The DAC can output an analog signal based on the pre-distorted signal and the system clock signal.Type: ApplicationFiled: May 19, 2010Publication date: November 24, 2011Inventors: Rahmi Hezar, Baher Haroun
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Publication number: 20110267210Abstract: A signal converting system is described that has a multi-segment digital to analog converter coupled to one or more error shaping loops. Each error shaping loop includes a quantizer with a feedback loop configured to generate a control signal responsive to a stream of symbols and to an error signal. Each error shaping loop also includes an inter-symbol-interference (ISI) shaping loop coupled to receive the control signal and to produce an ISI portion of the error signal that is responsive to inter-symbol transition rate.Type: ApplicationFiled: April 28, 2010Publication date: November 3, 2011Inventors: Lars Risbo, Rahmi Hezar, Burak Kelleci, Anker Bjoern-Josefsen
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Patent number: 7924191Abstract: A sigma delta analog to digital converter includes a clock operating at a conversion clock rate and first and second conversion paths. The first path includes a first sigma delta modulator configured to produce from an input analog signal a first bit stream at the clock rate, and a first digital filter configured to decimate the first bit stream. The second conversion path has a second sigma delta modulator configured to produce from the input analog signal a second bit stream separate from the first bit stream at the clock rate, and a second digital filter configured to decimate the second bit stream.Type: GrantFiled: June 30, 2009Date of Patent: April 12, 2011Assignee: Texas Instruments IncorporatedInventor: Rahmi Hezar
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Patent number: 7903015Abstract: An embodiment of the invention provides one or more cascade circuits that are cascaded together to form a cascaded circuit. The cascaded circuit reduces noise at an analog output of the cascaded circuit. Each of the cascade circuits contains a noise-shaping circuit, a PCM (Pulse Code Modulation)-to-PWM (Pulse Width Modulation) converter and a 1-bit P-tap AFIR (Analog Finite Impulse Response) filter DAC. Noise at the output of the cascaded circuit may be further reduced by increasing the number of cascade circuits.Type: GrantFiled: August 24, 2009Date of Patent: March 8, 2011Assignee: Texas Instruments IncorporatedInventors: Rahmi Hezar, Lars Risbo