Patents by Inventor Rahul Gulati

Rahul Gulati has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240359698
    Abstract: This disclosure provides systems, methods, and devices for vehicles with automated driving systems. In a first aspect, a method of isolation in an automated driving system includes detecting the error in a first domain of the automated driving system, isolating a second domain of the automated driving system from the first domain, maintaining operation of the second domain after isolating the second domain from the first domain, and bypassing, by the second domain, the first domain to transmit notifications to an external controller via a first communication interface. Other aspects and features are also claimed and described.
    Type: Application
    Filed: April 28, 2023
    Publication date: October 31, 2024
    Inventors: Amit Aneja, Rahul Gulati, Sriram Hariharan
  • Publication number: 20240321096
    Abstract: Systems and methodologies for determining validity of a location of a vehicle include obtaining a first location of the vehicle corresponding to a first time. A first RSU signal including an indication of a location of the first RSU is received at the vehicle from a first Roadside Unit (RSU). One or more location measurements are obtained of the vehicle relative thee first RSU based on one or more sensors of the vehicle. The first location of the vehicle is compared with the first RSU-based location of the vehicle.
    Type: Application
    Filed: March 23, 2023
    Publication date: September 26, 2024
    Inventors: Ali Reza ABBASPOUR, Rahul GULATI, Ahmed Kamel SADEK
  • Publication number: 20240323344
    Abstract: An image processing system includes an image sensor configured to generate a video frame, the video frame having a data portion and a test portion, an inline front end (IFE) having at least one processing module, a first memory, a functional software register, and a test software register, the IFE configured to receive the video frame, process the video frame and store the processed video frame to a second memory, a test pattern generator configured to generate test data that is provided to the IFE during the test portion of the video frame, a multiple input signature register (MISR) test function configured to compute a MISR signature from the test data, and a comparison function configured to compare a verified version of the test data to the computed MISR signature in the IFE to determine whether a system interrupt should be generated.
    Type: Application
    Filed: March 23, 2023
    Publication date: September 26, 2024
    Inventors: Abhijeet DEY, Rahul GULATI, Joby ABRAHAM, Vijayamanohar NAGARAJAN, Aakil Mahendra BAPNA
  • Publication number: 20240296702
    Abstract: Fail-safe and Fail-operational behavior can be achieved by providing two fully-redundant execution channels comprising at least first and second chiplet dies on a single SoC that are in communication with one another via a D2D interface. At least first and second instances of a first automotive safety integrity level (ASIL) domain circuit disposed on the at least first and second chiplet dies, respectively, perform at least a first ASIL domain process on one or more automotive sensor output signals to produce first and second output signals, respectively. A fault monitoring system monitors at least the first chiplet die for faults and assigns a first value to a selector signal if it detects a fault in the first chiplet die. A selector circuit outputs the second output signal from the system if the selector signal has the first value.
    Type: Application
    Filed: March 1, 2023
    Publication date: September 5, 2024
    Inventors: Amit ANEJA, Rahul GULATI, Sriram HARIHARAN
  • Publication number: 20240231982
    Abstract: Aspects of the present disclosure provide techniques and apparatus for safety monitoring of a vehicle control system. An example method of operating a vehicle includes detecting an error associated with a system-on-a-chip (SoC) having a main domain and a safety domain, wherein the main domain is coupled to a first bus for communicating with one or more electronic control units (ECUs) and wherein the safety domain is coupled to a second bus for communicating with the one or more ECUs; indicating the error to the one or more ECUs via at least one of the first bus, the second bus, or a power management integrated circuit (PMIC) in response to detecting the error, wherein the PMIC is configured to supply power to the main domain or the safety domain; and performing one or more actions in response to detecting the error.
    Type: Application
    Filed: October 18, 2023
    Publication date: July 11, 2024
    Inventors: Amit ANEJA, Vasant Kumar EASWARAN, Rahul GULATI
  • Publication number: 20240227825
    Abstract: Aspects of the present disclosure provide techniques and apparatus for testing a mixed safety system, such as system included in a vehicle. An example method of operating a vehicle includes operating an electronic control unit (ECU) in a first state; detecting one or more criteria being satisfied to perform a test associated with the ECU; and performing the test associated with the ECU in response to detecting the one or more criteria being satisfied, while the ECU is in a second state different from the first state.
    Type: Application
    Filed: January 10, 2023
    Publication date: July 11, 2024
    Inventors: Amit ANEJA, Rahul GULATI
  • Publication number: 20240134730
    Abstract: Aspects of the present disclosure provide techniques and apparatus for safety monitoring of a vehicle control system. An example method of operating a vehicle includes detecting an error associated with a system-on-a-chip (SoC) having a main domain and a safety domain, wherein the main domain is coupled to a first bus for communicating with one or more electronic control units (ECUs) and wherein the safety domain is coupled to a second bus for communicating with the one or more ECUs; indicating the error to the one or more ECUs via at least one of the first bus, the second bus, or a power management integrated circuit (PMIC) in response to detecting the error, wherein the PMIC is configured to supply power to the main domain or the safety domain; and performing one or more actions in response to detecting the error.
    Type: Application
    Filed: October 17, 2023
    Publication date: April 25, 2024
    Inventors: Amit ANEJA, Vasant Kumar EASWARAN, Rahul GULATI
  • Publication number: 20240067110
    Abstract: Techniques and apparatus for power supply monitoring in in-vehicle systems, such as advanced driver assistance systems (ADASs), in-vehicle infotainment (IVI) systems, and/or automated driving (AD) systems. One example method of power supply monitoring generally includes regulating power to a main domain of a system on a chip (SoC) using at least one main domain (MD) power management integrated circuit (PMIC); regulating power to a safety domain of the SoC using at least one safety domain (SD) PMIC; powering the at least one SD PMIC using a SD PMIC power supply rail; and monitoring the SD PMIC power supply rail using the at least one MD PMIC. For certain aspects, the method further includes powering the at least one MD PMIC using a MD PMIC power supply rail and monitoring the MD PMIC power supply rail using the at least one SD PMIC.
    Type: Application
    Filed: August 28, 2023
    Publication date: February 29, 2024
    Inventors: Amit ANEJA, Vasant Kumar EASWARAN, Rahul GULATI
  • Publication number: 20230297480
    Abstract: An integrated circuit (IC) chip can include a given core at a position in the IC chip that defines a given orientation, wherein the given core is designed to perform a particular function. The IC chip can include another core designed to perform the particular function. The other core can be flipped and rotated by 180 degrees relative to the given core such that the other core is asymmetrically oriented with respect to the given core. The IC chip can also include a compare unit configured to compare outputs of the given core and the other core to detect a fault in the IC chip.
    Type: Application
    Filed: May 25, 2023
    Publication date: September 21, 2023
    Inventors: JASBIR SINGH NAYYAR, SHASHANK SRINIVASA NUTHAKKI, RAHUL GULATI, ARUN SHRIMALI
  • Publication number: 20230258454
    Abstract: Information communication circuitry, including a first integrated circuit for coupling to a second integrated circuit in a package on package configuration. The first integrated circuit comprises processing circuitry for communicating information bits, and the information bits comprise data bits and error correction bits, where the error correction bits are for indicating whether data bits are received correctly. The second integrated circuit comprises a memory for receiving and storing at least some of the information bits. The information communication circuitry also includes interfacing circuitry for selectively communicating, along a number of conductors, between the package on package configuration. In a first instance, the interfacing circuitry selectively communicates only data bits along the number of conductors.
    Type: Application
    Filed: April 25, 2023
    Publication date: August 17, 2023
    Inventors: Rahul Gulati, Aishwarya Dubey, Nainala Vyagrheswarudu, Vasant Easwaran, Prashant Dinkar Karandikar, Mihir Mody
  • Patent number: 11698841
    Abstract: An integrated circuit (IC) chip can include a given core at a position in the IC chip that defines a given orientation, wherein the given core is designed to perform a particular function. The IC chip can include another core designed to perform the particular function. The other core can be flipped and rotated by 180 degrees relative to the given core such that the other core is asymmetrically oriented with respect to the given core. The IC chip can also include a compare unit configured to compare outputs of the given core and the other core to detect a fault in the IC chip.
    Type: Grant
    Filed: January 27, 2022
    Date of Patent: July 11, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jasbir Singh Nayyar, Shashank Srinivasa Nuthakki, Rahul Gulati, Arun Shrimali
  • Publication number: 20230203796
    Abstract: Various embodiments include components (e.g., a processor in a vehicle advanced driver assistance system) configured to identify subsystems that require testing in order to verify their compliance with a safety requirement. The components may determine whether verification of compliance requires that the subsystems be tested at PON, at POFF, during runtime or a combination thereof, dynamically determine the achievable parallelism for testing the identified subsystems, dynamically determine coverage level requirements for performing or executing built in self tests (BISTs) on each identified subsystem, and perform or execute the BISTs on the subsystems at the determined level of parallel and at the determined coverage level.
    Type: Application
    Filed: March 9, 2023
    Publication date: June 29, 2023
    Inventors: Kiran Kumar MALIPEDDI, Rahul GULATI
  • Patent number: 11662211
    Abstract: Information communication circuitry, including a first integrated circuit for coupling to a second integrated circuit in a package on package configuration. The first integrated circuit comprises processing circuitry for communicating information bits, and the information bits comprise data bits and error correction bits, where the error correction bits are for indicating whether data bits are received correctly. The second integrated circuit comprises a memory for receiving and storing at least some of the information bits. The information communication circuitry also includes interfacing circuitry for selectively communicating, along a number of conductors, between the package on package configuration. In a first instance, the interfacing circuitry selectively communicates only data bits along the number of conductors.
    Type: Grant
    Filed: August 3, 2020
    Date of Patent: May 30, 2023
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rahul Gulati, Aishwarya Dubey, Nainala Vyagrheswarudu, Vasant Easwaran, Prashant Dinkar Karandikar, Mihir Mody
  • Patent number: 11634895
    Abstract: Various embodiments include components (e.g., a processor in a vehicle advanced driver assistance system) configured to identify subsystems that require testing in order to verify their compliance with a safety requirement. The components may determine whether verification of compliance requires that the subsystems be tested at PON, at POFF, during runtime or a combination thereof, dynamically determine the achievable parallelism for testing the identified subsystems, dynamically determine coverage level requirements for performing or executing built in self tests (BISTs) on each identified subsystem, and perform or execute the BISTs on the subsystems at the determined level of parallel and at the determined coverage level.
    Type: Grant
    Filed: January 29, 2021
    Date of Patent: April 25, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Kiran Kumar Malipeddi, Rahul Gulati
  • Patent number: 11545114
    Abstract: The present disclosure relates to methods and apparatus for data processing, e.g., a display processing unit (DPU). The apparatus may receive data including a plurality of data bits, the data being associated with at least one data source. The apparatus may also determine whether at least a portion of the data corresponds to priority data, the priority data being within a region of interest (ROI). The apparatus may also detect an adjustment amount of the received data when at least a portion of the data corresponds to priority data, the data being displayed or stored based on the detected adjustment amount.
    Type: Grant
    Filed: November 6, 2020
    Date of Patent: January 3, 2023
    Assignee: QUALCOMM Incorporated
    Inventors: Paul Christopher John Wiercienski, John Chi Kit Wong, Rahul Gulati, Gary Arthur Ciambella, Sreekanth Modaikkal
  • Patent number: 11424621
    Abstract: In certain aspects, a device comprises a first processing unit; a first power distribution network coupled to the first processing unit; a first decoupling capacitor coupled to the first power distribution network; a second processing unit configured to be identical to the first processing unit; a second power distribution network coupled to the second processing unit; and a second decoupling capacitor coupled to the second power distribution network, wherein the second decoupling capacitor is configured to have different effect on the second power distribution network than the first decoupling capacitor on the first power distribution network.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: August 23, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Palkesh Jain, Rahul Gulati
  • Patent number: 11416049
    Abstract: Various embodiments may include methods and systems for monitoring characteristics of a system-on-a-chip. Various embodiments may include inputting, from a test data input connection, test data to a first scan chain section including a first group of logic gates located within a first region of the SoC. Various embodiments may include providing, from a first clock gate associated with the first region of the SoC, a clock signal to the first group of logic gates. Various embodiments may include measuring, using a first sensor, the characteristics at a second region of the SoC in response to providing the clock signal to the first group of logic gates. Embodiments may further include processing or analyzing measured characteristics to determine a testing result.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: August 16, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Palkesh Jain, Rahul Gulati
  • Publication number: 20220243437
    Abstract: Various embodiments include components (e.g., a processor in a vehicle advanced driver assistance system) configured to identify subsystems that require testing in order to verify their compliance with a safety requirement. The components may determine whether verification of compliance requires that the subsystems be tested at PON, at POFF, during runtime or a combination thereof, dynamically determine the achievable parallelism for testing the identified subsystems, dynamically determine coverage level requirements for performing or executing built in self tests (BISTs) on each identified subsystem, and perform or execute the BISTs on the subsystems at the determined level of parallel and at the determined coverage level.
    Type: Application
    Filed: January 29, 2021
    Publication date: August 4, 2022
    Inventors: Kiran Kumar MALIPEDDI, Rahul GULATI
  • Publication number: 20220147424
    Abstract: An integrated circuit (IC) chip can include a given core at a position in the IC chip that defines a given orientation, wherein the given core is designed to perform a particular function. The IC chip can include another core designed to perform the particular function. The other core can be flipped and rotated by 180 degrees relative to the given core such that the other core is asymmetrically oriented with respect to the given core. The IC chip can also include a compare unit configured to compare outputs of the given core and the other core to detect a fault in the IC chip.
    Type: Application
    Filed: January 27, 2022
    Publication date: May 12, 2022
    Inventors: JASBIR SINGH NAYYAR, SHASHANK SRINIVASA NUTHAKKI, RAHUL GULATI, ARUN SHRIMALI
  • Patent number: 11269742
    Abstract: An integrated circuit (IC) chip can include a given core at a position in the IC chip that defines a given orientation, wherein the given core is designed to perform a particular function. The IC chip can include another core designed to perform the particular function. The other core can be flipped and rotated by 180 degrees relative to the given core such that the other core is asymmetrically oriented with respect to the given core. The IC chip can also include a compare unit configured to compare outputs of the given core and the other core to detect a fault in the IC chip.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: March 8, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jasbir Singh Nayyar, Shashank Srinivasa Nuthakki, Rahul Gulati, Arun Shrimali