Patents by Inventor Rahul Gulati

Rahul Gulati has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11001143
    Abstract: Systems, methods, and devices of the various embodiments enable dynamic configuration of a number of display regions of interest (ROIs) associated with safety critical content presented on a display, such as a vehicle display. Various embodiments may enable verification of data integrity for ROIs on a display. Various embodiments may enable the selection of different sets of display ROIs from a plurality of independent sets of display ROIs each associated with its own set of stored integrity check values (ICVs). Various embodiments may enable stored ICVs to be used to verify the data integrity of ROIs on a display. Various embodiments may enable the set of display ROIs and the associated ICVs for each display ROI to be changed after a number of frames have been displayed.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: May 11, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Rahul Gulati, John Chi Kit Wong, Peter Koster, Reza Kakoee, Thomas Dannemann
  • Publication number: 20210064905
    Abstract: Certain aspects of the present disclosure generally relate to testing functionality of the display system. An example method generally includes selecting a first data integrity check value, associated with a region of interest (ROI) of an input frame, among a set of data integrity check values stored on a memory device, the data integrity check values are associated with an animation comprising a plurality of frames, and at least one of the frames of the animation corresponds to the input frame; processing, with a display processor, the input frame; calculating a second data integrity check value on the ROI of the input frame after the display processor processes the input frame; comparing, with a comparator, the data integrity check values; and generating, with the comparator, an interrupt if the comparison indicates that the values do not match.
    Type: Application
    Filed: August 29, 2019
    Publication date: March 4, 2021
    Inventors: Rahul GULATI, Robert HARDACKER, Sumant PARANJPE, Reza KAKOEE, John Chi Kit WONG, Sanjay GUPTA, Alex JONG
  • Patent number: 10901020
    Abstract: In one embodiment, a system including a duty-cycle-monitoring circuit is configured to receive a monitored signal having cycles that have a high portion and a low portion. The duty-cycle-monitoring circuit includes: a cascade of buffers including a first buffer, wherein the first buffer is configured to receive a first signal based on the monitored signal, a plurality of corresponding flip-flops. Each flip-flop is triggered by a second signal based on the monitored signal. The data input of each flip-flop is connected to an output of a corresponding buffer. The duty-cycle-monitoring circuit further includes a control circuit configured to determine, based on a state of the plurality of flip-flops, a measure of the duration of the high portion of a cycle of the monitored signal and determine, based on a state of the plurality of flip-flops, a measure of duration of the low portion of a cycle of the monitored signal.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: January 26, 2021
    Assignee: Qualcomm Incorporated
    Inventors: Palkesh Jain, Rahul Gulati, Edward Jacob Meisarosh
  • Patent number: 10848272
    Abstract: Systems and method for error detection in automobile tell-tales are provided. An initial cyclic redundancy check (CRC) for a tell-tale to be calculated and stored at a primary control system within the vehicle. When a fault or condition is detected which generates the tell-tale, the primary control system passes video information to a display embedded control unit (ECU) along with the initial CRC. A circuit in the display ECU performs its own CRC calculation and compares the initial CRC to the calculated CRC. If there is not a match, then a fault indication may be provided to the primary control system for action by the primary control system. Still further, back up or fail-operational options may be invoked so that the tell-tale is provided to the operator.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: November 24, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Robert Hardacker, Rahul Gulati, Alex Jong
  • Publication number: 20200363210
    Abstract: Information communication circuitry, including a first integrated circuit for coupling to a second integrated circuit in a package on package configuration. The first integrated circuit comprises processing circuitry for communicating information bits, and the information bits comprise data bits and error correction bits, where the error correction bits are for indicating whether data bits are received correctly. The second integrated circuit comprises a memory for receiving and storing at least some of the information bits. The information communication circuitry also includes interfacing circuitry for selectively communicating, along a number of conductors, between the package on package configuration. In a first instance, the interfacing circuitry selectively communicates only data bits along the number of conductors.
    Type: Application
    Filed: August 3, 2020
    Publication date: November 19, 2020
    Inventors: Rahul Gulati, Aishwarya Dubey, Nainala Vyagrheswarudu, Vasant Easwaran, Prashant Dinkar Karandikar, Mihir Mody
  • Patent number: 10767998
    Abstract: Information communication circuitry, including a first integrated circuit for coupling to a second integrated circuit in a package on package configuration. The first integrated circuit comprises processing circuitry for communicating information bits, and the information bits comprise data bits and error correction bits, where the error correction bits are for indicating whether data bits are received correctly. The second integrated circuit comprises a memory for receiving and storing at least some of the information bits. The information communication circuitry also includes interfacing circuitry for selectively communicating, along a number of conductors, between the package on package configuration. In a first instance, the interfacing circuitry selectively communicates only data bits along the number of conductors.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: September 8, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rahul Gulati, Aishwarya Dubey, Nainala Vyagrheswarudu, Vasant Easwaran, Prashant Dinkar Karandikar, Mihir Mody
  • Publication number: 20200233758
    Abstract: An integrated circuit (IC) chip can include a given core at a position in the IC chip that defines a given orientation, wherein the given core is designed to perform a particular function. The IC chip can include another core designed to perform the particular function. The other core can be flipped and rotated by 180 degrees relative to the given core such that the other core is asymmetrically oriented with respect to the given core. The IC chip can also include a compare unit configured to compare outputs of the given core and the other core to detect a fault in the IC chip.
    Type: Application
    Filed: April 2, 2020
    Publication date: July 23, 2020
    Inventors: JASBIR SINGH NAYYAR, SHASHANK SRINIVASA NUTHAKKI, RAHUL GULATI, ARUN SHRIMALI
  • Publication number: 20200210299
    Abstract: The disclosure describes techniques for a self-test of a graphics processing unit (GPU) independent of instructions from another processing device. The GPU may perform the self-test in response to a determination that the GPU enters an idle mode. The self-test may be based on information indicating a safety level, where the safety level indicates how many faults in circuits or memory blocks of the GPU need to be detected.
    Type: Application
    Filed: March 11, 2020
    Publication date: July 2, 2020
    Inventors: Rahul GULATI, Andrew Evan GRUBER, Brendon Lewis JOHNSON, Jay Chunsup YUN, Donghyun KIM, Alex Kwang Ho JONG, Anshuman SAXENA
  • Publication number: 20200198466
    Abstract: Systems, methods, and devices of the various embodiments enable dynamic configuration of a number of display regions of interest (ROIs) associated with safety critical content presented on a display, such as a vehicle display. Various embodiments may enable verification of data integrity for ROIs on a display. Various embodiments may enable the selection of different sets of display ROIs from a plurality of independent sets of display ROIs each associated with its own set of stored integrity check values (ICVs). Various embodiments may enable stored ICVs to be used to verify the data integrity of ROIs on a display. Various embodiments may enable the set of display ROIs and the associated ICVs for each display ROI to be changed after a number of frames have been displayed.
    Type: Application
    Filed: December 19, 2018
    Publication date: June 25, 2020
    Inventors: Rahul GULATI, John Chi Kit Wong, Peter Koster, Reza Kakoee, Thomas Dannemann
  • Patent number: 10649865
    Abstract: An integrated circuit (IC) chip can include a given core at a position in the IC chip that defines a given orientation, wherein the given core is designed to perform a particular function. The IC chip can include another core designed to perform the particular function. The other core can be flipped and rotated by 180 degrees relative to the given core such that the other core is asymmetrically oriented with respect to the given core. The IC chip can also include a compare unit configured to compare outputs of the given core and the other core to detect a fault in the IC chip.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: May 12, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jasbir Singh Nayyar, Shashank Srinivasa Nuthakki, Rahul Gulati, Arun Shrimali
  • Patent number: 10625752
    Abstract: A system and a method for error-correction code (“ECC”) error handling is described herein. In one aspect, the system and method may operate an ECC function on raw data. The ECC function may include generating ECC syndrome data by an ECC syndrome data generating module. The ECC syndrome data may be derived from the raw data. The system and a method may further inject a fault based on the ECC syndrome data or the raw data. The system and a method may further determine whether the ECC error detected by the ECC checker corresponds to a malfunction of the ECC function or the fault injected based on the ECC syndrome data or the raw data.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: April 21, 2020
    Assignee: Qualcomm Incorporated
    Inventors: Mohammad Reza Kakoee, Rahul Gulati, Eric Mahurin, Suresh Kumar Venkumahanti, Dexter Chun
  • Patent number: 10628274
    Abstract: The disclosure describes techniques for a self-test of a graphics processing unit (GPU) independent of instructions from another processing device. The GPU may perform the self-test in response to a determination that the GPU enters an idle mode. The self-test may be based on information indicating a safety level, where the safety level indicates how many faults in circuits or memory blocks of the GPU need to be detected.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: April 21, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Rahul Gulati, Andrew Evan Gruber, Brendon Lewis Johnson, Jay Chunsup Yun, Donghyun Kim, Alex Kwang Ho Jong, Anshuman Saxena
  • Publication number: 20200072885
    Abstract: In one embodiment, a system including a duty-cycle-monitoring circuit is configured to receive a monitored signal having cycles that have a high portion and a low portion. The duty-cycle-monitoring circuit includes: a cascade of buffers including a first buffer, wherein the first buffer is configured to receive a first signal based on the monitored signal, a plurality of corresponding flip-flops. Each flip-flop is triggered by a second signal based on the monitored signal. The data input of each flip-flop is connected to an output of a corresponding buffer. The duty-cycle-monitoring circuit further includes a control circuit configured to determine, based on a state of the plurality of flip-flops, a measure of the duration of the high portion of a cycle of the monitored signal and determine, based on a state of the plurality of flip-flops, a measure of duration of the low portion of a cycle of the monitored signal.
    Type: Application
    Filed: August 30, 2018
    Publication date: March 5, 2020
    Inventors: Palkesh JAIN, Rahul GULATI, Edward Jacob MEISAROSH
  • Publication number: 20200019477
    Abstract: In one embodiment, a system has an integrated circuit (IC) device, the IC device includes a first processing unit having a first functional block that has a diversifiable sub-circuit and a result output, a second processing unit having a second functional block substantially identical to the first functional block that includes a corresponding diversifiable sub-circuit and a corresponding result output. The IC device includes a comparator adapted to compare the result output of the first functional block to the result output of the second functional block. The diversifiable sub-circuit of the first functional block operates using a first set of operating parameters. The diversifiable sub-circuit of the second functional block operates using a second set of operating parameters different from the first set of operating parameters.
    Type: Application
    Filed: July 10, 2018
    Publication date: January 16, 2020
    Inventors: Palkesh JAIN, Rahul GULATI
  • Patent number: 10521321
    Abstract: A graphics processing unit (GPU) of a GPU subsystem of a computing device operates in a first rendering mode to process graphics data to produce a first image. The GPU operates in a second rendering mode to process the graphics data to produce a second image. The computing device detects whether a fault has occurred in the GPU subsystem based at least in part on comparing the first image with the second image.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: December 31, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Alex Kwang Ho Jong, Jay Chunsup Yun, Donghyun Kim, Rahul Gulati, Brendon Lewis Johnson, Andrew Evan Gruber
  • Patent number: 10514401
    Abstract: In certain aspects of the disclosure, a frequency monitor includes a counter configured to receive a monitored clock signal, to count a number of periods of the monitored clock signal over a predetermined time duration, and to output a count value corresponding to the number of periods of the monitored clock signal. The frequency monitor also includes a comparator configured to receive the count value from the counter, to receive an expected count value, to compare the count value from the counter with the expected count value, and to output a pass status signal or a fail status signal based on the comparison.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: December 24, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Bipin Duggal, Rahul Gulati, Sina Dena
  • Patent number: 10482289
    Abstract: A computing device includes a hardware resource, a component to send a transaction signal including a target address of the hardware resource, a security data associated with an initiator of the transaction signal, and a safety data associated with the initiator, and an access control unit coupled to the component and the hardware resource, the access control unit to receive the transaction signal, determine whether security access is granted based on the transaction signal, determine whether safety access is granted based on the transaction signal, and allow access to the hardware resource based on both the security access and the safety access being granted.
    Type: Grant
    Filed: August 24, 2017
    Date of Patent: November 19, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: David Barr, Dafna Shaool, Rahul Gulati, Pranjal Bhuyan
  • Patent number: 10481202
    Abstract: A self-test controller includes a memory configured to store a test patterns, configuration registers, and a memory data component. The test patterns are encoded in the memory using various techniques in order to save storage space. By using the configuration parameters, the memory data component is configured to decode the test patterns and perform multiple built-in self-test on a multitude of test cores. The described techniques allow for built-in self-test to be performed dynamically while utilizing less space in the memory.
    Type: Grant
    Filed: December 7, 2017
    Date of Patent: November 19, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Arvind Jain, Nishi Bhushan Singh, Rahul Gulati, Pranjal Bhuyan, Rakesh Kumar Kinger, Roberto Averbuj
  • Patent number: 10467723
    Abstract: A graphics processing unit (GPU) of a GPU subsystem of a computing device processes graphics data to produce a plurality of portions of a first image, and to produce a plurality of portions of a second image. The GPU generates a plurality of data integrity check values associated with the plurality of portions of the first image, and a plurality of data integrity check values associated with the plurality of portions of the second image. The GPU determines whether each of the plurality of portions of the second image matches a corresponding portion of the first image. The GPU determines, prior to producing every portion of the second image, whether an operational fault has occurred in the GPU subsystem based at least in part the determination of whether each of the plurality of portions of the second image matches a corresponding portion of the first image.
    Type: Grant
    Filed: December 21, 2017
    Date of Patent: November 5, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Brendon Lewis Johnson, Andrew Evan Gruber, Jay Chunsup Yun, Rahul Gulati, Donghyun Kim, Alex Kwang Ho Jong
  • Patent number: 10467774
    Abstract: Techniques of this disclosure may include processing data using one or more processors to produce a first image, including storing intermediate first results of processing the data in at least one internal memory of the one or more processors according to a first memory access pattern, processing the data using the one or more processors to produce a second image, including storing intermediate second results of processing the data in the at least one internal memory of the one or more processors according to a second memory access pattern, wherein the second memory access pattern is different than the first memory access pattern, comparing the first image to the second image, and generating an interrupt if the comparison indicates that the first image is different than the second image.
    Type: Grant
    Filed: November 6, 2017
    Date of Patent: November 5, 2019
    Assignee: QUALCOMM Incorporated
    Inventors: Andrew Evan Gruber, Rahul Gulati, Brendon Lewis Johnson, Jay Chunsup Yun, Alex Kwang Ho Jong, Donghyun Kim