Patents by Inventor Rahul Gulati

Rahul Gulati has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11424621
    Abstract: In certain aspects, a device comprises a first processing unit; a first power distribution network coupled to the first processing unit; a first decoupling capacitor coupled to the first power distribution network; a second processing unit configured to be identical to the first processing unit; a second power distribution network coupled to the second processing unit; and a second decoupling capacitor coupled to the second power distribution network, wherein the second decoupling capacitor is configured to have different effect on the second power distribution network than the first decoupling capacitor on the first power distribution network.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: August 23, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Palkesh Jain, Rahul Gulati
  • Patent number: 11416049
    Abstract: Various embodiments may include methods and systems for monitoring characteristics of a system-on-a-chip. Various embodiments may include inputting, from a test data input connection, test data to a first scan chain section including a first group of logic gates located within a first region of the SoC. Various embodiments may include providing, from a first clock gate associated with the first region of the SoC, a clock signal to the first group of logic gates. Various embodiments may include measuring, using a first sensor, the characteristics at a second region of the SoC in response to providing the clock signal to the first group of logic gates. Embodiments may further include processing or analyzing measured characteristics to determine a testing result.
    Type: Grant
    Filed: March 23, 2020
    Date of Patent: August 16, 2022
    Assignee: QUALCOMM Incorporated
    Inventors: Palkesh Jain, Rahul Gulati
  • Publication number: 20220243437
    Abstract: Various embodiments include components (e.g., a processor in a vehicle advanced driver assistance system) configured to identify subsystems that require testing in order to verify their compliance with a safety requirement. The components may determine whether verification of compliance requires that the subsystems be tested at PON, at POFF, during runtime or a combination thereof, dynamically determine the achievable parallelism for testing the identified subsystems, dynamically determine coverage level requirements for performing or executing built in self tests (BISTs) on each identified subsystem, and perform or execute the BISTs on the subsystems at the determined level of parallel and at the determined coverage level.
    Type: Application
    Filed: January 29, 2021
    Publication date: August 4, 2022
    Inventors: Kiran Kumar MALIPEDDI, Rahul GULATI
  • Publication number: 20220147424
    Abstract: An integrated circuit (IC) chip can include a given core at a position in the IC chip that defines a given orientation, wherein the given core is designed to perform a particular function. The IC chip can include another core designed to perform the particular function. The other core can be flipped and rotated by 180 degrees relative to the given core such that the other core is asymmetrically oriented with respect to the given core. The IC chip can also include a compare unit configured to compare outputs of the given core and the other core to detect a fault in the IC chip.
    Type: Application
    Filed: January 27, 2022
    Publication date: May 12, 2022
    Inventors: JASBIR SINGH NAYYAR, SHASHANK SRINIVASA NUTHAKKI, RAHUL GULATI, ARUN SHRIMALI
  • Patent number: 11269742
    Abstract: An integrated circuit (IC) chip can include a given core at a position in the IC chip that defines a given orientation, wherein the given core is designed to perform a particular function. The IC chip can include another core designed to perform the particular function. The other core can be flipped and rotated by 180 degrees relative to the given core such that the other core is asymmetrically oriented with respect to the given core. The IC chip can also include a compare unit configured to compare outputs of the given core and the other core to detect a fault in the IC chip.
    Type: Grant
    Filed: April 2, 2020
    Date of Patent: March 8, 2022
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jasbir Singh Nayyar, Shashank Srinivasa Nuthakki, Rahul Gulati, Arun Shrimali
  • Publication number: 20220020340
    Abstract: The present disclosure relates to methods and apparatus for data processing, e.g., a display processing unit (DPU). The apparatus may receive data including a plurality of data bits, the data being associated with at least one data source. The apparatus may also determine whether at least a portion of the data corresponds to priority data, the priority data being within a region of interest (ROI). The apparatus may also detect an adjustment amount of the received data when at least a portion of the data corresponds to priority data, the data being displayed or stored based on the detected adjustment amount.
    Type: Application
    Filed: November 6, 2020
    Publication date: January 20, 2022
    Inventors: Paul Christopher John WIERCIENSKI, John Chi Kit WONG, Rahul GULATI, Gary Arthur CIAMBELLA, Sreekanth MODAIKKAL
  • Patent number: 11194683
    Abstract: The disclosure describes techniques for a self-test of a graphics processing unit (GPU) independent of instructions from another processing device. The GPU may perform the self-test in response to a determination that the GPU enters an idle mode. The self-test may be based on information indicating a safety level, where the safety level indicates how many faults in circuits or memory blocks of the GPU need to be detected.
    Type: Grant
    Filed: March 11, 2020
    Date of Patent: December 7, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Rahul Gulati, Andrew Evan Gruber, Brendon Lewis Johnson, Jay Chunsup Yun, Donghyun Kim, Alex Kwang Ho Jong, Anshuman Saxena
  • Publication number: 20210294398
    Abstract: Various embodiments may include methods and systems for monitoring characteristics of a system-on-a-chip. Various embodiments may include inputting, from a test data input connection, test data to a first scan chain section including a first group of logic gates located within a first region of the SoC. Various embodiments may include providing, from a first clock gate associated with the first region of the SoC, a clock signal to the first group of logic gates. Various embodiments may include measuring, using a first sensor, the characteristics at a second region of the SoC in response to providing the clock signal to the first group of logic gates. Embodiments may further include processing or analyzing measured characteristics to determine a testing result.
    Type: Application
    Filed: March 23, 2020
    Publication date: September 23, 2021
    Inventors: Palkesh JAIN, Rahul GULATI
  • Publication number: 20210234376
    Abstract: In certain aspects, a device comprises a first processing unit; a first power distribution network coupled to the first processing unit; a first decoupling capacitor coupled to the first power distribution network; a second processing unit configured to be identical to the first processing unit; a second power distribution network coupled to the second processing unit; and a second decoupling capacitor coupled to the second power distribution network, wherein the second decoupling capacitor is configured to have different effect on the second power distribution network than the first decoupling capacitor on the first power distribution network.
    Type: Application
    Filed: January 28, 2020
    Publication date: July 29, 2021
    Inventors: Palkesh JAIN, Rahul GULATI
  • Patent number: 11001143
    Abstract: Systems, methods, and devices of the various embodiments enable dynamic configuration of a number of display regions of interest (ROIs) associated with safety critical content presented on a display, such as a vehicle display. Various embodiments may enable verification of data integrity for ROIs on a display. Various embodiments may enable the selection of different sets of display ROIs from a plurality of independent sets of display ROIs each associated with its own set of stored integrity check values (ICVs). Various embodiments may enable stored ICVs to be used to verify the data integrity of ROIs on a display. Various embodiments may enable the set of display ROIs and the associated ICVs for each display ROI to be changed after a number of frames have been displayed.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: May 11, 2021
    Assignee: QUALCOMM Incorporated
    Inventors: Rahul Gulati, John Chi Kit Wong, Peter Koster, Reza Kakoee, Thomas Dannemann
  • Publication number: 20210064905
    Abstract: Certain aspects of the present disclosure generally relate to testing functionality of the display system. An example method generally includes selecting a first data integrity check value, associated with a region of interest (ROI) of an input frame, among a set of data integrity check values stored on a memory device, the data integrity check values are associated with an animation comprising a plurality of frames, and at least one of the frames of the animation corresponds to the input frame; processing, with a display processor, the input frame; calculating a second data integrity check value on the ROI of the input frame after the display processor processes the input frame; comparing, with a comparator, the data integrity check values; and generating, with the comparator, an interrupt if the comparison indicates that the values do not match.
    Type: Application
    Filed: August 29, 2019
    Publication date: March 4, 2021
    Inventors: Rahul GULATI, Robert HARDACKER, Sumant PARANJPE, Reza KAKOEE, John Chi Kit WONG, Sanjay GUPTA, Alex JONG
  • Patent number: 10901020
    Abstract: In one embodiment, a system including a duty-cycle-monitoring circuit is configured to receive a monitored signal having cycles that have a high portion and a low portion. The duty-cycle-monitoring circuit includes: a cascade of buffers including a first buffer, wherein the first buffer is configured to receive a first signal based on the monitored signal, a plurality of corresponding flip-flops. Each flip-flop is triggered by a second signal based on the monitored signal. The data input of each flip-flop is connected to an output of a corresponding buffer. The duty-cycle-monitoring circuit further includes a control circuit configured to determine, based on a state of the plurality of flip-flops, a measure of the duration of the high portion of a cycle of the monitored signal and determine, based on a state of the plurality of flip-flops, a measure of duration of the low portion of a cycle of the monitored signal.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: January 26, 2021
    Assignee: Qualcomm Incorporated
    Inventors: Palkesh Jain, Rahul Gulati, Edward Jacob Meisarosh
  • Patent number: 10848272
    Abstract: Systems and method for error detection in automobile tell-tales are provided. An initial cyclic redundancy check (CRC) for a tell-tale to be calculated and stored at a primary control system within the vehicle. When a fault or condition is detected which generates the tell-tale, the primary control system passes video information to a display embedded control unit (ECU) along with the initial CRC. A circuit in the display ECU performs its own CRC calculation and compares the initial CRC to the calculated CRC. If there is not a match, then a fault indication may be provided to the primary control system for action by the primary control system. Still further, back up or fail-operational options may be invoked so that the tell-tale is provided to the operator.
    Type: Grant
    Filed: December 11, 2018
    Date of Patent: November 24, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Robert Hardacker, Rahul Gulati, Alex Jong
  • Publication number: 20200363210
    Abstract: Information communication circuitry, including a first integrated circuit for coupling to a second integrated circuit in a package on package configuration. The first integrated circuit comprises processing circuitry for communicating information bits, and the information bits comprise data bits and error correction bits, where the error correction bits are for indicating whether data bits are received correctly. The second integrated circuit comprises a memory for receiving and storing at least some of the information bits. The information communication circuitry also includes interfacing circuitry for selectively communicating, along a number of conductors, between the package on package configuration. In a first instance, the interfacing circuitry selectively communicates only data bits along the number of conductors.
    Type: Application
    Filed: August 3, 2020
    Publication date: November 19, 2020
    Inventors: Rahul Gulati, Aishwarya Dubey, Nainala Vyagrheswarudu, Vasant Easwaran, Prashant Dinkar Karandikar, Mihir Mody
  • Patent number: 10767998
    Abstract: Information communication circuitry, including a first integrated circuit for coupling to a second integrated circuit in a package on package configuration. The first integrated circuit comprises processing circuitry for communicating information bits, and the information bits comprise data bits and error correction bits, where the error correction bits are for indicating whether data bits are received correctly. The second integrated circuit comprises a memory for receiving and storing at least some of the information bits. The information communication circuitry also includes interfacing circuitry for selectively communicating, along a number of conductors, between the package on package configuration. In a first instance, the interfacing circuitry selectively communicates only data bits along the number of conductors.
    Type: Grant
    Filed: August 28, 2018
    Date of Patent: September 8, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Rahul Gulati, Aishwarya Dubey, Nainala Vyagrheswarudu, Vasant Easwaran, Prashant Dinkar Karandikar, Mihir Mody
  • Publication number: 20200233758
    Abstract: An integrated circuit (IC) chip can include a given core at a position in the IC chip that defines a given orientation, wherein the given core is designed to perform a particular function. The IC chip can include another core designed to perform the particular function. The other core can be flipped and rotated by 180 degrees relative to the given core such that the other core is asymmetrically oriented with respect to the given core. The IC chip can also include a compare unit configured to compare outputs of the given core and the other core to detect a fault in the IC chip.
    Type: Application
    Filed: April 2, 2020
    Publication date: July 23, 2020
    Inventors: JASBIR SINGH NAYYAR, SHASHANK SRINIVASA NUTHAKKI, RAHUL GULATI, ARUN SHRIMALI
  • Publication number: 20200210299
    Abstract: The disclosure describes techniques for a self-test of a graphics processing unit (GPU) independent of instructions from another processing device. The GPU may perform the self-test in response to a determination that the GPU enters an idle mode. The self-test may be based on information indicating a safety level, where the safety level indicates how many faults in circuits or memory blocks of the GPU need to be detected.
    Type: Application
    Filed: March 11, 2020
    Publication date: July 2, 2020
    Inventors: Rahul GULATI, Andrew Evan GRUBER, Brendon Lewis JOHNSON, Jay Chunsup YUN, Donghyun KIM, Alex Kwang Ho JONG, Anshuman SAXENA
  • Publication number: 20200198466
    Abstract: Systems, methods, and devices of the various embodiments enable dynamic configuration of a number of display regions of interest (ROIs) associated with safety critical content presented on a display, such as a vehicle display. Various embodiments may enable verification of data integrity for ROIs on a display. Various embodiments may enable the selection of different sets of display ROIs from a plurality of independent sets of display ROIs each associated with its own set of stored integrity check values (ICVs). Various embodiments may enable stored ICVs to be used to verify the data integrity of ROIs on a display. Various embodiments may enable the set of display ROIs and the associated ICVs for each display ROI to be changed after a number of frames have been displayed.
    Type: Application
    Filed: December 19, 2018
    Publication date: June 25, 2020
    Inventors: Rahul GULATI, John Chi Kit Wong, Peter Koster, Reza Kakoee, Thomas Dannemann
  • Patent number: 10649865
    Abstract: An integrated circuit (IC) chip can include a given core at a position in the IC chip that defines a given orientation, wherein the given core is designed to perform a particular function. The IC chip can include another core designed to perform the particular function. The other core can be flipped and rotated by 180 degrees relative to the given core such that the other core is asymmetrically oriented with respect to the given core. The IC chip can also include a compare unit configured to compare outputs of the given core and the other core to detect a fault in the IC chip.
    Type: Grant
    Filed: May 29, 2018
    Date of Patent: May 12, 2020
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jasbir Singh Nayyar, Shashank Srinivasa Nuthakki, Rahul Gulati, Arun Shrimali
  • Patent number: 10628274
    Abstract: The disclosure describes techniques for a self-test of a graphics processing unit (GPU) independent of instructions from another processing device. The GPU may perform the self-test in response to a determination that the GPU enters an idle mode. The self-test may be based on information indicating a safety level, where the safety level indicates how many faults in circuits or memory blocks of the GPU need to be detected.
    Type: Grant
    Filed: December 5, 2017
    Date of Patent: April 21, 2020
    Assignee: QUALCOMM Incorporated
    Inventors: Rahul Gulati, Andrew Evan Gruber, Brendon Lewis Johnson, Jay Chunsup Yun, Donghyun Kim, Alex Kwang Ho Jong, Anshuman Saxena