Patents by Inventor Rahul Jain

Rahul Jain has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11978106
    Abstract: Methods and systems for generating a plurality of matching items that match a reference item are disclosed. The method includes first determining reference attribute data for the reference item, where the reference attribute data is multimodal. Next, selecting a deep learning multimodal matching model from a plurality of candidate multimodal matching models. The selected deep learning multimodal matching model has a first deep learning neural network (DLNN) for processing data having a first data mode and a second DLNN analyzer for processing data having a second data mode. Then, matching a potential matching item to the reference item using the selected deep learning multimodal matching model to generate a match score, where the match score is computed based on the reference attribute data for the reference item and attribute data for the potential matching item. Finally, adding the potential matching item to the plurality of matching items based on the match score.
    Type: Grant
    Filed: March 15, 2021
    Date of Patent: May 7, 2024
    Assignee: Price Technologies Inc.
    Inventors: Rahul Jain, Steven Douglas Moffitt
  • Patent number: 11972224
    Abstract: Disclosed herein are various embodiments for training and enriching a natural language processing system. An embodiment operates by determining that a first prediction from a first machine model has been generated based on a dataset comprising a plurality of attributes. A technical map identifying a first subset of attributes of the plurality of attributes used to generate the first prediction by the first machine model is generated. Natural language translations corresponding to at least a portion of the first subset of attributes used to generate the first prediction by the first machine model are identified. A natural language map of the first subset of attributes is generated based on the natural language translations. The natural language map is provided with the first prediction.
    Type: Grant
    Filed: July 1, 2021
    Date of Patent: April 30, 2024
    Assignee: SAP SE
    Inventors: Vishal Mour, Sreya Dey, Shipra Jain, Rahul Lodhe
  • Publication number: 20240135831
    Abstract: A learning system is disclosed that leverages intention-driven causality to enhance skill learning. The learning system enables an author to easily develop mixed reality (MR) tutorial content for performing a task that advantageously captures causal relationships between steps and, thus, enables such causality to be conveyed to the novice user when learning how to perform the task. To this end, the learning system leverages a novel hierarchical representation of causality and intention alongside a systematic workflow suitable for designing skill learning content. By preserving and presenting causal information to the novice user, the user can better understand not only the steps required to perform a task, but also why each step is performed.
    Type: Application
    Filed: October 22, 2023
    Publication date: April 25, 2024
    Inventors: Karthik Ramani, Jingyu Shi, Rahul Jain
  • Patent number: 11968236
    Abstract: Technologies for providing event-level data privacy for streaming post analytics data include, in some embodiments, receiving a data stream that includes instances of count data collected over a time interval, computing a true count breakdown that includes a set of sub-counts of non-public user interface interactions on the post, creating a noisy count breakdown by applying at least one differential privacy mechanism to the set of sub-counts, and streaming the noisy count breakdown instead of the true count breakdown to a computing device. At least one of the sub-counts is a count that is associated with a particular value of an attribute that has different possible values. The attribute is associated with the non-public user interface interactions on the post.
    Type: Grant
    Filed: March 30, 2022
    Date of Patent: April 23, 2024
    Assignee: Microsoft Technology Licensing, LLC
    Inventors: Ryan M. Rogers, Subbu Subramaniam, Mark B. Cesar, Adrian Rivera Cardoso, Yu Chen, Jefferson Lai, Vinyas Maddi, Lin Xu, Gavin Castro Uathavikul, Neha Jain, Shraddha Sahay, Parvez Ahammad, Rahul Tandra
  • Publication number: 20240100303
    Abstract: A catheter system which provides adjustability of the length of the guidewire extending distally from the distal tip of the catheter and/or allows the guidewire to be secured relative to the catheter hub to allow the guidewire and the catheter to be steered simultaneously. The catheter system may include a catheter having an elongate shaft defining a catheter lumen, a hub assembly coupled to the proximal end of the elongate shaft and including a hub assembly lumen, a torque assembly releasably coupled to the hub assembly and including a torque assembly lumen, and a guidewire co-axially disposed within the catheter lumen, hub assembly lumen, and torque assembly lumen. In a first configuration the torque assembly may be configured to simultaneously torque the elongate shaft and the guidewire and in a second configuration the torque assembly may be configured to torque the guidewire independent of the elongate shaft.
    Type: Application
    Filed: September 26, 2023
    Publication date: March 28, 2024
    Applicant: Boston Scientific Medical Device Limited
    Inventors: Prateek Gupta, Jahnavi Konduru, Ishank Jain, Anshul Chabra, Rahul Jain
  • Patent number: 11934700
    Abstract: Aspects of a storage device are provided that handle pairing and atomic processing of fused commands received from submission queues based on data structures such as a linked lists which the controller respectively associates with each submission queue. A memory of the storage device includes a plurality of data structures each associated with a different submission queue. A controller of the storage device receives a first command for a fused operation from a submission queue, stores the first command in a data structure, receives a second command for the fused operation from the submission queue, determines whether the second command corresponds to the fused operation, stores the second command in the data structure in response to the determination, and performs the fused operation in response to storing the second command. As a result, fused command handling may be achieved with minimal impact to queue arbitration logic and command latency.
    Type: Grant
    Filed: April 13, 2022
    Date of Patent: March 19, 2024
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Rahul Jain, Arvind Kumar V M
  • Patent number: 11935805
    Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: April 12, 2023
    Date of Patent: March 19, 2024
    Assignee: Intel Corporation
    Inventors: Rahul Jain, Kyu Oh Lee, Siddharth K. Alur, Wei-Lun K. Jen, Vipul V. Mehta, Ashish Dhall, Sri Chaitra J. Chavali, Rahul N. Manepalli, Amruthavalli P. Alur, Sai Vadlamani
  • Publication number: 20240063173
    Abstract: Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. The die interconnect substrate further comprises a first interface structure for attaching a semiconductor die to the substrate structure, wherein the first interface structure is connected to the first bridge die pad. The die interconnect substrate further comprises a second interface structure for attaching a semiconductor die to the substrate structure, wherein the second interface structure is connected to the substrate interconnect. A surface of the first interface structure and a surface of the second interface structure are at the same height.
    Type: Application
    Filed: October 30, 2023
    Publication date: February 22, 2024
    Inventors: Rahul JAIN, Ji Yong PARK, Kyu Oh LEE
  • Patent number: 11901115
    Abstract: Apparatuses, systems and methods associated with a substrate assembly with an encapsulated magnetic feature for an inductor are disclosed herein. In embodiments, a substrate assembly may include a base substrate, a magnetic feature encapsulated within the base substrate, and a coil, wherein a portion of the coil extends through the magnetic feature. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: July 26, 2022
    Date of Patent: February 13, 2024
    Assignee: Intel Corporation
    Inventors: Kyu-Oh Lee, Rahul Jain, Sai Vadlamani, Cheng Xu, Ji Yong Park, Junnan Zhao, Seo Young Kim
  • Patent number: 11881463
    Abstract: A coreless semiconductor package comprises a plurality of horizontal layers of dielectric material. A magnetic inductor is situated at least partly in a first group of the plurality of layers. A plated laser stop is formed to protect the magnetic inductor against subsequent acidic processes. An EMIB is situated above the magnetic inductor within a second group of the plurality of layers. Vias and interconnections are configured within the horizontal layers to connect a die of the EMIB to other circuitry. A first level interconnect is formed on the top side of the package to connect to the interconnections. BGA pockets and BGA pads are formed on the bottom side of the package. In a second embodiment a polymer film is used as additional protection against subsequent acidic processes. The magnetic inductor comprises a plurality of copper traces encapsulated in magnetic material.
    Type: Grant
    Filed: November 11, 2021
    Date of Patent: January 23, 2024
    Assignee: Intel Corporation
    Inventors: Andrew J. Brown, Rahul Jain, Prithwish Chatterjee, Lauren A. Link, Sai Vadlamani
  • Patent number: 11848800
    Abstract: A system and method for connecting virtual computer networks in a public cloud computing environment using a transit virtual computer network uses a cloud gateway device in the transit virtual computer network that includes a first-tier logical router and a plurality of second-tier logical routers connected to the virtual computer networks. A source Internet Protocol (IP) address of outgoing data packets from a particular virtual computer network is translated at a particular second-tier logical router of the cloud gateway device from an IP address of the particular virtual computer network to an internal IP address from a particular pool of IP addresses. The outgoing data packets are then routed to the first-tier logical router of the cloud gateway device, where the outgoing data packets are transmitted a destination network from a particular interface of the first-tier logical router of the cloud gateway device.
    Type: Grant
    Filed: October 25, 2021
    Date of Patent: December 19, 2023
    Assignee: VMWARE, INC.
    Inventors: Rahul Jain, Mukesh Hira
  • Patent number: 11842981
    Abstract: Examples relate to a die interconnect substrate comprising a bridge die comprising at least one bridge interconnect connecting a first bridge die pad of the bridge die to a second bridge die pad of the bridge die. The die interconnect substrate further comprises a substrate structure comprising a substrate interconnect electrically insulated from the bridge die, wherein the bridge die is embedded in the substrate structure. The die interconnect substrate further comprises a first interface structure for attaching a semiconductor die to the substrate structure, wherein the first interface structure is connected to the first bridge die pad. The die interconnect substrate further comprises a second interface structure for attaching a semiconductor die to the substrate structure, wherein the second interface structure is connected to the substrate interconnect. A surface of the first interface structure and a surface of the second interface structure are at the same height.
    Type: Grant
    Filed: September 3, 2021
    Date of Patent: December 12, 2023
    Assignee: Intel Corporation
    Inventors: Rahul Jain, Ji Yong Park, Kyu Oh Lee
  • Patent number: 11821626
    Abstract: An adapter and adapter system for connecting a female end of a first chimney portion to a male end of a second chimney portion. The adapter includes a first radial adapter portion with a first inner surface and a first outer surface extending along a first axis and wherein the first inner surface and the first outer surface are substantially coaxial. The adapter further includes a first locking interface protruding outward from the first outer surface and configured to engage with a first locking interface of the first chimney portion and a second locking interface protruding inward from the first inner surface and configured to engage with a second interlocking interface of the second chimney. The first outer surface of the adapter is configured to be received within the female end of the first chimney portion and the inner surface is configured to receive the male end of the second chimney.
    Type: Grant
    Filed: July 22, 2019
    Date of Patent: November 21, 2023
    Assignee: Cardinal IP Holding, LLC
    Inventors: Rahul Jain, Satyendra Kumar, Rajat Saxena, Adam Michael Ryczek, Thomas J. Dykhuis
  • Publication number: 20230345621
    Abstract: Microelectronic assemblies, and related devices and methods, are disclosed herein. For example, in some embodiments, a microelectronic assembly may include a dielectric layer, in a substrate, the dielectric layer including an electroless catalyst, wherein the electroless catalyst includes one or more of palladium, gold, silver, ruthenium, cobalt, copper, nickel, titanium, aluminum, lead, silicon, and tantalum; a first conductive trace having a first thickness in the dielectric layer, wherein the first thickness is between 4 um and 143 um; and a second conductive trace having a second thickness in the dielectric layer, wherein the second thickness is between 2 um and 141 um, wherein the first thickness is greater than the second thickness, and wherein the first conductive trace and the second conductive trace have sloped sidewalls.
    Type: Application
    Filed: June 30, 2023
    Publication date: October 26, 2023
    Applicant: Intel Corporation
    Inventors: Brandon C. Marin, Andrew James Brown, Rahul Jain, Dilan Seneviratne, Praneeth Kumar Akkinepally, Frank Truong
  • Publication number: 20230343723
    Abstract: Embodiments disclosed herein include electronic packages with thermal solutions. In an embodiment, an electronic package comprises a package substrate, a first die electrically coupled to the package substrate, and an integrated heat spreader (IHS) that is thermally coupled to a surface of the first die. In an embodiment, the IHS comprises a main body having an outer perimeter, and one or more legs attached to the outer perimeter of the main body, wherein the one or more legs are supported by the package substrate. In an embodiment, the electronic package further comprises a thermal block between the package substrate and the main body of the IHS, wherein the thermal block is within the outer perimeter of the main body.
    Type: Application
    Filed: June 29, 2023
    Publication date: October 26, 2023
    Inventors: Nicholas NEAL, Nicholas S. HAEHN, Sergio CHAN ARGUEDAS, Edvin CETEGEN, Jacob VEHONSKY, Steve S. CHO, Rahul JAIN, Antariksh Rao Pratap SINGH, Tarek A. IBRAHIM, Thomas HEATON
  • Publication number: 20230333775
    Abstract: Aspects of a storage device are provided that handle pairing and atomic processing of fused commands received from submission queues based on data structures such as a linked lists which the controller respectively associates with each submission queue. A memory of the storage device includes a plurality of data structures each associated with a different submission queue. A controller of the storage device receives a first command for a fused operation from a submission queue, stores the first command in a data structure, receives a second command for the fused operation from the submission queue, determines whether the second command corresponds to the fused operation, stores the second command in the data structure in response to the determination, and performs the fused operation in response to storing the second command. As a result, fused command handling may be achieved with minimal impact to queue arbitration logic and command latency.
    Type: Application
    Filed: April 13, 2022
    Publication date: October 19, 2023
    Inventors: Rahul JAIN, Arvind Kumar V M
  • Patent number: 11776864
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment an electronic package comprises a package substrate, and a first level interconnect (FLI) bump region on the package substrate. In an embodiment, the FLI bump region comprises a plurality of pads, and a plurality of bumps, where each bump is over a different one of the plurality of pads. In an embodiment, the electronic package further comprises a guard feature adjacent to the FLI bump region. In an embodiment, the guard feature comprises, a guard pad, and a guard bump over the guard pad, wherein the guard feature is electrically isolated from circuitry of the electronic package.
    Type: Grant
    Filed: July 15, 2019
    Date of Patent: October 3, 2023
    Assignee: Intel Corporation
    Inventors: Jacob Vehonsky, Nicholas S. Haehn, Thomas Heaton, Steve S. Cho, Rahul Jain, Tarek Ibrahim, Antariksh Rao Pratap Singh, Edvin Cetegen, Nicholas Neal, Sergio Chan Arguedas
  • Patent number: 11770292
    Abstract: A cloud extension agent can be provided on a customer premise for interfacing, via an outbound secure connection, cloud based services.
    Type: Grant
    Filed: June 25, 2020
    Date of Patent: September 26, 2023
    Assignee: Snowflake Inc.
    Inventors: Vineeth Narasimhan, Joshua Lambert, Thomas Herchek, Ryan Elliot Hope, Nitish Jha, Rahul Jain, Sumeet Singh
  • Patent number: 11768753
    Abstract: Methods, systems, and computer-readable media are disclosed herein for a concurrent comparative tool for assessing multiple versions of a data model in a pre-deployment environment to ensure that any subsequently deployed version will perform than a current version of the data model. In aspects, the tool extracts observed and predictive data for various versions and comparatively evaluates the performance measures of each version. The performance measures can be validated across the versions to determine and select a leading version that has demonstrated improve technological performance and predictive accuracy. The leading version can be deployed.
    Type: Grant
    Filed: July 11, 2022
    Date of Patent: September 26, 2023
    Assignee: Cerner Innovation, Inc.
    Inventors: James Gritter, Ashwin Chhetri, Rahul Jain V, Uttam Ramamurthy, Pankaj Saxena
  • Publication number: 20230290545
    Abstract: A switch assembly including a switch and an interface physically coupled to the switch and configured to be physically coupled to an electrical component, such as a transformer. The switch assembly also includes an interface having electrical hardware electrically coupled to the switch and configured to be electrically coupled to the component. The switch assembly further includes a surge arrester having an insulation member, a grounding jacket formed over a portion of the insulation member and a conductor extending through the insulation member and being electrically coupled to the hardware and the grounding jacket. The interface further includes a releasable connector that is electrically coupled to the conductor and allows the surge arrester to be disconnected from the interface.
    Type: Application
    Filed: February 24, 2023
    Publication date: September 14, 2023
    Applicant: S&C Electric Company
    Inventors: Thomas S. Kelley, Mark Francis Muir, Andrew B. Berman, Xin Guo Zhu, Rahul Jain