Patents by Inventor Rahul N. Manepalli

Rahul N. Manepalli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240096809
    Abstract: Microelectronic assemblies, related devices and methods, are disclosed herein.
    Type: Application
    Filed: September 15, 2022
    Publication date: March 21, 2024
    Applicant: Intel Corporation
    Inventors: Hiroki Tanaka, Robert Alan May, Onur Ozkan, Ali Lehaf, Steve Cho, Gang Duan, Jieping Zhang, Rahul N. Manepalli, Ravindranath Vithal Mahajan, Hamid Azimi
  • Patent number: 11935805
    Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: April 12, 2023
    Date of Patent: March 19, 2024
    Assignee: Intel Corporation
    Inventors: Rahul Jain, Kyu Oh Lee, Siddharth K. Alur, Wei-Lun K. Jen, Vipul V. Mehta, Ashish Dhall, Sri Chaitra J. Chavali, Rahul N. Manepalli, Amruthavalli P. Alur, Sai Vadlamani
  • Publication number: 20240088121
    Abstract: Techniques for a patch to couple one or more surface dies to an interposer or motherboard are provided. In an example, the patch can include multiple embedded dies. In an example, a microelectronic device can be formed to include a patch on an interposer, where the patch can include multiple embedded dies and each die can have a different thickness.
    Type: Application
    Filed: November 16, 2023
    Publication date: March 14, 2024
    Inventors: Srinivas PIETAMBARAM, Robert Alan MAY, Kristof DARMAWIKARTA, Hiroki TANAKA, Rahul N. MANEPALLI, Sri Ranga Sai BOYAPATI
  • Patent number: 11923307
    Abstract: Disclosed herein are microelectronic structures including bridges, as well as related assemblies and methods. In some embodiments, a microelectronic structure may include a substrate and a bridge.
    Type: Grant
    Filed: June 16, 2020
    Date of Patent: March 5, 2024
    Assignee: Intel Corporation
    Inventors: Bai Nie, Gang Duan, Omkar G. Karhade, Nitin A. Deshpande, Yikang Deng, Wei-Lun Jen, Tarek A. Ibrahim, Sri Ranga Sai Boyapati, Robert Alan May, Yosuke Kanaoka, Robin Shea McRee, Rahul N. Manepalli
  • Publication number: 20240063069
    Abstract: Embodiments disclosed herein include package substrates with glass cores. In an embodiment, a core comprises a substrate with a first surface and a second surface opposite from the first surface. In an embodiment, the substrate comprises glass, In an embodiment, through glass vias (TGVs) pass through the substrate, and notches are formed into the first surface and the second surface of the substrate.
    Type: Application
    Filed: August 22, 2022
    Publication date: February 22, 2024
    Inventors: Brandon C. MARIN, Rahul N. MANEPALLI, Ravindranath V. MAHAJAN, Srinivas V. PIETAMBARAM, Jeremy D. ECTON, Gang DUAN, Suddhasattwa NAD
  • Publication number: 20240055345
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a substrate, where the substrate comprises glass. In an embodiment, a pillar is over the substrate, and a capacitor is over the pillar. In an embodiment, the capacitor comprises a first conductive layer on the pillar, a dielectric layer over the first conductive layer, and a second conductive layer over the dielectric layer.
    Type: Application
    Filed: August 11, 2022
    Publication date: February 15, 2024
    Inventors: Brandon C. MARIN, Srinivas V. PIETAMBARAM, Gang DUAN, Suddhasattwa NAD, Jeremy D. ECTON, Rahul N. MANEPALLI
  • Patent number: 11901248
    Abstract: Various examples provide a semiconductor patch. The patch includes a glass core having first and second opposed major surfaces extending in an x-y direction. The patch further includes a conductive via extending from the first major surface to the second major surface substantially in a z-direction. The patch further includes a bridge die embedded in a dielectric material in communication with the conductive via. The patch further includes an overmold at least partially encasing the glass core.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: February 13, 2024
    Assignee: Intel Corporation
    Inventors: Robert L. Sankman, Rahul N. Manepalli, Robert Alan May, Srinivas Venkata Ramanuja Pietambaram, Bharat P. Penmecha
  • Publication number: 20240006297
    Abstract: Embodiments herein relate to systems, apparatuses, or processes for forming a silicide and a silicon nitrate layer between a copper feature and dielectric to reduce delamination of the dielectric. Embodiments allow an unroughened surface for the copper feature to reduce the insertion loss for transmission lines that go through the unroughened surface of the copper. Embodiments may include sequential interlayers between a dielectric and copper. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: June 29, 2022
    Publication date: January 4, 2024
    Inventors: Suddhasattwa NAD, Kristof DARMAWIKARTA, Srinivas V. PIETAMBARAM, Tarek A. IBRAHIM, Rahul N. MANEPALLI, Darko GRUJICIC, Marcel WALL, Yi YANG
  • Publication number: 20240006283
    Abstract: Embodiments disclosed herein include package substrates and methods of forming such substrates. In an embodiment, a package substrate comprises a core, a first layer over the core, where the first layer comprises a metal, and a second layer over the first layer, where the second layer comprises an electrical insulator. In an embodiment, the package substrate further comprises a third layer over the second layer, where the third layer comprises a dielectric material, and where an edge of the core extends past edges of the first layer, the second layer, and the third layer.
    Type: Application
    Filed: June 29, 2022
    Publication date: January 4, 2024
    Inventors: Suddhasattawa NAD, Rahul N. MANEPALLI, Gang DUAN, Srinivas V. PIETAMBARAM, Yi YANG, Marcel WALL, Darko GRUJICIC, Haobo CHEN, Aaron GARELICK
  • Patent number: 11862619
    Abstract: Techniques for a patch to couple one or more surface dies to an interposer or motherboard are provided. In an example, the patch can include multiple embedded dies. In an example, a microelectronic device can be formed to include a patch on an interposer, where the patch can include multiple embedded dies and each die can have a different thickness.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: January 2, 2024
    Assignee: Intel Corporation
    Inventors: Srinivas Pietambaram, Robert Alan May, Kristof Darmawikarta, Hiroki Tanaka, Rahul N. Manepalli, Sri Ranga Sai Boyapati
  • Publication number: 20230420375
    Abstract: A glass substrate houses an embedded multi-die interconnect bridge that is part of a semiconductor device package. Through-glass vias communicate to a surface for mounting on a semiconductor package substrate.
    Type: Application
    Filed: September 12, 2023
    Publication date: December 28, 2023
    Inventors: Srinivas V. PIETAMBARAM, Tarek IBRAHIM, Kristof DARMAWIKARTA, Rahul N. MANEPALLI, Debendra MALLIK, Robert L. SANKMAN
  • Publication number: 20230361043
    Abstract: Electrical interconnect bridge technology is disclosed. An electrical interconnect bridge can include a bridge substrate formed of a mold compound material. The electrical interconnect bridge can also include a plurality of routing layers within the bridge substrate, each routing layer having a plurality of fine line and space (FLS) traces. In addition, the electrical interconnect bridge can include a via extending through the substrate and electrically coupling at least one of the FLS traces in one of the routing layers to at least one of the FLS traces in another of the routing layers.
    Type: Application
    Filed: July 20, 2023
    Publication date: November 9, 2023
    Applicant: Intel Corporation
    Inventors: Srinivas V. PIETAMBARAM, Rahul N. MANEPALLI
  • Patent number: 11810859
    Abstract: Structures are described that include multi-layered adhesion promotion films over a conductive structure in a microelectronic package. The multi-layered aspect provides adhesion to surrounding dielectric material without a roughened surface of the conductive structure. Furthermore, the multi-layered aspect allows for materials with different dielectric constants to be used, the average of which can provide a closer match to the dielectric constant of the surrounding dielectric material. According to an embodiment, a first dielectric layer that includes at least one nitride material can provide good adhesion with the underlying conductive structure, while one or more subsequent dielectric layers that include at least one oxide material can provide different dielectric constant values (e.g., typically lower) compared to the first dielectric layer to bring the overall dielectric constant closer to that of a surrounding dielectric material.
    Type: Grant
    Filed: February 18, 2020
    Date of Patent: November 7, 2023
    Assignee: Intel Corporation
    Inventors: Srinivas V. Pietambaram, Rahul N. Manepalli, Cemil S. Geyik, Kemal Aygun
  • Patent number: 11798887
    Abstract: A glass substrate houses an embedded multi-die interconnect bridge that is part of a semiconductor device package. Through-glass vias communicate to a surface for mounting on a semiconductor package substrate.
    Type: Grant
    Filed: October 1, 2021
    Date of Patent: October 24, 2023
    Assignee: Intel Corporation
    Inventors: Srinivas V. Pietambaram, Tarek Ibrahim, Kristof Darmawikarta, Rahul N. Manepalli, Debendra Mallik, Robert L. Sankman
  • Patent number: 11791269
    Abstract: Electrical interconnect bridge technology is disclosed. An electrical interconnect bridge can include a bridge substrate formed of a mold compound material. The electrical interconnect bridge can also include a plurality of routing layers within the bridge substrate, each routing layer having a plurality of fine line and space (FLS) traces. In addition, the electrical interconnect bridge can include a via extending through the substrate and electrically coupling at least one of the FLS traces in one of the routing layers to at least one of the FLS traces in another of the routing layers.
    Type: Grant
    Filed: July 17, 2020
    Date of Patent: October 17, 2023
    Assignee: Intel Corporation
    Inventors: Srinivas V. Pietambaram, Rahul N. Manepalli
  • Publication number: 20230317614
    Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate with a plurality of first layers, where the first layers comprise an organic material. In an embodiment, a trace is embedded in the package substrate, and a second layer is over the trace, where the second layer comprises silicon and nitrogen.
    Type: Application
    Filed: March 29, 2022
    Publication date: October 5, 2023
    Inventors: Yi YANG, Rahul N. MANEPALLI, Suddhasattwa NAD, Marcel WALL, Benjamin DUONG
  • Publication number: 20230317584
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a package substrate with a plurality of first layers, where the first layers comprise an organic material. In an embodiment, a trace is embedded in the package substrate. In an embodiment, a second layer is over the trace, where the second layer comprises silicon and nitrogen, and wherein the second layer is chemically bonded to one of the first layers by an oxygen containing ligand and/or a nitrogen containing ligand.
    Type: Application
    Filed: March 29, 2022
    Publication date: October 5, 2023
    Inventors: Yi YANG, Suddhasattwa NAD, Marcel WALL, Rahul N. MANEPALLI, Benjamin DUONG
  • Publication number: 20230317583
    Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, an electronic package comprises a package substrate with a plurality of first layers, where the first layers comprise an organic material. In an embodiment, a trace is embedded in the package substrate. In an embodiment, a second layer is over the trace, where the second layer comprises silicon, nitrogen, and a catalyst, and where the second layer is chemically bonded to one of the first layers.
    Type: Application
    Filed: March 29, 2022
    Publication date: October 5, 2023
    Inventors: Rahul N. MANEPALLI, Yi YANG, Suddhasattwa NAD, Benjamin DUONG, Marcel WALL
  • Publication number: 20230245940
    Abstract: An apparatus is provided which comprises: a substrate, a die site on the substrate to couple with a die, a die side component site on the substrate to couple with a die side component, and a raised barrier on the substrate between the die and die side component sites to contain underfill material disposed at the die site, wherein the raised barrier comprises electroplated metal. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: April 12, 2023
    Publication date: August 3, 2023
    Applicant: Intel Corporation
    Inventors: Rahul JAIN, Kyu Oh LEE, Siddharth K. ALUR, Wei-Lun K. JEN, Vipul V. MEHTA, Ashish DHALL, Sri Chaitra J. CHAVALI, Rahul N. MANEPALLI, Amruthavalli P. ALUR, Sai VADLAMANI
  • Publication number: 20230197660
    Abstract: A computer apparatus includes a hierarchy of solder joints in a multi-chip package, with solder joints at different levels of the packaging having different melting temperatures. Interconnections, such as pads or pins, on integrated circuit (IC) die can be electrically coupled to ends of contact pillars with solder joints having a higher melting temperature. The other ends of the contact pillars can electrically couple to another substrate or another device with solder joints having a lower melting temperature. The contact pillars can be, for example, a contact array or through-hole via in a substrate.
    Type: Application
    Filed: December 21, 2021
    Publication date: June 22, 2023
    Inventors: Yue DENG, Jung Kyu HAN, Liang HE, Gang DUAN, Rahul N. MANEPALLI