Patents by Inventor Rainer Goettfert
Rainer Goettfert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20150032992Abstract: A processing arrangement having a first processing component and a second processing component is provided. The first component has a first output memory and a second output memory and a control device using the first memory storing a value to be output and the second memory stores a value that is based according to a prescribed function on the value. The control device stores a new value in the first memory whenever the second component has read a value stored in the first memory. The second component has a reading device reading the values stored in the first and second memories, and a processing device that checks whether the value read from the second memory is based according to the prescribed function on the value read from the first memory and, depending on the result, to process the value read from the first memory.Type: ApplicationFiled: July 28, 2014Publication date: January 29, 2015Inventors: Rainer Goettfert, Berndt Gammel, Gerd Dirscherl
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Patent number: 8879733Abstract: A random bit stream generator includes an internal state memory for storing a current internal state of the random bit stream generator and a periodic bit sequence generator configured to provide a periodic bit sequence. An output function receives a bit sequence portion of the periodic bit sequence and a first internal state portion of the current internal state. A new output bit of the random bit stream is determined, by the output function, based on a Boolean combination of the bit sequence portion and the first internal state portion. A feedback arrangement feeds the new output bit back to the internal state memory by performing a Boolean combination involving the new output bit and a second internal state portion of the current internal state to determine a next internal state of the random bit generator.Type: GrantFiled: July 10, 2012Date of Patent: November 4, 2014Assignee: Infineon Technologies AGInventors: Rainer Goettfert, Berndt Gammel, Markus Gail
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Patent number: 8861725Abstract: A random bit stream generator includes a plurality of feedback shift registers configured to store a plurality of bit values that represent an internal state of the random bit stream generator. Each feedback shift register includes a register input and a register output. The random bit stream generator further includes a Boolean output function configured to receive the plurality of register outputs from the plurality of feedback registers, to perform a first Boolean combination of the plurality of register outputs, and to provide a corresponding output bit, wherein a plurality of successive output bits forms a random bit stream. A feedback loop is configured to perform a second Boolean combination of the output bit with at least one register feedback bit of at least one of the feedback shift registers, so that the register input of the at least one feedback shift register is a function of the output bit.Type: GrantFiled: July 10, 2012Date of Patent: October 14, 2014Assignee: Infineon Technologies AGInventors: Rainer Goettfert, Berndt Gammel, Markus Gail, Wieland Fischer
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Patent number: 8781114Abstract: An apparatus for recognizing a failure in a cryptographic unit, wherein the cryptographic unit includes a determinator for determining an input control signal and an output control signal, with the determinator being formed to determine the input control signal on the basis of an encryption of an input control signal parity of a group of input signals or an input signal of the group of input signals with an encryption number and to determine the output control signal on the basis of an encryption of an output control signal parity of a group of the output signals or an output signal of the group of output signals with the encryption number. Furthermore, the apparatus for recognizing includes an evaluator for evaluating the input control signal and the output control signal to recognize a failure of the cryptographic unit on the basis of a comparison between the input control signal and the output control signal.Type: GrantFiled: September 7, 2005Date of Patent: July 15, 2014Assignee: Infineon Technologies AGInventors: Berndt Gammel, Michael Goessel, Rainer Goettfert
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Patent number: 8726123Abstract: A bit error corrector includes an aging bit pattern memory operable to store at least one aging bit pattern which conveys aging-related effects within a succession of uncorrected bit patterns, a bit pattern modifier operable to modify a current, uncorrected bit pattern using the at least one aging bit pattern and generate a modified bit pattern, and a bit pattern comparator operable to compare the current uncorrected bit pattern with a corrected bit pattern which is based on the modified bit pattern and determine a corresponding comparative bit pattern. An aging bit pattern determiner is operable to recursively determine a new aging bit pattern based on the at least one aging bit pattern and the comparative bit pattern, and store the new aging bit pattern in the aging bit pattern memory for use during modification of a subsequent uncorrected bit pattern by the bit pattern modifier.Type: GrantFiled: July 13, 2012Date of Patent: May 13, 2014Assignee: Infineon Technologies AGInventors: Rainer Goettfert, Berndt Gammel, Thomas Kuenemund
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Publication number: 20140032990Abstract: A decoder comprises a feedback shift register having a plurality of register elements that implement a simplex code and take a register vector for determining an appropriate syndrome fed into the feedback shift register and stored in the plurality of register elements. A combination device algebraically combines a subset of the register elements and provides a combination result vector. A majority decision-making unit ascertains a most frequently occurring value within the combination result vector and provides it as a decision result. An input selector connects an input of the feedback shift register to an input interface arrangement or to an output of the majority decision-making unit, and provides an input vector by the input interface arrangement and corresponds to the ascertained form of the physical unclonable properties as a register vector and, and provides a decision vector comprising the decision result and further decision results as a register vector.Type: ApplicationFiled: July 25, 2013Publication date: January 30, 2014Applicant: Infineon Technologies AGInventor: Rainer Goettfert
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Publication number: 20140016778Abstract: A random bit stream generator includes an internal state memory for storing a current internal state of the random bit stream generator and a periodic bit sequence generator configured to provide a periodic bit sequence. An output function receives a bit sequence portion of the periodic bit sequence and a first internal state portion of the current internal state. A new output bit of the random bit stream is determined, by the output function, based on a Boolean combination of the bit sequence portion and the first internal state portion. A feedback arrangement feeds the new output bit back to the internal state memory by performing a Boolean combination involving the new output bit and a second internal state portion of the current internal state to determine a next internal state of the random bit generator.Type: ApplicationFiled: July 10, 2012Publication date: January 16, 2014Applicant: INFINEON TECHNOLOGIES AGInventors: Rainer Goettfert, Berndt Gammel, Markus Gail
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Publication number: 20140019502Abstract: A random bit stream generator includes a plurality of feedback shift registers configured to store a plurality of bit values that represent an internal state of the random bit stream generator. Each feedback shift register includes a register input and a register output. The random bit stream generator further includes a Boolean output function configured to receive the plurality of register outputs from the plurality of feedback registers, to perform a first Boolean combination of the plurality of register outputs, and to provide a corresponding output bit, wherein a plurality of successive output bits forms a random bit stream. A feedback loop is configured to perform a second Boolean combination of the output bit with at least one register feedback bit of at least one of the feedback shift registers, so that the register input of the at least one feedback shift register is a function of the output bit.Type: ApplicationFiled: July 10, 2012Publication date: January 16, 2014Applicant: Infineon Technologies AGInventors: Rainer Goettfert, Berndt Gammel, Markus Gail, Wieland Fischer
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Patent number: 8595277Abstract: A hybrid random number generator (HRNG) including an output, a combinational logic, a TRNG, and a PRNG. The HRNG is configurable to operate in a first and a second mode, wherein in the first mode the PRNG is serially connected between the TRNG and the output and the TRNG intermittently influences the PRNG, and in the second mode the TRNG and the PRNG are connected to the output via the combinational logic.Type: GrantFiled: February 13, 2008Date of Patent: November 26, 2013Assignee: Infineon Technologies AGInventors: Rainer Goettfert, Stefan Rueping, Berndt Gammel
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Publication number: 20130246881Abstract: A method for reconstructing a physically uncloneable function (PUF) A for use in an electronic device is provided. The method includes generating a potentially erroneous PUF At and performing a preliminary correction of the potentially erroneous PUF At by means of a stored correction vector Deltat-1, to obtain a preliminarily corrected PUF Bt. The PUF A is reconstructed from the preliminarily corrected PUF Bt by means of an error correction algorithm. A corresponding apparatus is also provided.Type: ApplicationFiled: March 14, 2013Publication date: September 19, 2013Inventors: Rainer Goettfert, Gerd Dirscherl, Berndt Gammel, Thomas Kuenemund
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Patent number: 8533557Abstract: A device for protecting a data word against data corruption includes first and second determiners. The first determiner is configured to determine an error correction code cvA associated with a data word a so that cvA=aAT, with A being a generator matrix of a linear systematic base correction code, the columns of which enable performance of an x-bit error correction on replica of the data word a and the associated error correction code cvA. The second determiner is configured to determine an extended error correction code cvE so that (cvA|cvE)=aFT, with F being an extended generator matrix F = ( A E ) of an extended linear systematic correction code, the columns of which enable, using the extension error correction code cvE, performance of an y-bit error correction, with y>x, on a replica of the data word a and the associated error correction code cvA.Type: GrantFiled: January 28, 2011Date of Patent: September 10, 2013Assignee: Infineon Technologies AGInventors: Jan Otterstedt, Rainer Goettfert
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Publication number: 20130185611Abstract: A bit error corrector includes an aging bit pattern memory operable to store at least one aging bit pattern which conveys aging-related effects within a succession of uncorrected bit patterns, a bit pattern modifier operable to modify a current, uncorrected bit pattern using the at least one aging bit pattern and generate a modified bit pattern, and a bit pattern comparator operable to compare the current uncorrected bit pattern with a corrected bit pattern which is based on the modified bit pattern and determine a corresponding comparative bit pattern. An aging bit pattern determiner is operable to recursively determine a new aging bit pattern based on the at least one aging bit pattern and the comparative bit pattern, and store the new aging bit pattern in the aging bit pattern memory for use during modification of a subsequent uncorrected bit pattern by the bit pattern modifier.Type: ApplicationFiled: July 13, 2012Publication date: July 18, 2013Applicant: INFINEON TECHNOLOGIES AGInventors: Rainer Goettfert, Berndt Gammel, Thomas Kuenemund
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Patent number: 8250659Abstract: By arranging a redundancy means and a control means upstream from an encryption means which encrypts and decrypts the data to be stored in an external memory, the integrity of data may be ensured when the generation of redundancy information is realized by the redundancy means, and when the generation of a syndrome bit vector indicating any alteration of the data is implemented by the control means. What is preferred is a control matrix constructed from idempotent, thinly populated, circulant square sub-matrices only. By arranging redundancy and control means upstream from the encryption/decryption means, what is achieved is that both errors in the encrypted data and errors of the non-encrypted data may be proven, provided that they have occurred in the data path between the redundancy/control means and the encryption/decryption means.Type: GrantFiled: June 19, 2006Date of Patent: August 21, 2012Assignee: Infineon Technologies AGInventors: Berndt Gammel, Rainer Goettfert
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Publication number: 20120198302Abstract: A device for protecting a data word against data corruption includes first and second determiners. The first determiner is configured to determine an error correction code cvA associated with a data word a so that cvA=aAT, with A being a generator matrix of a linear systematic base correction code, the columns of which enable performance of an x-bit error correction on replica of the data word a and the associated error correction code cvA. The second determiner is configured to determine an extended error correction code cvE so that (cvA|cvE)=aFT, with F being an extended generator matrix F = ( A E ) of an extended linear systematic correction code, the columns of which enable, using the extension error correction code cvE, performance of an y-bit error correction, with y>x, on a replica of the data word a and the associated error correction code cvA.Type: ApplicationFiled: January 28, 2011Publication date: August 2, 2012Applicant: INFINEON TECHNOLOGIES AGInventors: Jan Otterstedt, Rainer Goettfert
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Patent number: 8180816Abstract: A system having a pseudo random number generator, a control circuit being configured to increase a quality of a pseudo random number output signal of the pseudo random number generator by coupling the pseudo random number generator with a true random number output signal of a true random number generator and a consumer circuit being configured to use the pseudo random number output signal before and after the increase.Type: GrantFiled: November 30, 2007Date of Patent: May 15, 2012Assignee: Infineon Technologies AGInventors: Stefan Rueping, Rainer Goettfert
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Patent number: 8141167Abstract: A communication device for transmitting data to a communication partner device includes a transmitter for transmitting transmit data to the communication partner device, a determiner for determining a check value from the transmit data in accordance with a determination specification, a receiver for receiving a verification value from the communication partner device, and a checker configured to compare the check value with the verification value and to provide a fault indication signal as a function of the comparison.Type: GrantFiled: June 1, 2006Date of Patent: March 20, 2012Assignee: Infineon Technologies AGInventors: Berndt Gammel, Rainer Goettfert, Oliver Kniffler, Dietmar Scheiblhofer
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Patent number: 8060757Abstract: An encryption part or a decryption part of an encryption/decryption apparatus or a part common to both parts is used both for encryption and decryption of a datum to be stored and the encrypted memory content and for the generation of the address-individual key and the address-dependent key, respectively.Type: GrantFiled: March 30, 2006Date of Patent: November 15, 2011Assignee: Infineon Technologies AGInventors: Rainer Goettfert, Erwin Hess, Bernd Meyer, Steffen Sonnekalb
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Patent number: 7979482Abstract: A random number generator includes a plurality of memory cells arranged in a series, a feedback processor for generating a feedback signal and for feeding the feedback signal into one of the memory cells, and a random number outputter formed to combine states of a group of at least two memory cells to obtain an output sequence. Sequences strongly differing from one another, the number of which is greater than the number of memory cells, can be generated by generating several output sequences AF0, AF1, AF2, . . . , AFk by combining states of different memory cells such that a safe and efficient bus encryption is achievable.Type: GrantFiled: March 18, 2005Date of Patent: July 12, 2011Assignee: Infineon Technologies AGInventors: Berndt Gammel, Rainer Goettfert
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Patent number: 7764789Abstract: A bit sequence which is generated by a feedback shift register is decimated with a variable decimation value m (m?|N) in a predetermined manner which is known on the decryption side, i.e. in that every mth bit of the bit sequence is picked out from the bit sequence so as to obtain the key bit stream.Type: GrantFiled: March 4, 2005Date of Patent: July 27, 2010Assignee: Infineon Technologies AGInventors: Rainer Goettfert, Berndt Gammel, Kalman Cinkler, Stefan Rueping
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Patent number: 7734969Abstract: Feedback shift register control circuit including a checking circuit having an input being coupled to a seed input of a feedback shift register or to an internal node of the feedback shift register, the checking circuit configured to be responsive to a signal at the input indicating that the feedback shift register is in a not-allowed state, or is going to assume a not-allowed state to output an exception signal; and a gate circuit being coupled to the seed input or the feedback shift register and configured to be responsive to the exception signal to change the state of the feedback shift register or seed the feedback shift register such that the feedback shift register assumes an allowed state.Type: GrantFiled: October 30, 2007Date of Patent: June 8, 2010Assignee: Infineon Technologies AGInventors: Rainer Goettfert, Stefan Rueping