Patents by Inventor Raj Kumar

Raj Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20190340202
    Abstract: An electronic device for providing contextual recommendations and a method therefor are provided. The electronic device includes a memory storing instructions, and at least one processor configured to execute the instructions to obtain text including characters, identify, based on a language model, a domain corresponding to the text, identify a reference of the characters based on the domain, and perform, based on the reference, an action related to the domain.
    Type: Application
    Filed: May 2, 2019
    Publication date: November 7, 2019
    Inventors: Barath Raj KANDUR RAJA, Ankur AGARWAL, Arko SABUI, Arjun Raj Kumar S, Shashank SRIRAM, Himanshi SINHA, Ketki Aniruddha GUPTE, Vibhav AGARWAL
  • Publication number: 20190313312
    Abstract: An electronic device includes a communication circuitry, a processor electrically connected with the communication circuitry, a memory electrically connected with the processor. The memory stores instructions, when executed, causing the processor to connect the electronic device and a first network using the communication circuitry, determine a first user context among user contexts which are data associated with an operation state of the electronic device, and maintain a connection with the first network based on whether communication quality of the first network meets first communication quality corresponding to the determined first user context or switch from the first network to a second network different from the first network. Various other embodiments recognized from the specification are also possible.
    Type: Application
    Filed: December 6, 2017
    Publication date: October 10, 2019
    Inventors: Ashish GUPTA, Manbir Singh SONI, Parveen DUDANI, Gi Beom KIM, Yong Hae CHOI, Raj Kumar SARANAPP, Prashanta C MUTNAL
  • Publication number: 20190286782
    Abstract: Provided is a method for performing connectivity verification of an integrated circuit device. In embodiments of the invention, the method includes creating a directed graph representation of integrated circuit device. The method can further include determining target gates referred to as trace signals within integrated circuit device. The method can further include creating hierarchical representation of trace signals and determining nested trace signals. The method can further include determining one or more locations for cut points for non-nested trace signals. Thereafter, performing connectivity verification using the one or more locations for cut points. Finally improving the scalability of connectivity verification by utilizing hierarchical decomposition embodiment of the invention.
    Type: Application
    Filed: March 15, 2018
    Publication date: September 19, 2019
    Inventors: Pradeep Kumar Nalla, Raj Kumar Gajavelly, Jason Baumgartner, Raja Bilwakeshwar Ivaturi
  • Publication number: 20190287125
    Abstract: A service provider may receive item price information and/or point of sale (POS) transaction information from a plurality of merchant devices associated with a plurality of merchants. The service provider may categorize the plurality of merchants according to the types of items offered by the respective merchants, and may further categorize the merchants according to the locations at which they conduct business. The service provider may subsequently determine a price recommendation or other pricing information for a particular item offered by a particular merchant. A merchant device of the particular merchant may present the pricing information in a user interface that enables the merchant to view projected sales at various different price points. Further, the merchant may be able to specify one or more factors used for determining the recommend price, such as a desired business model, a desired clientele, a desired profit margin, or the like.
    Type: Application
    Filed: June 4, 2019
    Publication date: September 19, 2019
    Inventors: Abhay Raj Kumar, Rong Yan, Mason Ng, Gian Perrone, Mai Leduc
  • Publication number: 20190272214
    Abstract: A processor of an aspect includes a decode unit to decode a read from memory instruction. The read from memory instruction is to indicate a source memory operand and a destination storage location. The processor also includes an execution unit coupled with the decode unit. The execution unit, in response to the read from memory instruction, is to read data from the source memory operand, store an indication of defective data in an architecturally visible storage location, when the data is defective, and complete execution of the read from memory instruction without causing an exceptional condition, when the data is defective. Other processors, methods, systems, and instructions are disclosed.
    Type: Application
    Filed: May 20, 2019
    Publication date: September 5, 2019
    Inventors: Ashok Raj, Ron Gabor, Hisham Shafi, Sergiu Ghetie, Mohan J. Kumar, Theodros Yigzaw, Sarathy Jayakumar, Neeraj S. Upasani
  • Publication number: 20190259875
    Abstract: A transistor, such as laterally diffused (LD) transistor, having a band region below a drift well is disclosed. The band region and drift well are oppositely doped. The band region is self-aligned to the drift well. The band region reduces the depth of the drift well. A shallower drift well reduces risk of punch-through, improving reliability. In addition, the shallower drift well reduces the drain to body parasitic capacitance which improves performance.
    Type: Application
    Filed: February 19, 2018
    Publication date: August 22, 2019
    Inventors: Liming LI, Shaoqiang ZHANG, Ruchil Kumar JAIN, Raj Verma PURAKH
  • Patent number: 10387072
    Abstract: A systems and methods for dynamic address based minoring are disclosed. A system may include a processor, comprising a mirror address range register to store data indicating a location and a size of a first portion of a system memory to be mirrored. The processor may further include a memory controller coupled to the mirror address range register and including circuitry to cause a second portion of the system memory to mirror the first portion of the system memory.
    Type: Grant
    Filed: December 29, 2016
    Date of Patent: August 20, 2019
    Assignee: Intel Corporation
    Inventors: Sarathy Jayakumar, Mohan J. Kumar, Ashok Raj, Hemalatha Gurumoorthy, Ronald N. Story
  • Patent number: 10389839
    Abstract: An apparatus comprises a processor to generate, in anticipation of receipt of a read request for data of a data set, a prefetch request to retrieve the data set from a memory device, the prefetch request to comprise at least one parameter indicating a size of the data set. The processor is further to cause transmission of the prefetch request to the memory device and in response to a read request for at least a portion of the data set, request the at least a portion of the data set from a cache storing a copy of the data set, wherein the cache is to store the copy of the data set after the copy is received from the memory device in response to the prefetch request.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: August 20, 2019
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Karthik Kumar, Thomas Willhalm, Raj K. Ramanujan, Brian J. Slechta
  • Patent number: 10379882
    Abstract: The disclosure discloses methods and systems for localizing a user interface based on a personal device of a user. The method includes receiving a personal device by a multi-function device, the personal device stores one or more documents, the personal device is associated with a name and each document is associated with a name, wherein the name of the personal device and the name of each document indicate a local language of the user. Upon receiving, the personal device is detected by the multi-function device. Then, the name of the personal device and the name of each document are extracted and compared with one or more pre-stored language patterns to detect the local language of the user. Upon detection, the pre-defined language of the user interface is automatically changed to the local language of the user.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: August 13, 2019
    Assignee: Xerox Corporation
    Inventors: Muralidaran Krishnasamy, Raj Kumar, Narayan Kesavan
  • Patent number: 10366436
    Abstract: A particular item may be categorized based on delivery times of the particular item. In some instances, the particular item may be ranked across multiple merchants that are offering the particular item for acquisition. The ranking may be based on an estimated amount of delivery time to deliver the particular item, for the individual merchants, to a current location of a user. The estimated amount of delivery time may be based on a preparation time for the respective merchant to prepare the particular item, a courier time for a courier to transport the particular item to the current location of the user, and so on. Information regarding the ranking may be displayed or otherwise output to enable the user to identify and order the particular item from a merchant that satisfies the user's needs.
    Type: Grant
    Filed: December 31, 2014
    Date of Patent: July 30, 2019
    Assignee: SQUARE, INC.
    Inventors: Abhay Raj Kumar, Matthew O'Connor, Zachary Brock, James F. Butts, III, Daniel Hipschman
  • Publication number: 20190218249
    Abstract: The present invention relates to a process for the purification of compound of formula II, wherein X may be independently selected from trifluoroacetic acid, hydrochloric acid, hydrobromic acid, p-toluene sulfonic acid and phosphoric acid; its isolation as solid and use for the preparation of carfilzomib.
    Type: Application
    Filed: September 13, 2017
    Publication date: July 18, 2019
    Applicant: FRESENIUS KABI ONCOLOGY LIMITED
    Inventors: Walter CABRI, Saswata LAHIRI, Govind SINGH, Sarbjot Singh SOKHI, Maneesh Kumar PANDEY, Raj Narayan TIWARI, Sonu Prasad SHUKLA
  • Patent number: 10346091
    Abstract: Methods and apparatus related to fabric resiliency support for atomic writes of many store operations to remote nodes are described. In one embodiment, non-volatile memory stores data corresponding to a plurality of write operations. A first node includes logic to perform one or more operations (in response to the plurality of write operations) to cause storage of the data at a second node atomically. The plurality of write operations are atomically bound to a transaction and the data is written to the non-volatile memory in response to release of the transaction. Other embodiments are also disclosed and claimed.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: July 9, 2019
    Assignee: Intel Corporation
    Inventors: Francesc Guim Bernat, Thomas Willhalm, Karthik Kumar, Martin P. Dimitrov, Raj K. Ramanujan
  • Publication number: 20190199620
    Abstract: Technologies for quality of service based throttling in a fabric architecture include a network node of a plurality of network nodes interconnected across the fabric architecture via an interconnect fabric. The network node includes a host fabric interface (HFI) configured to facilitate the transmission of data to/from the network node, monitor quality of service levels of resources of the network node used to process and transmit the data, and detect a throttling condition based on a result of the monitored quality of service levels. The HFI is further configured to generate and transmit a throttling message to one or more of the interconnected network nodes in response to having detected a throttling condition. The HFI is additionally configured to receive a throttling message from another of the network nodes and perform a throttling action on one or more of the resources based on the received throttling message. Other embodiments are described herein.
    Type: Application
    Filed: March 4, 2019
    Publication date: June 27, 2019
    Inventors: Francesc Guim Bernat, Karthik Kumar, Thomas Willhalm, Raj K. Ramanujan, Brian J. Slechta
  • Publication number: 20190186868
    Abstract: System for securing firearms and methods for making and using the same.
    Type: Application
    Filed: December 18, 2018
    Publication date: June 20, 2019
    Inventors: Eddilene Paola Cordero Pardo, Sy Cohen, Jonathan Ng, Ashwin Raj Kumar, Anthony R. Clarke
  • Patent number: 10324852
    Abstract: One embodiment provides for a data processing system comprising a multi-level system memory including a first memory level of volatile memory and a second memory level that is larger and slower in comparison with the first memory level. The second memory level includes non-volatile memory and can additionally include volatile memory. The multi-level system memory includes a multi-level memory controller including logic to manage a list of faulty addresses within the multi-level system memory. The multi-level memory controller can manage a list of faulty addresses. The multi-level memory controller is configured to satisfy a request for data stored in the first memory level from the second memory level when the data is stored in an address on the list of faulty addresses.
    Type: Grant
    Filed: December 9, 2016
    Date of Patent: June 18, 2019
    Assignee: INTEL CORPORATION
    Inventors: Theodros Yigzaw, Ashok Raj, Robert C. Swanson, Mohan J. Kumar
  • Publication number: 20190175615
    Abstract: The present disclosure is drawn to oral pharmaceutical compositions and dosage forms containing select testosterone esters and related methods. In one embodiment of the present invention, an oral pharmaceutical composition for administration to subjects in need of testosterone is provided. The composition comprises a testosterone ester and a pharmaceutically acceptable carrier. The testosterone ester can have the structure wherein R is —C13H25O or —C14H27O. One or both of the esters can be present in the pharmaceutical composition. The composition is formulated such that upon single dose administration to a group of human subject, the composition provides a mean serum testosterone Cavg t12-t24 that is within about 35% to about 70% of the mean serum testosterone Cavg t0-t24.
    Type: Application
    Filed: July 6, 2018
    Publication date: June 13, 2019
    Applicant: Lipocine Inc.
    Inventors: Satish Kumar Nachaegari, Chandrashekar Giliyar, Raj Patel, Nachiappan Chidambaram, Srinivansan Venkateshwaran, Mahesh V. Patel
  • Patent number: 10319458
    Abstract: Methods and apparatuses relating to a hardware memory test unit to check a section of a data storage device for a transient fault before the data is stored in and/or loaded from the section of the data storage device are described. In one embodiment, an integrated circuit includes a hardware processor to operate on data in a section of a data storage device, and a memory test unit to check the section of the data storage device for a transient fault before the data is stored in the section of the data storage device, wherein the transient fault is to cause a machine check exception if accessed by the hardware processor.
    Type: Grant
    Filed: March 13, 2017
    Date of Patent: June 11, 2019
    Assignee: Intel Corporation
    Inventors: Ashok Raj, Ron Gabor, Hisham Shafi, Mohan J. Kumar, Theodros Yigzaw
  • Publication number: 20190171556
    Abstract: Systems, apparatuses and methods may provide for detecting an issued request in a queue that is shared by a plurality of domains in a memory architecture, wherein the plurality of domains are associated with non-uniform access latencies. Additionally, a destination domain associated with the issued request may be determined. Moreover, a first set of additional requests may be prevented from being issued to the queue if the issued request satisfies an overrepresentation condition with respect to the destination domain and the first set of additional requests are associated with the destination domain. In one example, a second set of additional requests are permitted to be issued to the queue while the first set of additional requests are prevented from being issued to the queue, wherein the second set of additional requests are associated with one or more remaining domains in the plurality of domains.
    Type: Application
    Filed: November 29, 2018
    Publication date: June 6, 2019
    Inventors: Francesc Guim Bernat, Karthik Kumar, Thomas Willhalm, Raj K. Ramanujan, Brian J. Slechta
  • Patent number: 10311094
    Abstract: A method and system for description of synthetic audiovisual content makes it easier for humans, software components or devices to identify, manage, categorize, search, browse and retrieve such content. For instance, a user may wish to search for specific synthetic audiovisual objects in digital libraries, Internet web sites or broadcast media; such a search is enabled by the invention. Key characteristics of synthetic audiovisual content itself such as the underlying 2d or 3d models and parameters for animation of these models are used to describe it. To represent features of synthetic audiovisual content, depending on the description scheme to be used, a number of descriptors are selected and assigned values. The description scheme instantiated with descriptor values is used to generate the description, which is then stored for actual use during query/search.
    Type: Grant
    Filed: November 3, 2014
    Date of Patent: June 4, 2019
    Assignee: AT&T INTELLECTUAL PROPERTY II, L.P.
    Inventors: Qian Huang, Joern Ostermann, Atul Puri, Raj Kumar Rajendran
  • Publication number: 20190150622
    Abstract: This disclosure includes armrests having one or more laminates and methods and kits for making the same. Some armrests include an elongated beam extending between a first end and a second end, the elongated beam having one or more laminates configured to be disposed along the elongated beam, each including a plurality of fibers dispersed within a matrix material, and a reinforcing structure having a plurality of ribs, the reinforcing structure configured to be coupled to the one or more laminates, where the first end of the elongated beam is configured to be pivotally coupled to a mount. In some armrests, the one or more laminates are configured to be disposed along the elongated beam such that the one or more laminates define a channel and/or an arch extending between the first and second ends.
    Type: Application
    Filed: April 4, 2017
    Publication date: May 23, 2019
    Inventors: Somasekhar Bobba, Rahul Sagare, Raj Kumar, Ashwin Kumar, Kylie Speirs, Peter Zuber, Matthew Buratto, Ranvir Soni, Roy Watson, Andy May