Patents by Inventor Rajasekaran Swaminathan

Rajasekaran Swaminathan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160343680
    Abstract: Methods of forming a microelectronic packaging structure are described. Those methods may include forming a solder paste comprising a sacrificial polymer on a substrate, curing the solder paste below a reflow temperature of the solder to form a solid composite hybrid bump on the conductive pads, forming a molding compound around the solid composite hybrid bump, and reflowing the hybrid bump, wherein the sacrificial polymer is substantially decomposed.
    Type: Application
    Filed: August 1, 2016
    Publication date: November 24, 2016
    Inventors: Rajasekaran SWAMINATHAN, Leonel R. ARANA, Yoshihiro TOMITA, Yosuke KANAOKA
  • Patent number: 9502800
    Abstract: A double-mated edge finger connector that is configured to double the connector density without resorting to a reduction in pitch. A first connector defines a first slot configured to receive and permit horizontal displacement of an edge finger of a second board relative thereto, while a second connector defines a second slot configured to receive and permit horizontal displacement of an edge finger of a first board relative thereto, to thereby establish an electrical connection between the first board and the second board.
    Type: Grant
    Filed: May 5, 2014
    Date of Patent: November 22, 2016
    Assignee: Intel Corporation
    Inventors: Donald T. Tran, Srikant Nekkanty, Rajasekaran Swaminathan
  • Patent number: 9478881
    Abstract: Embodiments of the present disclosure are directed towards a snap connector for socket assembly and associated techniques and configurations. In one embodiment, a socket assembly includes a socket body having a plurality of openings extending from a first side of the socket body to a second side of the socket body to provide an electrical pathway between the first side and the second side, the second side disposed opposite to the first side, wherein a holding portion of an individual opening of the plurality of openings adjacent to the first side of the socket body is shaped to hold a corresponding electrical contact of a die package by elastic force applied by the socket body to the electrical contact when the electrical contact is positioned within the holding portion. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: March 9, 2015
    Date of Patent: October 25, 2016
    Assignee: Intel Corporation
    Inventors: Zhichao Zhang, Gaurav Chawla, Rajasekaran Swaminathan, Kemal Aygun, Li Sun
  • Patent number: 9472519
    Abstract: Methods of forming a microelectronic packaging structure are described. Those methods may include forming a solder paste comprising a sacrificial polymer on a substrate, curing the solder paste below a reflow temperature of the solder to form a solid composite hybrid bump on the conductive pads, forming a molding compound around the solid composite hybrid bump, and reflowing the hybrid bump, wherein the sacrificial polymer is substantially decomposed.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: October 18, 2016
    Assignee: INTEL CORPORATION
    Inventors: Rajasekaran Swaminathan, Leonel R. Arana, Yoshihiro Tomita, Yosuke Kanaoka
  • Patent number: 9461014
    Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include attaching a device to a patch substrate, wherein the assembled device and patch substrate comprise a warpage, attaching the assembled device and patch substrate to an interposer to form a package structure, and then reflowing the package structure at a temperature below about 200 degrees Celsius to form a substantially flat package structure.
    Type: Grant
    Filed: April 14, 2015
    Date of Patent: October 4, 2016
    Assignee: Intel Corporation
    Inventors: Sriram Srinivasan, Ram S. Viswanath, Paul R. Start, Rajen S. Sidhu, Rajasekaran Swaminathan
  • Publication number: 20160268710
    Abstract: Embodiments of the present disclosure are directed towards a snap connector for socket assembly and associated techniques and configurations. In one embodiment, a socket assembly includes a socket body having a plurality of openings extending from a first side of the socket body to a second side of the socket body to provide an electrical pathway between the first side and the second side, the second side disposed opposite to the first side, wherein a holding portion of an individual opening of the plurality of openings adjacent to the first side of the socket body is shaped to hold a corresponding electrical contact of a die package by elastic force applied by the socket body to the electrical contact when the electrical contact is positioned within the holding portion. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: March 9, 2015
    Publication date: September 15, 2016
    Inventors: Zhichao Zhang, Gaurav Chawla, Rajasekaran Swaminathan, Kemal Aygun, Li Sun
  • Publication number: 20160183374
    Abstract: Configurable central processing unit (CPU) package substrates are disclosed. A package substrate is described that includes a processing device interface. The package substrate also includes a memory device electrical interface disposed on the package substrate. The package substrate also includes a removable memory mechanical interface disposed proximately to the memory device electrical interface. The removable memory mechanical interface is to allow a memory device to be easily removed from the package substrate after attachment of the memory device to the package substrate.
    Type: Application
    Filed: December 18, 2014
    Publication date: June 23, 2016
    Inventors: Mani Prakash, Thomas T. Holden, Jeffory L. Smalley, Ram S. Viswanath, Bassam N. Coury, Dimitrios Ziakas, Chong J. Zhao, Jonathan W. Thibado, Gregorio R. Murtagian, Kuang C. Liu, Rajasekaran Swaminathan, Zhichao Zhang, John M. Lynch, David J. Llapitan, Sanka Ganesan, Xiang Li, George Vergis
  • Publication number: 20160172320
    Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein magnetic particles distributed within a solder paste may be used to form a magnetic intermetallic compound interconnect. The intermetallic compound interconnect may be exposed to a magnetic field, which can heat a solder material to a reflow temperature for attachment of microelectronic components comprising the microelectronic packages.
    Type: Application
    Filed: December 10, 2014
    Publication date: June 16, 2016
    Applicant: Intel Corporation
    Inventors: RAJASEKARAN SWAMINATHAN, RAVINDRANATH V. MAHAJAN
  • Publication number: 20160079150
    Abstract: Embodiments of the present disclosure are directed toward techniques and configurations associated with a package load assembly. In one embodiment, a package load assembly may include a frame configured to form a perimeter around a die area of a package substrate having a first surface configured to be coupled with a surface of the package substrate and a second surface disposed opposite to the first surface. The frame may include deformable members disposed on the second surface, which may be configured to be coupled with a base of a heat sink to distribute force applied between the heat sink and the package substrate, via the frame, and may deform under application of the force, which may allow the base of the heat sink to contact a surface of an integrated heat spreader within the die area of the package substrate.
    Type: Application
    Filed: September 12, 2014
    Publication date: March 17, 2016
    Inventors: Gaurav Chawla, Joshua D. Heppner, Vijaykumar Krithivasan, Michael Garcia, Kuang C. Liu, Rajasekaran Swaminathan
  • Patent number: 9265170
    Abstract: Embodiments related to integrated circuit (IC) connectors are described. In some embodiments, an IC assembly may include an IC package substrate, an intermediate member, and a male connector. The IC package substrate may have first signal contacts on a top or bottom surface, and the bottom surface may have second signal contacts for coupling with a socket on a circuit board. The intermediate member may have a first end coupled to the first signal contacts and a second end extending beyond the side surface. The male connector may be disposed at the second end of the intermediate member, and may have signal contacts coupled to the signal contacts of the intermediate member. The male connector may be mateable with a female connector when the female connector is brought into engagement in a direction parallel to the axis of the intermediate member. Other embodiments may be disclosed and/or claimed.
    Type: Grant
    Filed: October 28, 2013
    Date of Patent: February 16, 2016
    Assignee: Intel Corporation
    Inventors: Rajasekaran Swaminathan, Ram S. Viswanath, Sanka Ganesan, Gaurav Chawla, Joshua D. Heppner, Jeffory L. Smalley, Vijaykumar Krithivasan, David J. Llapitan, Neal E. Ulen, Donald T. Tran
  • Publication number: 20160044786
    Abstract: This disclosure relates generally to an electronic package and methods that include an electrically conductive pad, a package insulator layer including a substantially non-conductive material, the package insulator layer being substantially planar, and a via. The via may be formed within the package insulator layer and electrically coupled to the electrically conductive pad. The via may include a conductor extending vertically through at least part of the package insulator layer and having a first end proximate the electrically conductive pad and a second end opposite the first end and a finish layer secured to the second end of the conductor, the finish layer including a gold compound.
    Type: Application
    Filed: August 11, 2014
    Publication date: February 11, 2016
    Inventors: Rajasekaran Swaminathan, Sairam Agraharam, Amruthavalli Pallavi Alur, Ram Viswanath, Wei-Lun Kane Jen
  • Publication number: 20150357736
    Abstract: Embodiments of the present disclosure are directed to an interconnect cable including a edge finger connector, and associated configurations and methods. The edge finger connector may be disposed at a first end of the interconnect cable and may connect the interconnect cable to an edge finger included in or coupled to a package substrate. The package substrate may be included in a processor package assembly, and a processor may be mounted on the substrate. The interconnect cable may include one or more elongate conductors, with contacts directly coupled to respective conductors. A second connector may be disposed at a second end of the interconnect cable, and may couple the interconnect cable to a small form-factor pluggable (SFP) case that is configured to connect the interconnect cable to an SFP cable. Other embodiments may be described and claimed.
    Type: Application
    Filed: August 10, 2015
    Publication date: December 10, 2015
    Inventors: Donald T. Tran, Rajasekaran Swaminathan
  • Publication number: 20150318630
    Abstract: A double-mated edge finger connector that is configured to double the connector density without resorting to a reduction in pitch. A first connector defines a first slot configured to receive and permit horizontal displacement of an edge finger of a second board relative thereto, while a second connector defines a second slot configured to receive and permit horizontal displacement of an edge finger of a first board relative thereto, to thereby establish an electrical connection between the first board and the second board.
    Type: Application
    Filed: May 5, 2014
    Publication date: November 5, 2015
    Inventors: Donald T. Tran, Srikant Nekkanty, Rajasekaran Swaminathan
  • Patent number: 9118151
    Abstract: Embodiments of the present disclosure are directed to an interconnect cable including a edge finger connector, and associated configurations and methods. The edge finger connector may be disposed at a first end of the interconnect cable and may connect the interconnect cable to an edge finger included in or coupled to a package substrate. The package substrate may be included in a processor package assembly, and a processor may be mounted on the substrate. The interconnect cable may include one or more elongate conductors, with contacts directly coupled to respective conductors. A second connector may be disposed at a second end of the interconnect cable, and may couple the interconnect cable to a small form-factor pluggable (SFP) case that is configured to connect the interconnect cable to an SFP cable. Other embodiments may be described and claimed.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: August 25, 2015
    Assignee: Intel Corporation
    Inventors: Donald T. Tran, Rajasekaran Swaminathan
  • Publication number: 20150221609
    Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include attaching a device to a patch substrate, wherein the assembled device and patch substrate comprise a warpage, attaching the assembled device and patch substrate to an interposer to form a package structure, and then reflowing the package structure at a temperature below about 200 degrees Celsius to form a substantially flat package structure.
    Type: Application
    Filed: April 14, 2015
    Publication date: August 6, 2015
    Applicant: Intel Corporation
    Inventors: Sriram Srinivasan, Ram S. Viswanath, Paul R. Start, Rajen S. Sidhu, Rajasekaran Swaminathan
  • Publication number: 20150194401
    Abstract: Methods of forming a microelectronic packaging structure are described. Those methods may include forming a solder paste comprising a sacrificial polymer on a substrate, curing the solder paste below a reflow temperature of the solder to form a solid composite hybrid bump on the conductive pads, forming a molding compound around the solid composite hybrid bump, and reflowing the hybrid bump, wherein the sacrificial polymer is substantially decomposed.
    Type: Application
    Filed: March 13, 2015
    Publication date: July 9, 2015
    Inventors: Rajasekaran SWAMINATHAN, Leonel R. ARANA, Yoshihiro TOMITA, Yosuke KANAOKA
  • Patent number: 9064971
    Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include attaching a device to a patch substrate, wherein the assembled device and patch substrate comprise a warpage, attaching the assembled device and patch substrate to an interposer to form a package structure, and then reflowing the package structure at a temperature below about 200 degrees Celsius to form a substantially flat package structure.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: June 23, 2015
    Assignee: Intel Corporation
    Inventors: Sriram Srinivasan, Ram S. Viswanath, Paul R. Start, Rajen S. Sidhu, Rajasekaran Swaminathan
  • Publication number: 20150118870
    Abstract: Embodiments related to integrated circuit (IC) connectors are described. In some embodiments, an IC assembly may include an IC package substrate, an intermediate member, and a male connector. The IC package substrate may have first signal contacts on a top or bottom surface, and the bottom surface may have second signal contacts for coupling with a socket on a circuit board. The intermediate member may have a first end coupled to the first signal contacts and a second end extending beyond the side surface. The male connector may be disposed at the second end of the intermediate member, and may have signal contacts coupled to the signal contacts of the intermediate member. The male connector may be mateable with a female connector when the female connector is brought into engagement in a direction parallel to the axis of the intermediate member. Other embodiments may be disclosed and/or claimed.
    Type: Application
    Filed: October 28, 2013
    Publication date: April 30, 2015
    Inventors: Rajasekaran Swaminathan, Ram S. Viswanath, Sanka Ganesan, Gaurav Chawla, Joshua D. Heppner, Jeffory L. Smalley, Vijaykumar Krithivasan, David J. Llapitan, Neal E. Ulen, Donald T. Tran
  • Patent number: 9010618
    Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein components of the microelectronic packages may have magnetic attachment structures comprising a magnetic component and a metal component. The magnetic attachment structure may be exposed to a magnetic field, which, through the vibration of the magnetic component, can heat the magnetic attachment structure, and which when placed in contact with a solder material can reflow the solder material and attach microelectronic components of the microelectronic package.
    Type: Grant
    Filed: April 2, 2013
    Date of Patent: April 21, 2015
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Rajasekaran Swaminathan, Ting Zhong
  • Patent number: 9006887
    Abstract: Methods of forming a microelectronic packaging structure are described. Those methods may include forming a solder paste comprising a sacrificial polymer on a substrate, curing the solder paste below a reflow temperature of the solder to form a solid composite hybrid bump on the conductive pads, forming a molding compound around the solid composite hybrid bump, and reflowing the hybrid bump, wherein the sacrificial polymer is substantially decomposed.
    Type: Grant
    Filed: March 4, 2009
    Date of Patent: April 14, 2015
    Assignee: Intel Corporation
    Inventors: Rajasekaran Swaminathan, Leonel Arana, Yoshihiro Tomita, Yosuke Kanaoka