Patents by Inventor Rajasekaran Swaminathan

Rajasekaran Swaminathan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8939347
    Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein magnetic particles distributed within a solder paste may be used to form a magnetic intermetallic compound interconnect. The intermetallic compound interconnect may be exposed to a magnetic field, which can heat a solder material to a reflow temperature for attachment of microelectronic components comprising the microelectronic packages.
    Type: Grant
    Filed: April 28, 2010
    Date of Patent: January 27, 2015
    Assignee: Intel Corporation
    Inventors: Rajasekaran Swaminathan, Ravindranath V. Mahajan
  • Publication number: 20140322932
    Abstract: Embodiments of the present disclosure are directed to an interconnect cable including a edge finger connector, and associated configurations and methods. The edge finger connector may be disposed at a first end of the interconnect cable and may connect the interconnect cable to an edge finger included in or coupled to a package substrate. The package substrate may be included in a processor package assembly, and a processor may be mounted on the substrate. The interconnect cable may include one or more elongate conductors, with contacts directly coupled to respective conductors. A second connector may be disposed at a second end of the interconnect cable, and may couple the interconnect cable to a small form-factor pluggable (SFP) case that is configured to connect the interconnect cable to an SFP cable. Other embodiments may be described and claimed.
    Type: Application
    Filed: April 25, 2013
    Publication date: October 30, 2014
    Inventors: Donald T. Tran, Rajasekaran Swaminathan
  • Publication number: 20140205851
    Abstract: An interconnect structure for electrically joining two surfaces includes magnetic attachment structures and an anisotropic conductive adhesive (ACA). Magnetic attachment structures on a first surface are magnetically attracted to magnetic attachment structures on a second surface. Opposing magnetic attachment structures are joined via an ACA, which conducts electricity when compressed, and is electrically insulating when not compressed. The magnetic attraction between opposing magnetic attachment structures generates a sufficient force to maintain compression of the intervening ACA in order to sustain a desired level of electrical conductivity between the first surface and second surface. A method for joining two surfaces using the interconnect structure is disclosed. Additionally, a magnetic anisotropic conductive adhesive having magnetic conductive particles dispersed therein is disclosed.
    Type: Application
    Filed: January 23, 2013
    Publication date: July 24, 2014
    Inventors: Ravindranath V. MAHAJAN, Aleksandar ALEKSOV, Debendra MALLIK, Ian A. YOUNG, Rajasekaran SWAMINATHAN, Sairam AGRAHARAM, John S. GUZEK
  • Publication number: 20140175644
    Abstract: Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods and structures may include attaching a device to a patch substrate, wherein the assembled device and patch substrate comprise a warpage, attaching the assembled device and patch substrate to an interposer to form a package structure, and then reflowing the package structure at a temperature below about 200 degrees Celsius to form a substantially flat package structure.
    Type: Application
    Filed: December 20, 2012
    Publication date: June 26, 2014
    Inventors: Sriram Srinivasan, Ram S. Viswanath, Paul R. Start, Rajen S. Sidhu, Rajasekaran Swaminathan
  • Patent number: 8609532
    Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein microelectronic components of the microelectronic packages may have sintered conductive vias comprising sintered metal and magnetic particles.
    Type: Grant
    Filed: May 26, 2010
    Date of Patent: December 17, 2013
    Assignee: Intel Corporation
    Inventors: Rajasekaran Swaminathan, Ravindranath V. Mahajan
  • Publication number: 20130292838
    Abstract: Embodiments of the invention relate to a package-on-package (PoP) assembly comprising a top device package and a bottom device package interconnected by way of an electrically interconnected planar stiffener. Embodiments of the invention include a first semiconductor package having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads; a second semiconductor package having a plurality of SLI pads on the bottom side of the package; and a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener electrically connected to the SLI pads of the second package, and a second plurality of planar contact pads electrically connected to the inter-package contact pads of the first package.
    Type: Application
    Filed: July 10, 2013
    Publication date: November 7, 2013
    Inventors: Sanka Ganesan, Yosuke Kanaoka, Ram S. Viswanath, Rajasekaran Swaminathan, Robert M. Nickerson, Leonel R. Arana, John S. Guzek, Yoshihiro Tomita
  • Patent number: 8569108
    Abstract: A coating for a microelectronic device comprises a polymer film (131) containing a filler material (232). The polymer film has a thermal conductivity greater than 3 W/m·K and a thickness (133) that does not exceed 10 micrometers. The polymer film may be combined with a dicing tape (310) to form a treatment (300) that simplifies a manufacturing process for a microelectronic package (100) and may be used in order to manage a thermal profile of the microelectronic device.
    Type: Grant
    Filed: September 13, 2012
    Date of Patent: October 29, 2013
    Assignee: Intel Corporation
    Inventors: Dingying Xu, Leonel R. Arana, Nachiket R. Raravikar, Mohit Mamodia, Rajasekaran Swaminathan, Rahul Manepalli
  • Patent number: 8550327
    Abstract: A clad solder thermal interface material is described. In one example the material has a a first layer of solder having a melting temperature lower than a temperature of a particular solder reflow furnace, a second layer of solder clad to the first layer of solder, the second layer having a melting temperature higher than the temperature of the solder reflow furnace, and a third layer of solder clad to the second layer of solder opposite the first layer, the third layer having a melting temperature lower than the temperature of the solder reflow furnace.
    Type: Grant
    Filed: February 3, 2011
    Date of Patent: October 8, 2013
    Assignee: Intel Corporation
    Inventors: Carl L. Deppisch, Rajasekaran Swaminathan
  • Publication number: 20130224444
    Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein components of the microelectronic packages may have magnetic attachment structures comprising a magnetic component and a metal component. The magnetic attachment structure may be exposed to a magnetic field, which, through the vibration of the magnetic component, can heat the magnetic attachment structure, and which when placed in contact with a solder material can reflow the solder material and attach microelectronic components of the microelectronic package.
    Type: Application
    Filed: April 2, 2013
    Publication date: August 29, 2013
    Inventors: ALEKSANDAR ALEKSOV, RAJASEKARAN SWAMINATHAN, TING ZHONG
  • Patent number: 8513792
    Abstract: Embodiments of the invention relate to a package-on-package (PoP) assembly comprising a top device package and a bottom device package interconnected by way of an electrically interconnected planar stiffener. Embodiments of the invention include a first semiconductor package having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads; a second semiconductor package having a plurality of SLI pads on the bottom side of the package; and a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener electrically connected to the SLI pads of the second package, and a second plurality of planar contact pads electrically connected to the inter-package contact pads of the first package.
    Type: Grant
    Filed: April 10, 2009
    Date of Patent: August 20, 2013
    Assignee: Intel Corporation
    Inventors: Sanka Ganesan, Yosuke Kanaoka, Ram S. Viswanath, Rajasekaran Swaminathan, Robert M. Nickerson, Leonel R. Arana, John S. Guzek, Yoshihiro Tomita
  • Patent number: 8434668
    Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein components of the microelectronic packages may have magnetic attachment structures comprising a magnetic component and a metal component. The magnetic attachment structure may be exposed to a magnetic field, which, through the vibration of the magnetic component, can heat the magnetic attachment structure, and which when placed in contact with a solder material can reflow the solder material and attach microelectronic components of the microelectronic package.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: May 7, 2013
    Assignee: Intel Corporation
    Inventors: Aleksandar Aleksov, Rajasekaran Swaminathan, Ting Zhong
  • Patent number: 8377550
    Abstract: Methods and associated structures of forming underfill material are described. Those methods may include applying an underfill to an interconnect structure comprising residue from a no clean flux, wherein the underfill comprises at least one of a functionalized nanofiller and a micron-sized filler.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: February 19, 2013
    Assignee: Intel Corporation
    Inventors: Rajasekaran Swaminathan, Hong Dong, Sandeep Razdan, Nisha Ananthakrisnan, Rahul Manepalli
  • Publication number: 20130017650
    Abstract: A coating for a microelectronic device comprises a polymer film (131) containing a filler material (232). The polymer film has a thermal conductivity greater than 3 W/m·K and a thickness (133) that does not exceed 10 micrometers. The polymer film may be combined with a dicing tape (310) to form a treatment (300) that simplifies a manufacturing process for a microelectronic package (100) and may be used in order to manage a thermal profile of the microelectronic device.
    Type: Application
    Filed: September 13, 2012
    Publication date: January 17, 2013
    Inventors: Dingying Xu, Leonel R. Arana, Nachiket R. Raravikar, Mohit Mamodia, Rajasekaran Swaminathan, Rahul Manepalli
  • Patent number: 8313958
    Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein microelectronic devices of the microelectronic packages may have magnetic attachment structures comprising a magnetic material formed on an attachment structure. The microelectronic device may be aligned on a substrate with a magnetic field and then held in place therewith while being attached to the substrate. The microelectronic device may also be aligned with an alignment plate which magnetically aligns and holds the component in place while being packaged.
    Type: Grant
    Filed: May 12, 2010
    Date of Patent: November 20, 2012
    Assignee: Intel Corporation
    Inventors: Rajasekaran Swaminathan, Ravindranath Mahajan, John S. Guzek
  • Patent number: 8287996
    Abstract: A coating for a microelectronic device comprises a polymer film (131) containing a filler material (232). The polymer film has a thermal conductivity greater than 3 W/m·K and a thickness (133) that does not exceed 10 micrometers. The polymer film may be combined with a dicing tape (310) to form a treatment (300) that simplifies a manufacturing process for a microelectronic package (100) and may be used in order to manage a thermal profile of the microelectronic device.
    Type: Grant
    Filed: December 21, 2009
    Date of Patent: October 16, 2012
    Assignee: Intel Corporation
    Inventors: Dingying Xu, Leonel R. Arana, Nachiket R. Raravikar, Mohit Mamodia, Rajasekaran Swaminathan, Rahul Manepalli
  • Patent number: 8222730
    Abstract: A semiconductor package is described. The semiconductor package includes a substrate and an integrated heat spreader disposed above and coupled with the substrate. A cavity is disposed between the substrate and the integrated heat spreader. A semiconductor die is disposed above the substrate and in the cavity. An array of first-level solder joints is disposed between the substrate and the semiconductor die. A layer of magnetic particle-based composite material is also disposed in the cavity.
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: July 17, 2012
    Assignee: Intel Corporation
    Inventor: Rajasekaran Swaminathan
  • Publication number: 20110291276
    Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein microelectronic components of the microelectronic packages may have sintered conductive vias comprising sintered metal and magnetic particles.
    Type: Application
    Filed: May 26, 2010
    Publication date: December 1, 2011
    Inventors: Rajasekaran Swaminathan, Ravindranath V. Mahajan
  • Publication number: 20110281375
    Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein microelectronic devices of the microelectronic packages may have magnetic attachment structures comprising a magnetic material formed on an attachment structure. The microelectronic device may be aligned on a substrate with a magnetic field and then held in place therewith while being attached to the substrate. The microelectronic device may also be aligned with an alignment plate which magnetically aligns and holds the component in place while being packaged.
    Type: Application
    Filed: May 12, 2010
    Publication date: November 17, 2011
    Inventors: Rajasekaran Swaminathan, Ravindranath Ravi Mahajan, John S. Guzek
  • Publication number: 20110278044
    Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein components of the microelectronic packages may have magnetic attachment structures comprising a magnetic component and a metal component. The magnetic attachment structure may be exposed to a magnetic field, which, through the vibration of the magnetic component, can heat the magnetic attachment structure, and which when placed in contact with a solder material can reflow the solder material and attach microelectronic components of the microelectronic package.
    Type: Application
    Filed: May 12, 2010
    Publication date: November 17, 2011
    Inventors: Aleksandar Aleksov, Rajasekaran Swaminathan, Ting Zhong
  • Publication number: 20110278351
    Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein a magnetic particle attachment material comprising magnetic particles distributed within a carrier material may be used to achieve attachment between microelectronic components. The magnetic particle attachment material may be exposed to a magnetic field, which, through the vibration of the magnetic particles within the magnetic particle attachment material, can heat a solder material to a reflow temperature for attaching microelectronic components of the microelectronic packages.
    Type: Application
    Filed: May 11, 2010
    Publication date: November 17, 2011
    Inventors: Aleksandar Aleksov, Rajasekaran Swaminathan, Nachiket Raravikar