Patents by Inventor Rajasekaran Swaminathan

Rajasekaran Swaminathan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110266030
    Abstract: The present disclosure relates to the field of fabricating microelectronic packages, wherein magnetic particles distributed within a solder paste may be used to form a magnetic intermetallic compound interconnect. The intermetallic compound interconnect may be exposed to a magnetic field, which can heat a solder material to a reflow temperature for attachment of microelectronic components comprising the microelectronic packages.
    Type: Application
    Filed: April 28, 2010
    Publication date: November 3, 2011
    Inventors: Rajasekaran Swaminathan, Ravindranath V. Mahajan
  • Publication number: 20110159228
    Abstract: Methods and associated structures of forming underfill material are described. Those methods may include applying an underfill to an interconnect structure comprising residue from a no clean flux, wherein the underfill comprises at least one of a functionalized nanofiller and a micron-sized filler.
    Type: Application
    Filed: December 29, 2009
    Publication date: June 30, 2011
    Inventors: Rajasekaran Swaminathan, Hong Dong, Sandeep Razdan, Nisha Ananthakrishana, Rahul Manepalli
  • Publication number: 20110147914
    Abstract: A clad solder thermal interface material is described. In one example the material has a a first layer of solder having a melting temperature lower than a temperature of a particular solder reflow furnace, a second layer of solder clad to the first layer of solder, the second layer having a melting temperature higher than the temperature of the solder reflow furnace, and a third layer of solder clad to the second layer of solder opposite the first layer, the third layer having a melting temperature lower than the temperature of the solder reflow furnace.
    Type: Application
    Filed: February 3, 2011
    Publication date: June 23, 2011
    Inventors: Carl L. Deppisch, Rajasekaran Swaminathan
  • Publication number: 20110151624
    Abstract: A coating for a microelectronic device comprises a polymer film (131) containing a filler material (232). The polymer film has a thermal conductivity greater than 3 W/m·K and a thickness (133) that does not exceed 10 micrometers. The polymer film may be combined with a dicing tape (310) to form a treatment (300) that simplifies a manufacturing process for a microelectronic package (100) and may be used in order to manage a thermal profile of the microelectronic device.
    Type: Application
    Filed: December 21, 2009
    Publication date: June 23, 2011
    Inventors: Dingying Xu, Leonel R. Arana, Nachiket R. Raravikar, Mohit Mamodia, Rajasekaran Swaminathan, Rahul Manepalli
  • Publication number: 20110147438
    Abstract: A clad solder thermal interface material is described. In one example the material has a first layer of solder, a second layer of solder clad to the first layer of solder, the second layer having a melting temperature lower than the melting temperature of the first layer, and a third layer of solder clad to the first layer of solder opposite the second layer, the third layer having a melting temperature lower than the melting temperature of the first layer.
    Type: Application
    Filed: December 23, 2009
    Publication date: June 23, 2011
    Inventors: Carl Ludwig Deppisch, Rajasekaran Swaminathan
  • Publication number: 20110127663
    Abstract: A semiconductor package is described. The semiconductor package includes a substrate and an integrated heat spreader disposed above and coupled with the substrate. A cavity is disposed between the substrate and the integrated heat spreader. A semiconductor die is disposed above the substrate and in the cavity. An array of first-level solder joints is disposed between the substrate and the semiconductor die. A layer of magnetic particle-based composite material is also disposed in the cavity.
    Type: Application
    Filed: January 31, 2011
    Publication date: June 2, 2011
    Inventor: Rajasekaran Swaminathan
  • Patent number: 7906376
    Abstract: A semiconductor package is described. The semiconductor package includes a substrate and an integrated heat spreader disposed above and coupled with the substrate. A cavity is disposed between the substrate and the integrated heat spreader. A semiconductor die is disposed above the substrate and in the cavity. An array of first-level solder joints is disposed between the substrate and the semiconductor die. A layer of magnetic particle-based composite material is also disposed in the cavity.
    Type: Grant
    Filed: June 30, 2008
    Date of Patent: March 15, 2011
    Assignee: Intel Corporation
    Inventor: Rajasekaran Swaminathan
  • Patent number: 7902060
    Abstract: Electronic devices and methods for fabricating electronic devices are described. One method includes providing a first body with a plurality of composite bumps thereon, the composite bumps comprising a solder and magnetic particles. The method also includes applying a magnetic field to the magnetic particles to generate sufficient heat to melt the solder and form molten bump regions containing the magnetic particles therein. The method also includes coupling a second body to the first body through the molten bump regions, and cooling the molten bump regions to form solidified composite bumps coupling the second body to the first body. Other embodiments are described and claimed.
    Type: Grant
    Filed: December 23, 2008
    Date of Patent: March 8, 2011
    Assignee: Intel Corporation
    Inventor: Rajasekaran Swaminathan
  • Publication number: 20100258927
    Abstract: Embodiments of the invention relate to a package-on-package (PoP) assembly comprising a top device package and a bottom device package interconnected by way of an electrically interconnected planar stiffener. Embodiments of the invention include a first semiconductor package having a plurality of inter-package contact pads and a plurality of second level interconnect (SLI) pads; a second semiconductor package having a plurality of SLI pads on the bottom side of the package; and a planar stiffener having a first plurality of planar contact pads on the top side of the stiffener electrically connected to the SLI pads of the second package, and a second plurality of planar contact pads electrically connected to the inter-package contact pads of the first package.
    Type: Application
    Filed: April 10, 2009
    Publication date: October 14, 2010
    Inventors: Sanka Ganesan, Yosuke Kanaoka, Ram S. Viswanath, Rajasekaran Swaminathan, Robert M. Nickerson, Leonel R. Arane, John S. Guzek, Yoshihiro Tomita
  • Publication number: 20100224993
    Abstract: Methods of forming a microelectronic packaging structure are described. Those methods may include forming a solder paste comprising a sacrificial polymer on a substrate, curing the solder paste below a reflow temperature of the solder to form a solid composite hybrid bump on the conductive pads, forming a molding compound around the solid composite hybrid bump, and reflowing the hybrid bump, wherein the sacrificial polymer is substantially decomposed.
    Type: Application
    Filed: March 4, 2009
    Publication date: September 9, 2010
    Inventors: Rajasekaran Swaminathan, Leonel Arana, Yoshihiro Tomita, Yosuke Kanaoka
  • Publication number: 20100159692
    Abstract: Electronic devices and methods for fabricating electronic devices are described. One method includes providing a first body with a plurality of composite bumps thereon, the composite bumps comprising a solder and magnetic particles. The method also includes applying a magnetic field to the magnetic particles to generate sufficient heat to melt the solder and form molten bump regions containing the magnetic particles therein. The method also includes coupling a second body to the first body through the molten bump regions, and cooling the molten bump regions to form solidified composite bumps coupling the second body to the first body. Other embodiments are described and claimed.
    Type: Application
    Filed: December 23, 2008
    Publication date: June 24, 2010
    Inventor: Rajasekaran SWAMINATHAN
  • Publication number: 20090321923
    Abstract: A semiconductor package is described. The semiconductor package includes a substrate and an integrated heat spreader disposed above and coupled with the substrate. A cavity is disposed between the substrate and the integrated heat spreader. A semiconductor die is disposed above the substrate and in the cavity. An array of first-level solder joints is disposed between the substrate and the semiconductor die. A layer of magnetic particle-based composite material is also disposed in the cavity.
    Type: Application
    Filed: June 30, 2008
    Publication date: December 31, 2009
    Inventor: Rajasekaran Swaminathan