Abstract: A method for forming a stud bumped semiconductor die is disclosed. The method includes forming a ball at the tip of a coated wire passing through a hole in a capillary, where the coated wire has a core and an oxidation-resistant coating. The formed ball is pressed to the conductive region on the semiconductor die. The coated wire is cut, thereby leaving a conductive stud bump on the conductive region, where the conductive stud bump includes an inner conductive portion and an outer oxidation-resistant layer.

Abstract: A semiconductor device that does not include a molded body or package. The semiconductor device includes a substrate and a die coupled to the substrate. The die is coupled to the substrate such that the source and gate regions of the die, assuming a MOSFET-type device, are coupled to the substrate. Solder balls are provided adjacent to the die such that when the semiconductor device is coupled to a printed circuit board, the exposed surface of the serves as the drain connections while the solder balls serve as the source and gate connections.

Abstract: A structure and method of manufacture for an improved multi-chip semiconductor package that reduces package resistance to a negligible level, and offers superior thermal performance. Housing of multiple dies is facilitated by providing electrically isolated lead frames that are separated from a common base carrier by a non-conductive layer of laminating material. A silicon die is attached inside a cavity formed in each lead frame. Direct connection of the active surface of the silicon die to the printed circuit board is then made by an array of solder bumps that is distributed across the surface of each die as well as the edges of the lead frame adjacent to each die.

Abstract: A method for processing a semiconductor substrate is disclosed. The method includes providing a mask having an aperture on a semiconductor substrate having a conductive region. An aperture in the mask is disposed over the conductive region. A pre-formed conductive column is placed in the aperture and is bonded to the conductive region.

Abstract: A multichip module is disclosed. In one embodiment, the multichip module includes a substrate having a first side and a second side, the first side being opposite to the first side. A driver chip is at the first side of the substrate. A semiconductor die comprising a vertical transistor is at the second side of the substrate. The driver chip and the semiconductor die are in electrical communication through the substrate.

Abstract: A bumped wafer for use in making a chip device. The bumped wafer includes two titanium layers sputtered alternatingly with two copper layers over a non-passivated die. The bumped wafer further includes under bump material under solder bumps contained thereon.

Abstract: A method for forming a semiconductor die package is disclosed. In one embodiment, the method includes forming a semiconductor die comprising a semiconductor device. A plurality of copper bumps is formed on the semiconductor die using a plating process. An adhesion layer is formed on each of the copper bumps, and a noble metal layer is formed on each of the copper bumps.

Abstract: A chip device that includes a leadframe, a die and a mold compound. The backside of the die is metallized and exposed through a window defined within a mold compound that encapsulates the die when it is coupled to the leadframe. Leads on the leadframe are coupled to source and gate terminals on the die while the metallized backside of the die serves as the drain terminals.

Abstract: A chip device that includes a leadframe, a die and a mold compound. The backside of the die is metallized and exposed through a window defined within a mold compound that encapsulates the die when it is coupled to the leadframe. Leads on the leadframe are coupled to source and gate terminals on the die while the metallized backside of the die serves as the drain terminals.

Abstract: A semiconductor die package is disclosed. In one embodiment, the semiconductor die package has a substrate. It includes (i) a lead frame structure including a die attach region with a die attach surface and a lead having a lead surface, and (ii) a molding material. The die attach surface and the lead surface are exposed through the molding material. A semiconductor die is on the die attach region, and the semiconductor die is electrically coupled to the lead.

Abstract: A structure and method of manufacture for an improved multi-chip semiconductor package that reduces package resistance to a negligible level, and offers superior thermal performance. Housing of multiple dies is facilitated by providing electrically isolated lead frames that are separated from a common base carrier by a non-conductive layer of laminating material. A silicon die is attached inside a cavity formed in each lead frame. Direct connection of the active surface of the silicon die to the printed circuit board is then made by an array of solder bumps that is distributed across the surface of each die as well as the edges of the lead frame adjacent to each die.

Abstract: A method for processing a semiconductor substrate is disclosed. The method includes providing a mask having an aperture on a semiconductor substrate having a conductive region. An aperture in the mask is disposed over the conductive region. A pre-formed conductive column is placed in the aperture and is bonded to the conductive region.

Abstract: A chip device that includes a leadframe that has a die attach cavity. The memory device further includes a die that is placed within the die attach cavity. The die attach cavity is substantially the same thickness as the die. The die is positioned within the cavity and is attached therein with a standard die attachment procedure.

Abstract: A semiconductor die package is disclosed. The die package includes a semiconductor die having a first side and a second side, a vertical transistor, and a bond pad at the first side. A passivation layer having a first aperture is on the first side, and the bond pad is exposed through the first aperture. An underbump metallurgy layer is on and in direct contact with the passivation layer. The underbump metallurgy layer is within the first aperture and contacts the bond pad. A dielectric layer comprising a second aperture is on and in direct contact with the underbump metallurgy layer. A solder structure is on the underbump metallurgy layer and is within the second aperture of the dielectric layer.

Abstract: An optocoupler package is disclosed. The optocoupler package comprises a carrier substrate and a plurality of conductive regions on the carrier substrate. An optoelectronic device, an optically transmissive medium, and a plurality of conductive structures can be on the carrier substrate.

Abstract: A structure and method of manufacture for an improved multi-chip semiconductor package that reduces package resistance to a negligible level, and offers superior thermal performance. Housing of multiple dies is facilitated by providing electrically isolated lead frames that are separated from a common base carrier by a non-conductive layer of laminating material. A silicon die is attached inside a cavity formed in each lead frame. Direct connection of the active surface of the silicon die to the printed circuit board is then made by an array of solder bumps that is distributed across the surface of each die as well as the edges of the lead frame adjacent to each die.

Abstract: A method for forming a semiconductor die package is disclosed. In one embodiment, the method includes forming a semiconductor die comprising a semiconductor device. A plurality of copper bumps is formed on the semiconductor die using a plating process. An adhesion layer is formed on each of the copper bumps, and a noble metal layer is formed on each of the copper bumps.

Abstract: A structure and method of manufacture for an improved multi-chip semiconductor package that reduces package resistance to a negligible level, and offers superior thermal performance. Housing of multiple dies is facilitated by providing electrically isolated lead frames that are separated from a common base carrier by a non-conductive layer of laminating material. A silicon die is attached inside a cavity formed in each lead frame. Direct connection of the active surface of the silicon die to the printed circuit board is then made by an array of solder bumps that is distributed across the surface of each die as well as the edges of the lead frame adjacent to each die.

Abstract: A structure and method of manufacture for an improved multi-chip semiconductor package that reduces package resistance to a negligible level, and offers superior thermal performance. Housing of multiple dies is facilitated by providing electrically isolated lead frames that are separated from a common base carrier by a non-conductive layer of laminating material. A silicon die is attached inside a cavity formed in each lead frame. Direct connection of the active surface of the silicon die to the printed circuit board is then made by an array of solder bumps that is distributed across the surface of each die as well as the edges of the lead frame adjacent to each die.

Abstract: A semiconductor die package is disclosed. In one embodiment, the package includes a semiconductor die comprising a vertical power transistor. A source electrode and a gate contact region are at the first surface of the semiconductor die. A drain electrode is at the second surface of the semiconductor die. A base member is proximate to the second surface of the semiconductor die and is distal to the first surface of the semiconductor die and a cover disposed over the first surface of the semiconductor die. The cover is coupled to the base member and is adapted to transfer beat away from the semiconductor die.