Abstract: Asynchronous circuit elements are described. Asynchronous circuit elements include a consensus element (c-element), completion tree, and validity tree. The c-element is implemented using adjustable threshold based multi-input capacitive circuitries. The completion tree comprises a plurality of c-elements organized in a tree formation. The validity tree comprises OR gates followed by c-elements. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the various asynchronous circuitries.

Abstract: A memory device includes a first electrode comprising a first conductive nonlinear polar material, where the first conductive nonlinear polar material comprises a first average grain length. The memory device further includes a dielectric layer comprising a perovskite material on the first electrode, where the perovskite material includes a second average grain length. A second electrode comprising a second conductive nonlinear polar material is on the dielectric layer, where the second conductive nonlinear polar material includes a third grain average length that is less than or equal to the first average grain length or the second average grain length.

Abstract: Certain aspects of the present disclosure provide techniques for wireless communications by a user equipment (UE). The UE receives a configuration for at least one machine learning function name (MLFN). The UE receives machine learning (ML) data associated with the at least one MLFN. The UE uses the ML data as an input for at least one of: operation or training of an ML model associated with the at least one MLFN.

Abstract: Aspects described herein relate to receiving, from a network node, a list of supported models or model structures (MS) identifiers (IDs) per machine learning function name (MLFN) or machine learning feature (MLF) at the network node, updating a capability at the UE to an updated capability based on the list of supported models or MS IDs per MLFN or MLF at the network node, and downloading, at the UE and from a model repository, one or more models or MSs per MLFN or MLF based on the updated capability and available resources at the UE. Other aspects relate to transmitting the list of supported models or MS IDs and configuring use of a model or MS ID for a particular MLFN or MLF.

Abstract: Asynchronous circuit elements are described. Asynchronous circuit elements include a consensus element (c-element), completion tree, and validity tree. The c-element is implemented using adjustable threshold based multi-input capacitive circuitries. The completion tree comprises a plurality of c-elements organized in a tree formation. The validity tree comprises OR gates followed by c-elements. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the various asynchronous circuitries.

Abstract: A packaging technology to improve performance of an AI processing system resulting in an ultra-high bandwidth system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die can be a first logic die (e.g., a compute chip, CPU, GPU, etc.) while the second die can be a compute chiplet comprising ferroelectric or paraelectric logic. Both dies can include ferroelectric or paraelectric logic. The ferroelectric/paraelectric logic may include AND gates, OR gates, complex gates, majority, minority, and/or threshold gates, sequential logic, etc. The IC package can be in a 3D or 2.5D configuration that implements logic-on-logic stacking configuration. The 3D or 2.5D packaging configurations have chips or chiplets designed to have time distributed or spatially distributed processing. The logic of chips or chiplets is segregated so that one chip in a 3D or 2.5D stacking arrangement is hot at a time.

Abstract: A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.

Abstract: Routing of a traffic in a fabric network may be provided. A first traffic may be received at a first node. It may be determined that the first traffic is coming from a provider virtual network. In response to determining that the first traffic is coming from the provider virtual network, it may be determined that a first subnet associated with the first traffic is associated with a subscriber virtual network. In response to determining that the first subnet associated with the first traffic is associated with the subscriber virtual network, a first virtual network associated with the first traffic may be changed to the subscriber virtual network. A lookup for the first traffic may be changed to a first virtual routing and forwarding of the subscriber virtual network.

Abstract: Methods, devices, and mechanisms for detecting and reporting successful secondary node and/or primary secondary cell group cell (PScell) changes are provided. In one example, a method of wireless communication performed by a first network unit comprises: transmitting, to a second network unit, an indication of a primary secondary cell group cell (PScell) change associated with a user equipment (UE); transmitting, based on the indication, a SPC configuration; and receiving a SPC report, wherein the SPC report is based on the SPC configuration and SPC information associated with the UE.

Abstract: Described is a packaging technology to improve performance of an AI processing system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die includes memory and the second die includes computational logic. The first die comprises a ferroelectric RAM (FeRAM) having bit-cells. Each bit-cell comprises an access transistor and a capacitor including ferroelectric material. The access transistor is coupled to the ferroelectric material. The FeRAM can be FeDRAM or FeSRAM. The memory of the first die may store input data and weight factors. The computational logic of the second die is coupled to the memory of the first die. The second die is an inference die that applies fixed weights for a trained model to an input data to generate an output. In one example, the second die is a training die that enables learning of the weights.

Abstract: A user equipment (UE) disconnects from next generation radio access network (NG-RAN) base station (BS) and receives, from the NG-RAN BS, a fallback indication. The UE then attempts to connect to an evolved-universal mobile telecommunications system terrestrial radio access network (E-UTRAN) BS. The UE determines that communication with the E-UTRAN BS was not established and identifies an alternate BS. After establishing communication with the alternate BS, the UE generates and transmits a report to the alternate BS including the fallback indication and information relating to the failed connection attempt with the E-UTRAN BS. The report is then conveyed to the NG-RAN BS for optimization of future fallback procedures.

Abstract: A memory device includes a first electrode comprising a first conductive nonlinear polar material, where the first conductive nonlinear polar material comprises a first average grain length. The memory device further includes a dielectric layer comprising a perovskite material on the first electrode, where the perovskite material includes a second average grain length. A second electrode comprising a second conductive nonlinear polar material is on the dielectric layer, where the second conductive nonlinear polar material includes a third grain average length that is less than or equal to the first average grain length or the second average grain length.

Abstract: Methods, systems, and devices for wireless communication are described. A first wireless device may establish a communication session with a second wireless device using a neighbor awareness networking (NAN) radio access technology (RAT). The first wireless device may transmit a first indication that the first wireless device is capable of using a secured ranging protocol. The first wireless device may receive a second indication that the second wireless device is also capable of using the secured ranging protocol. The first wireless device may determine one or more setup parameters to use for a ranging procedure between the first wireless device and the second wireless device based on the first indication and the second indication. Accordingly, the first wireless device may obtain a measurement report after using the secured ranging protocol to perform the ranging procedure in accordance with the one or more setup parameters.

Abstract: A multiplier cell is derived from a 1-bit full adder and an AND gate. The 1-bit full adder is derived from majority and/or minority gates. The majority and/or minority gates include non-linear polar material (e.g., ferroelectric or paraelectric material). A reset mechanism is provided to reset the nodes across the non-linear polar material. The multiplier cell is a hybrid of majority and/or minority gates and complementary metal oxide semiconductor (CMOS) based inverters and/or buffers. The adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.

Abstract: A computer-implemented system provides a chatbot communications network between a plurality of system participating users including merchants and clients. The system comprises a system controller with a memory. A user device communicates with the system controller and comprises an input/output interface for inputting commands to the system controller and for outputting information from the system controller. The system controller creates at least one chatbot framework for a responding user such as a merchant. User content is converted in real time content into converted chatbot content within the chatbot framework. A chatbot interface is created to be communicated to initiating users such as clients via the input/output interface. Initiator users such as clients input queries and/or commands from their user device related to responding user content such as merchant content via the user chatbot interface.

Abstract: Embodiments provide methods, and server systems for enhancing checkout experience of an e-commerce transaction. A method includes receiving, by a server system associated with a payment network, a pre-authentication request signal for a prospective e-commerce transaction for a payment card of user. The pre-authentication request signal includes a time data for an expected transaction time, a transaction amount data, a payment card data and at least one transaction identifier data. The method includes electronically facilitating a pre-authentication of the prospective e-commerce transaction based at least on performing a multi-factor pre-authentication. Upon successful pre-authentication, the method includes storing a pre-authenticated transaction data. The method includes sending a notification signal of successful pre-authentication to a user device.

Abstract: A method for modulating a position of a movable command input image displayed on a graphical user interface (GUI) based on a user viewing direction relative to graphical user interface comprises capturing real time images of the user's face, eyes and irises. The general eye orientation of the user is determined based on the real time images. A first position of the movable command input image displayed on the GUI is determined. The GUI is separated into portions. A real-time correlation between the general eye orientation and one or more of the interface portions is determined thereby determining a viewing direction of the user and one or more real-time viewed interface portions. The movable command input image is moved from the first position to a second position on the GUI. The second position is at the one or more real-time viewed interface portions.

Abstract: Endurance mechanisms are introduced for memories such as non-volatile memories for broad usage including caches, last-level cache(s), embedded memory, embedded cache, scratchpads, main memory, and storage devices. Here, non-volatile memories (NVMs) include magnetic random-access memory (MRAM), resistive RAM (ReRAM), ferroelectric RAM (FeRAM), phase-change memory (PCM), etc. In some cases, features of endurance mechanisms (e.g., randomizing mechanisms) are applicable to volatile memories such as static random-access memory (SRAM), and dynamic random-access memory (DRAM). The endurance mechanisms include a wear leveling scheme that uses index rotation, outlier compensation to handle weak bits, and random swap injection to mitigate wear out attacks.

Abstract: A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A memory device including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density material.

Abstract: Endurance mechanisms are introduced for memories such as non-volatile memories for broad usage including caches, last-level cache(s), embedded memory, embedded cache, scratchpads, main memory, and storage devices. Here, non-volatile memories (NVMs) include magnetic random-access memory (MRAM), resistive RAM (ReRAM), ferroelectric RAM (FeRAM), phase-change memory (PCM), etc. In some cases, features of endurance mechanisms (e.g., randomizing mechanisms) are applicable to volatile memories such as static random-access memory (SRAM), and dynamic random-access memory (DRAM). The endurance mechanisms include a wear leveling scheme that uses index rotation, outlier compensation to handle weak bits, and random swap injection to mitigate wear out attacks.