Abstract: Approaches for integrating FE memory arrays into a processor, and the resulting structures are described. Simultaneous integrations of regions with ferroelectric (FE) cells and regions with standard interconnects are also described. FE cells include FE capacitors that include a FE stack of layers, which is encapsulated with a protection material. The protection material protects the FE stack of layers as structures for regular logic are fabricated in the same die.

Abstract: A method may include bridging in, via a fabric, a multicast data packet from a source device to a first edge device of a plurality of edge devices and flooding the multicast data packet to the plurality of edge devices within a mutual subnetwork of the fabric. The method further includes bridging out the multicast data packet from a second edge device of the plurality of edge devices to a receiving device. The source device and the receiving device are located within the mutual subnetwork.

Abstract: A low power sequential circuit (e.g., latch) uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. In one example, a sequential circuit includes pass-gates and inverters, but without a feedback mechanism or memory element. In another example, a sequential uses load capacitors (e.g., capacitors coupled to a storage node and a reference supply). The load capacitors are implemented using ferroelectric material, paraelectric material, or linear dielectric. In one example, a sequential uses minority, majority, or threshold gates with ferroelectric or paraelectric capacitors. In one example, a sequential circuit uses minority, majority, or threshold gates configured as NAND gates.

Abstract: Automated techniques for converting network devices from a Layer 2 (L2) network into a Layer 3 (L3) network in a hierarchical manner are described herein. The network devices may be configured to boot such that their ports are in an initialization mode in which the ports are unable to transmit locally generated DHCP packets. When a network device detects that a neighbor (or “peer”) device has acquired an IP address or has been configured by a network controller, then the port on which the neighbor device is detected can then be transitioned from the initialization mode into a forwarding mode. In the forwarding mode, the port can be used to transmit packets to obtain an IP address. Thus, the network devices are converted from an L2 device to an L3 device in a hierarchical order such that upstream devices are discovered and converted into L3 devices before downstream devices.

Abstract: Methods, systems, and devices for wireless communications are described, in which a base station may determine a load balancing adjustment for traffic communicated through the base station. The load balancing adjustment may be provided at a beam level for one or more beams of a plurality of beams, at a network slice level for one or more network slice IDs of a number of network slice IDs, or combinations thereof. The base station may use the load balancing adjustment to identify one or more updated parameters for triggering a handover of at least one user equipment (UE) between beams or slice IDs of a same cell or different cells. The base station may format a mobility change request that indicates the one or more parameters that are updated, and transmit the mobility change request to another base station to establish parameters for handovers between the base stations.

Abstract: Described herein is a memory bit-cell that results in lower leakage and higher sensing margin. In at least one embodiment, a memory bit-cell comprises a plurality of capacitors, wherein an individual capacitor is coupled to a node and an individual plate-line. In at least one embodiment, memory bit-cell comprises a first transistor coupled to the node. In at least one embodiment, memory bit-cell comprises a second transistor coupled in series with the first transistor, wherein the second transistor is coupled to a bit-line, wherein the first transistor or the second transistor is controllable by a word-line, and wherein the word-line is parallel to the individual plate-line.

Abstract: The memory bit-cell formed using the ferroelectric capacitor results in a taller and narrower bit-cell compared to traditional memory bit-cells. As such, more bit-cells can be packed in a die resulting in a higher density memory that can operate at lower voltages than traditional memories while providing the much sought after non-volatility behavior. The pillar capacitor includes a plug that assists in fabricating a narrow pillar.

Abstract: In one aspect, the present invention encompasses blends of structurally different polycarbonate polyols, resulting polyurethanes derived from such blends of polyols, methods of making such polyurethane compositions, and coatings and adhesives derived from such polyurethane compositions.

Abstract: Described herein is a memory bit-cell that results in lower leakage and higher sensing margin. In at least one embodiment, a memory bit-cell comprises a plurality of capacitors, wherein an individual capacitor is coupled to a node and an individual plate-line. In at least one embodiment, memory bit-cell comprises a first transistor coupled to the node. In at least one embodiment, memory bit-cell comprises a second transistor coupled in series with the first transistor, wherein the second transistor is coupled to a bit-line, wherein the first transistor or the second transistor is controllable by a word-line, and wherein the word-line is parallel to the individual plate-line.

Abstract: Certain aspects of the present disclosure provide techniques for handling RRC segmentation during a handover procedure. According to certain aspects, a UE may transmit, to a source base station prior to a handover of the UE to a target base station, one or more first segments of a radio resource control (RRC) message; and transmit, to the target base station after the handover, one or more second segments of the RRC message.

Abstract: A disturb mitigation scheme is described for a 1TnC or multi-element ferroelectric gain bit-cell where after writing to a selected capacitor of the bit-cell, a cure phase is initiated. Between the cure phase and the write phase, there may be zero or more cycles where the selected word-line, bit-line, and plate-lines are pulled-down to ground. The cure phase may occur immediately before the write phase. In the cure phase, the word-line is asserted again just like in the write phase. In the cure phase, the voltage on bit-line is inverted compared to the voltage on the bit-line in the write phase. By programming a value in a selected capacitor to be opposite of the value written in the write phase of that selected capacitor, time accumulation of disturb is negated. This allows to substantially zero out disturb field on the unselected capacitors of the same bit-cell and/or other unselected bit-cells.

Abstract: The present invention discloses a process for extraction of oil from the Valeriana jatamansi Jones by Supercritical Fluid extraction (SFE) process with and without co-solvent. The extraction method is performed on the comminuted Valeriana jatamansi Jones using different mesh size of root/rhizome under a pressure ranging from about 220-360 bar and temperature about 45° C. utilizing carbon dioxide as a supercritical fluid. Further the volatile fractions are separated from the supercritical fluid at reduced pressure in the range of about 10-60 bar. Later the same material has been extracted with polar solvent (ethanol) as the co-solvent. The qualitative comparison of essential oil has been done between the essential oil obtained from Hydro distillation and Supercritical Fluid Extraction.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may transmit capability information that indicates support for one or more model combinations of machine learning (ML) models, wherein the capability information further indicates one or more performance parameters of an ML model of the ML models with respect to a model combination of the one or more model combinations that includes the ML model. The UE may receive one or more indications to use one or more of the ML models based at least in part on the capability information. Numerous other aspects are described.

Abstract: Certain aspects of the present disclosure provide techniques and apparatus for a priority-aware transmit power control in compliance with a radio frequency (RF) exposure limit. An example method of wireless communication includes obtaining a transmit power budget for a time interval. The method further includes obtaining at least a first packet having a first priority and a second packet having a second priority lower than the first priority for transmission in the time interval. The method further includes determining a first transmit power for a first signal representing at least the first packet based at least in part on the transmit power budget, the first priority, and a time elapsed in the time interval. The method further includes transmitting the first signal representing at least the first packet at the determined first transmit power.

Abstract: Aspects present herein relate to methods and devices for wireless communication including an apparatus, e.g., a UE and/or a base station. The apparatus may receive, from a base station, a logged measurement configuration including a PLMN ID and a NID, the logged measurement configuration further including at least one of a trace reference, a logging area, a MDT PLMN list, or a MDT NPN list. The apparatus may also store the PLMN ID and the NID based on the received logged measurement configuration. Additionally, the apparatus may compare the PLMN ID and the NID to an MDT SNPN list to identify if the PLMN ID and the NID are included in the MDT SNPN list. The apparatus may also transmit, to the base station, an availability indicator if the PLMN ID and the NID are included in the MDT SNPN list.

Abstract: A configuration for efficiently placing a group of capacitors with one terminal connected to a common node is described. The capacitors are stacked and folded along the common node. In a stack and fold configuration, devices are stacked vertically (directly or with a horizontal offset) with one terminal of the devices being shared to a common node, and further the capacitors are placed along both sides of the common node. The common node is a point of fold. In one example, the devices are capacitors. N number of capacitors can be divided in L number of stack layers such that there are N/L capacitors in each stacked layer. The N/L capacitors are shorted together with an electrode (e.g., bottom electrode). The electrode can be metal, a conducting oxide, or a combination of a conducting oxide and a barrier material. The capacitors can be planar, non-planar or replaced by memory elements.

Abstract: Described is a packaging technology to improve performance of an AI processing system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die includes memory and the second die includes computational logic. The first die comprises DRAM having bit-cells. The memory of the first die may store input data and weight factors. The computational logic of the second die is coupled to the memory of the first die. In one example, the second die is an inference die that applies fixed weights for a trained model to an input data to generate an output. In one example, the second die is a training die that enables learning of the weights. Ultra high-bandwidth is changed by placing the first die below the second die. The two dies are wafer-to-wafer bonded or coupled via micro-bumps.

Abstract: A ferroelectric memory chiplet in a multi-dimensional packaging. The multi-dimensional packaging includes a first die comprising a switch and a first plurality of input-output transceivers. The multi-dimensional packaging includes a second die comprising a processor, wherein the second die includes a second plurality of input-output transceivers coupled to the first plurality of input-output transceivers. The multi-dimensional packaging includes a third die comprising a coherent cache or memory-side buffer, wherein the coherent cache or memory-side buffer comprises ferroelectric memory cells, wherein the coherent cache or memory-side buffer is coupled to the second die via I/Os. The dies are wafer-to-wafer bonded or coupled via micro-bumps, copper-to-copper hybrid bond, or wire bond, Flip-chip ball grid array routing, chip-on-wafer substrate, or embedded multi-die interconnect bridge.

Abstract: Methods, systems, and devices for wireless communication are described. A user equipment (UE) may receive control signaling indicating a measurement configuration for minimization of drive test measurement and reporting supporting broadcast receptions within a single-frequency network. The UE may determine, based at least in part on the measurement configuration, a set of measurements for the single-frequency network. The UE may transmit a minimization of drive test report indicating the set of measurements.

Abstract: Various implementations for an automatic system and processes for monitoring the use of personal protective equipment in a work space are provided. The system includes barcodes attached to the personal protective equipment. The operation of the system involves capturing images of the work space and detecting human form objects and barcode objects in the images. The system and processes further involve calculating the probability that a user is wearing all personal protective equipment in accordance with safety rules applicable to the work space. In some implementations, the system and processes may be used to track personal protective equipment and other objects in a work space. Accordingly, the system and processes may be used to prevent or limit the occurrence of accidents, incidents and/or injuries in hazardous work environments.