Abstract: A computer-implemented system for modulating a navigation graphical user interface during movement of a vehicle comprises a device with an interface and a controller with a memory. The memory comprises a positioning system application providing for real-time tracking of a position of the moving vehicle within a geographic location and determining a direction pathway towards a target location within the geographic location. The interface comprises a display for displaying the navigation graphical user interface. A system controller determines the geographic location of the device and of the moving vehicle via the positioning system application in the memory of the device and accessible thereto via the interface. A leader virtual vehicle image is generated within the navigation graphical user interface and is displayed via the device display. The virtual vehicle image is positioned ahead of the tracked position of the moving vehicle within the navigation pathway.

Abstract: Aspects presented herein may enable a network entity (e.g., a consumer network entity) to request data and/or analytics (e.g., AI/ML analytics, AI/ML inference, etc.) from another network entity (e.g., a RAN) via a core network or a function associated with the network (e.g., an NWDAF of the core network). In one aspect, a core network entity receives, from a first network entity, an analytics request. The core network entity transmits, to a second network entity, a data collection request based at least in part on the analytics request. The core network entity receives, from the second network entity, a data collection response based on the data collection request. The core network entity transmits, to the first network entity, an analytics response based at least in part on the data collection response.

Abstract: A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A trench capacitor including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density dielectric material.

Abstract: A system and method for providing technical support when using an application that includes recording and/or otherwise capturing a problem as a video file or screen image while using the application and sending the file or image to a technician from the application. The system includes a back-end server operating the online application and having a processor for processing data and information, a communications interface communicatively coupled to the processor, and a memory device storing data and executable code. When the code is executed, the processor can allow a user to record the problem that the user encounters while using the application as a file, send the file to a technical support team to be reviewed, and allow the user to correspond with a technician about the file.

Abstract: Methods, systems, and devices for wireless communications are described. In some examples, a wireless communications system may support machine learning and may configure a user equipment (UE) for machine learning. The UE may transmit, to a base station, a request message that includes an indication of a machine learning model or a neural network function based at least in part on a trigger event. In response to the request message, the base station may transmit a machine learning model, a set of parameters corresponding to the machine learning model, or a configuration corresponding to a neural network function and may transmit an activation message to the UE to implement the machine learning model and the neural network function.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may initiate a quality of experience (QoE) session for a QE configuration at an application layer of the UE. The UE may provide, from the application to a radio resource control (RRC) layer of the UE, a session start or stop indication based at least in part on initiating the QoE session. The indication may include at least one of a service type, an RRC level identifier, a QoE reference, or a QoE measurement collection. The UE may provide, to a base station and based at least in part on the indication, information indicating the service type, the RRC level identifier, the QoE reference, or the QoE measurement collection. Numerous other aspects are described.

Abstract: A packaging technology to improve performance of an AI processing system resulting in an ultra-high bandwidth system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die can be a first logic die (e.g., a compute chip, CPU, GPU, etc.) while the second die can be a compute chiplet comprising ferroelectric or paraelectric logic. Both dies can include ferroelectric or paraelectric logic. The ferroelectric/paraelectric logic may include AND gates, OR gates, complex gates, majority, minority, and/or threshold gates, sequential logic, etc. The IC package can be in a 3D or 2.5D configuration that implements logic-on-logic stacking configuration. The 3D or 2.5D packaging configurations have chips or chiplets designed to have time distributed or spatially distributed processing. The logic of chips or chiplets is segregated so that one chip in a 3D or 2.5D stacking arrangement is hot at a time.

Abstract: A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A trench capacitor including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density dielectric material.

Abstract: A method for monetizing ferroelectric process development is described. In at least one embodiment, the method comprises procuring a target material based on a model driven selection which is based on charge, mass and magnetic moment, and/or mass of the atomic constituents of the target material. The method further comprises applying the target material to a fabrication process to build a ferroelectric device. The method further comprises generating a notification indicative of procurement of the target material and application of the target material. The method further comprises electronically transmitting the notification to a customer, wherein the notification includes an invoice having a line item associated with a cost of the procuring of the target material and application of the target material.

Abstract: A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A trench capacitor including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density dielectric material.

Abstract: A packaging technology to improve performance of an AI processing system resulting in an ultra-high bandwidth system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die can be a first logic die (e.g., a compute chip, CPU, GPU, etc.) while the second die can be a compute chiplet comprising ferroelectric or paraelectric logic. Both dies can include ferroelectric or paraelectric logic. The ferroelectric/paraelectric logic may include AND gates, OR gates, complex gates, majority, minority, and/or threshold gates, sequential logic, etc. The IC package can be in a 3D or 2.5D configuration that implements logic-on-logic stacking configuration. The 3D or 2.5D packaging configurations have chips or chiplets designed to have time distributed or spatially distributed processing. The logic of chips or chiplets is segregated so that one chip in a 3D or 2.5D stacking arrangement is hot at a time.

Abstract: Systems, methods, and computer-readable media are provided for performing secure frame encryption as a service. For instance, a network edge device can determine at least a first path and a second path for routing a data packet. The network edge device can obtain a first plurality of values for at least one network metric, wherein the first plurality of values corresponds to the first path and at least a first backup path associated with the first path. The network edge device can obtain a second plurality of values for the at least one network metric, wherein the second plurality of values corresponds to the second path and at least a second backup path associated with the second path. The network edge device can select one of the first path or the second path for routing the data packet based on a comparison of the first plurality of values and the second plurality of values.

Abstract: This disclosure provides methods, components, devices and systems for Neighbor Aware Networking (NAN) communications between two devices concurrently over multiple NAN Data Links (NDLs). A multi-NDL connection is formed between two NAN devices where both devices support multi-link operation (MLO) for NAN communications. A first NAN device and a second NAN device each advertises its respective capability to support MLO for NAN communications to the other device by transmitting to the other device a NAN frame that includes an MLO information element. A multi-NDL connection is formed between the first NAN device and the second NAN device in accordance with the information in the multi-link information elements. Each NDL of the multi-NDL connection is associated with a set of frequency channels that do not overlap the set of frequency channels associated with another NDL. Concurrent NAN communication can occur over the multiple NDLs.

Abstract: A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A trench capacitor including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density dielectric material.

Abstract: Asynchronous circuit elements are described. Asynchronous circuit elements include a consensus element (c-element), completion tree, and validity tree. The c-element is implemented using adjustable threshold based multi-input capacitive circuitries. The completion tree comprises a plurality of c-elements organized in a tree formation. The validity tree comprises OR gates followed by c-elements. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the various asynchronous circuitries.

Abstract: Asynchronous circuit elements are described. Asynchronous circuit elements include a consensus element (c-element), completion tree, and validity tree. The c-element is implemented using adjustable threshold based multi-input capacitive circuitries. The completion tree comprises a plurality of c-elements organized in a tree formation. The validity tree comprises OR gates followed by c-elements. The multi-input capacitive circuitries include capacitive structures that may comprise linear dielectric, paraelectric dielectric, or ferroelectric dielectric. The capacitors can be planar or non-planar. The capacitors may be stacked vertically to reduce footprint of the various asynchronous circuitries.

Abstract: A device includes, in a first region, a first conductive interconnect, an electrode structure on the first conductive interconnect, where the electrode structure includes a first conductive hydrogen barrier layer and a first conductive fill material. A memory device including a ferroelectric material or a paraelectric material is on the electrode structure. A second dielectric includes an amorphous, greater than 90% film density hydrogen barrier material laterally surrounds the memory device. A via electrode including a second conductive hydrogen barrier material is on at least a portion of the memory device. A second region includes a conductive interconnect structure embedded within a less than 90% film density material.

Abstract: Embodiments provide methods and systems for recovering a failed payment processing request. Method includes receiving, by a server system associated with a payment network, a transaction recovery request signal initiated from a User Interface (UI) of a merchant application running on a user device for recovering a payment transaction failed due to a disconnection between the server system and a merchant server. The request signal includes a unique ID associated with the payment transaction. The method includes electronically retrieving a corresponding transaction information stored against the unique ID. The transaction information includes a transaction status. The unique ID is sent in advance by the merchant server along with a transaction amount. The method includes identifying the transaction status as an approved payment transaction. The method includes sending a confirmation notification signal including the transaction status to the merchant server.

Abstract: Various aspects of the present disclosure generally relate to wireless communication. In some aspects, a user equipment (UE) may receive, from a first base station prior to entering an inactive state, one or more quality of experience (QoE) configurations. The UE may perform, based at least in part on transitioning from the inactive state to a connected state with a second base station, at least one operation for the one or more QoE configurations. Numerous other aspects are described.

Abstract: A packaging technology to improve performance of an AI processing system resulting in an ultra-high bandwidth system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die can be a first logic die (e.g., a compute chip, CPU, GPU, etc.) while the second die can be a compute chiplet comprising ferroelectric or paraelectric logic. Both dies can include ferroelectric or paraelectric logic. The ferroelectric/paraelectric logic may include AND gates, OR gates, complex gates, majority, minority, and/or threshold gates, sequential logic, etc. The IC package can be in a 3D or 2.5D configuration that implements logic-on-logic stacking configuration. The 3D or 2.5D packaging configurations have chips or chiplets designed to have time distributed or spatially distributed processing. The logic of chips or chiplets is segregated so that one chip in a 3D or 2.5D stacking arrangement is hot at a time.