Patents by Inventor Rajeev
Rajeev has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250203396Abstract: A network node obtains, from a core network component, a quality of experience (QoE) configuration associated with a high speed dedicated network (HSDN) indication and outputs the QoE configuration for a user equipment (UE) based on the UE being camped on an HSDN cell or based on a mobility condition of the UE. A UE receives, from a network node, a QoE configuration associated with an HSDN indication and collects QoE information based on at least one of an HSDN status of a cell or a mobility condition of the UE.Type: ApplicationFiled: April 29, 2022Publication date: June 19, 2025Inventors: Shankar KRISHNAN, Jianhua LIU, Xipeng ZHU, Rajeev KUMAR
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Publication number: 20250201778Abstract: Described is a packaging technology to improve performance of an AI processing system. An IC package is provided which comprises: a substrate; a first die on the substrate, and a second die stacked over the first die. The first die includes memory and the second die includes computational logic. The first die comprises a ferroelectric RAM (FeRAM) having bit-cells. Each bit-cell comprises an access transistor and a capacitor including ferroelectric material. The access transistor is coupled to the ferroelectric material. The FeRAM can be FeDRAM or FeSRAM. The memory of the first die may store input data and weight factors. The computational logic of the second die is coupled to the memory of the first die. The second die is an inference die that applies fixed weights for a trained model to an input data to generate an output. In one example, the second die is a training die that enables learning of the weights.Type: ApplicationFiled: March 3, 2025Publication date: June 19, 2025Applicant: Kepler Computing Inc.Inventors: Sasikanth Manipatruni, Rajeev Kumar Dokania, Amrita Mathuriya, Ramamoorthy Ramesh
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Publication number: 20250201037Abstract: A control system and method of performing an inspection event on a vehicle includes identifying a type of energy used to power one or more components of the vehicle; and from plural different test preset settings, selecting at least one selected setting based at least in part on the type of energy that is identified. One or more control settings of the vehicle are changed based on the at least one selected setting to energize at least one component of a propulsion system of the vehicle at a first level of energization. One or more first characteristics of one or more systems of the vehicle are obtained responsive to the energizing of the at least one component at the first level of energization. A condition or operating readiness level of the vehicle is determined based at least in part on the one or more first characteristics.Type: ApplicationFiled: December 13, 2024Publication date: June 19, 2025Applicant: Transportation IP Holdings, LLCInventors: Lindsay Moir, Chirag Bipinchandra Parikh, Tyler Yost, Margaret Ilorieuse Dieudonne, Mike Beyerlein, Naren Dhass, David Eugene Dukes, Shankar Chandrasekaran, Harold Hostettler, Scott Zarella, Rajeev Verma, Prasanth Sunkara
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Patent number: 12336184Abstract: A device structure comprises a first conductive interconnect, an electrode structure on the first conductive interconnect, an etch stop layer laterally surrounding the electrode structure; a plurality of memory devices above the electrode structure, where individual ones of the plurality of memory devices comprise a dielectric layer comprising a perovskite material. The device structure further comprises a plate electrode coupled between the plurality of memory devices and the electrode structure, where the plate electrode is in direct contact with a respective lower most conductive layer of the individual ones of the plurality of memory devices. The device structure further includes an insulative hydrogen barrier layer on at least a sidewall of the individual ones of the plurality of memory devices; and a plurality of via electrodes, wherein individual ones of the plurality of via electrodes are on a respective one of the individual ones of the plurality of memory devices.Type: GrantFiled: March 18, 2022Date of Patent: June 17, 2025Assignee: Kepler Computing Inc.Inventors: Noriyuki Sato, Tanay Gosavi, Rafael Rios, Amrita Mathuriya, Niloy Mukherjee, Mauricio Manfrini, Rajeev Kumar Dokania, Somilkumar J. Rathi, Sasikanth Manipatruni
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Patent number: 12331023Abstract: The present invention provides substituted heterocyclylderivatives of formula (I), which are therapeutically useful, particularly as selective transcriptional CDK inhibitors including CDK7, CDK9, CDK12, CDK13 and CDK18, more particularly transcriptional CDK7 inhibitors. These compounds are useful in the treatment and prevention of diseases and/or disorders associated with selective transcriptional CDKs in a mammal. The present invention also provides preparation of the compounds and pharmaceutical formulations comprising at least one of the substituted heterocyclyl derivatives of formula (I) or a pharmaceutically acceptable salt or a stereoisomer thereof.Type: GrantFiled: October 7, 2021Date of Patent: June 17, 2025Assignee: Aurigene Oncology LimitedInventors: Susanta Samajdar, Ramulu Poddutoori, Chetan Pandit, Subhendu Mukherjee, Rajeev Goswami
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Patent number: 12334918Abstract: An apparatus and configuring scheme where a capacitive input circuit can be programmed to perform different logic functions by adjusting the switching threshold of the capacitive input circuit. Digital inputs are received by respective capacitors on first terminals of those capacitors. The second terminals of the capacitors are connected to a summing node. A pull-up and pull-down device are coupled to the summing node. The pull-up and pull-down devices are controlled separately. During a reset phase, the pull-up and/or pull-down devices are turned on or off in a sequence, and inputs to the capacitors are set to condition the voltage on node n1. As such, a threshold for the capacitive input circuit is set. After the reset phase, an evaluation phase follows. In the evaluation phase, the output of the capacitive input circuit is determined based on the inputs and the logic function configured during the reset phase.Type: GrantFiled: December 15, 2021Date of Patent: June 17, 2025Assignee: Kepler Computing Inc.Inventors: Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Rajeev Kumar Dokania, Debo Olaosebikan, Sasikanth Manipatruni
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Patent number: 12334923Abstract: A multiplier cell is derived from a 1-bit full adder and an AND gate. The 1-bit full adder is derived from majority and/or minority gates. The majority and/or minority gates include non-linear polar material (e.g., ferroelectric or paraelectric material). A reset mechanism is provided to reset the nodes across the non-linear polar material. The multiplier cell is a hybrid of majority and/or minority gates and complementary metal oxide semiconductor (CMOS) based inverters and/or buffers. The adder uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. The non-linear polar capacitor includes ferroelectric material, paraelectric material, or non-linear dielectric. Input signals are received by respective terminals of capacitors having non-linear polar material. The other terminals of these capacitors are coupled to a node where the majority function takes place for the inputs.Type: GrantFiled: October 1, 2021Date of Patent: June 17, 2025Assignee: Kepler Computing Inc.Inventors: Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Rajeev Kumar Dokania, Sasikanth Manipatruni
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Patent number: 12334127Abstract: Described herein is a memory bit-cell that results in lower leakage and higher sensing margin. In at least one embodiment, a memory bit-cell comprises a plurality of capacitors, wherein an individual capacitor is coupled to a node and an individual plate-line. In at least one embodiment, memory bit-cell comprises a first transistor coupled to the node. In at least one embodiment, memory bit-cell comprises a second transistor coupled in series with the first transistor, wherein the second transistor is coupled to a bit-line, wherein the first transistor or the second transistor is controllable by a word-line, and wherein the word-line is parallel to the individual plate-line.Type: GrantFiled: January 30, 2023Date of Patent: June 17, 2025Assignee: Kepler Computing Inc.Inventors: Rajeev Kumar Dokania, Mustansir Yunus Mukadam, Erik Unterborn, Pramod Kolar, Amrita Mathuriya, Debo Olaosebikan, Tanay Gosavi, Noriyuki Sato, Sasikanth Manipatruni
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Publication number: 20250193177Abstract: A system to perform operations that include: minting a Non-Fungible Token (NFT) that comprises a media object and mutable metadata; allocating the NFT to a user of a client device; granting the user of the client device a permission to change the mutable metadata of the NFT based on the allocating the NFT to the user of the client device; generating an open-edition of the NFT, the open-edition of the NFT comprising a reference to the mutable metadata; receiving a change to the mutable metadata from the user of the client device; and updating the open-edition of the NFT based on the change.Type: ApplicationFiled: February 14, 2025Publication date: June 12, 2025Inventors: Rajeev Advani, Sophia Dominguez, Vu Tran
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Publication number: 20250193624Abstract: Disclosed implementations for generating personalized audio. In response to receiving sensor data corresponding with a physical characteristic of a user, a first function is determined based on a similarity between the physical characteristic of the user and a first model and a second function is determined based on a similarity of the physical characteristic between the user and a second model. A modified function, representing an audio response, is generated by combining the first function and the second function. An audio stream is generated based on the modified function.Type: ApplicationFiled: December 9, 2024Publication date: June 12, 2025Inventors: Sinan Hersek, Dongeek Shin, Pouya Samangouei, Rajeev Nongpiur
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Patent number: 12325066Abstract: A casting furnace includes a melting chamber, a dual zone mold heating chamber, and a dual zone mold cooling chamber. The melting chamber provides a source of molten alloy or ceramics with adequate superheat. The dual zone mold heating chamber includes an independently controlled primary heating zone and a secondary heating zone. The primary heating zone raises the mold temperature adequately to impart high gradient solidification conditions. The secondary heating zone assists the primary heating zone to minimize overheating of the majority of the mold. The dual zone mold cooling chamber includes a primary cooling chamber and a secondary cooling chamber. The primary cooling chamber speeds up solidification in order to prevent defect formation and refine microstructure. The secondary cooling chamber slows down the cooling of castings to reduce residual stresses build up and minimize elemental segregation through augmenting solid-state diffusion of lower melting elements.Type: GrantFiled: March 19, 2024Date of Patent: June 10, 2025Inventor: Rajeev Naik
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Publication number: 20250177775Abstract: A Circadian Rhythm Monitoring and Regulation (CMR) system and method that includes: a novel non-obtrusive wearable system for increasing the health and productivity of warfighters or other individuals that are disrupted by excessive, abnormal shifts in work or flights across multiple time zones. The CMR system is based on advanced sensor and software technology and models of human circadian system phototransduction and a circadian stimulator oscillator developed by applicants. It measures circadian misalignment and provides lighting suggestions for circadian rhythm maintenance and realignment.Type: ApplicationFiled: January 31, 2025Publication date: June 5, 2025Inventors: Devendra Tolani, Pedram Hovareshti, Rajeev Bhalla, Glenn Nickens, Jordan Specht, Devon Callan, Andrew Bierman, Mariana G. Figueiro, Geoffrey E. Jones, Mark S. Rea, Gregory A. Ward
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Publication number: 20250177885Abstract: A system, composition, method and kit for removing a detergent, such as an anionic detergent, from an aqueous solution, comprising a salt, a water immiscible alcohol of Formula I: R1—OH??(Formula I) where R1 is an optionally substituted, linear, branched or cyclic C4-C12 alkyl; and a water immiscible halocarbon, wherein said halocarbon is miscible with said alcohol of Formula I. The system can be used on aqueous solutions that contain detergents (such as Sodium Dodecyl Sulphate (SDS), for example), and any detergent-associated or detergent-bound molecules that may be present in the aqueous solution, to form an aqueous phase and a non-aqueous phase, for effectively removing the detergent and any detergent-associated or detergent-bound molecules, and sequestering them into the non-aqueous phase.Type: ApplicationFiled: February 3, 2025Publication date: June 5, 2025Applicant: DNA GENOTEK INC.Inventors: Hyman Chaim BIRNBOIM, Rajeev Mani NEPAL, Bitapi RAY, Jessica Lynne GAGE, Christopher Gordon ASKEW
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Publication number: 20250179755Abstract: A solar module support and foundation system includes a first concrete foundation, a second concrete foundation, and a solar module A-frame support. The first concrete foundation is within a first bore and includes a first concrete foundation stem portion and a first concrete foundation reamed bulb portion. The second foundation is within a second bore and includes a second concrete foundation stem portion and a second concrete foundation reamed bulb portion. A first leg distal end of the A-frame support is nested within the first concrete foundation at each of the first concrete foundation stem and reamed bulb portions, and a second leg distal end of the A-frame support is nested within the second concrete foundation at each of the second concrete foundation stem and reamed bulb portions.Type: ApplicationFiled: August 7, 2024Publication date: June 5, 2025Inventors: Abhimanyu Anil Sable, Raghavendra Praveen Maddulapalli, Jacob Mark Morin, Rajeev Kumar Samayamanthula
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Publication number: 20250181834Abstract: Disclosed herein are apparatus, system, method, and computer-readable medium aspects for extracting themes from textual data. Textual data is initially cleansed from its submitted form into a simplified form for improved accuracy of topic extraction. From the cleansed text, phrases are extracted. Embeddings of the phrases are then determined so that similarities can be identified between different phrases within the text. Using these embodiments, clustering is performed on the embeddings to reveal the topics included within the text submission, as well as their frequency and relationship to one another. This clustering processing can be repeated at multiple levels of granularity for improved accuracy. Based on an analysis of the resulting clusters, a graphical representation of the clusters at the various levels is generated to provide an easy-to-understand indication of the body of text and the topics and themes included therein.Type: ApplicationFiled: November 30, 2023Publication date: June 5, 2025Applicant: AMERICAN EXPRESS TRAVEL RELATED SERVICES COMPANY, INC.Inventors: Salil Rajeev JOSHI, Aayush SACHETI, Minnie KABRA, Abhishek JHA, Abhinav NAGPAL
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Publication number: 20250180645Abstract: Scan testing features on a chip may include a streaming scan network (SSN) with core streaming scan hubs (CSHs). A CSH may include a parent bus interface, a child bus interface, and a streaming scan hub (SSH). A CSH may also include multiplexing logic configured to select whether the child bus interface is included in the SSN or excluded from the SSN. Multiple CSHs may be interconnected in a hierarchical topology through the child bus interfaces.Type: ApplicationFiled: February 24, 2023Publication date: June 5, 2025Inventors: Jais ABRAHAM, Arvind JAIN, Rajeev KOMALAN NAIR, Basim Mohammed Issa SHANYOUR, Madan KRISHNAPPA
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Publication number: 20250184320Abstract: In an aspect of the disclosure, a method includes: obtaining, by a computing device, a user request to access at least one system resource; obtaining, by the computing device, a digital certificate of the user requesting access to the at least one system resource; obtaining, by the computing device, a validation result associated with the digital certificate from a blockchain ledger network; determining, by the computing device, whether the validation result authorizes access to an authorization service; and sending the authorization to the authorization service to deny or permit the user access to the at least one system resource based on the validation result.Type: ApplicationFiled: November 30, 2023Publication date: June 5, 2025Inventors: Sachio Iwamoto, Nadeem Malik, Balaji Narasimhan, Kishor Grandhe, Cesar Augusto Rodriguez Bravo, Rajeev Puri
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Publication number: 20250184211Abstract: A method for managing a plurality of network devices of a network includes determining, by one or more processors, a causality map for the plurality of network devices according to an intent. The method further includes receiving, by the one or more processors, an indication of a network service impact and determining, by the one or more processors, a relevant portion of the causality map based on the network service impact. The method further includes determining, by the one or more processors, one or more candidate root cause faults based on the relevant portion of the causality map and outputting, by the one or more processors, an indication of the one or more candidate root cause faults.Type: ApplicationFiled: February 13, 2025Publication date: June 5, 2025Inventors: Chi Fung Michael Chan, Aleksandar Luka Ratkovic, Raunak Banthia, Atul Bhaskarrao Patil, Diheng Qu, Rajeev Menon Kadekuzhi, Roman Andreevich Bogorodskiy, Aleksandr Dmitrievich Gordeev, Aleksei Vladimirovich Goditskii
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Patent number: 12321767Abstract: The techniques disclosed herein enable a guest operating system (OS) to access and use a media processing component configured on a host OS. The guest OS provides, via an API, a request to create an instance of the media processing component (e.g., a codec, an encryption/decryption component, a DRM component). In association with the request, the guest OS allocates space in memory for media data that is to be processed by the instance of the media processing component configured on the host OS. The guest OS stores the input media data in the allocated memory and provides, via the API, reference(s) to locations of the allocated memory. The reference(s) to the locations of the allocated memory enable the host OS to retrieve the input media data and process the input media data using the instance of the media processing component configured on the host OS.Type: GrantFiled: September 30, 2022Date of Patent: June 3, 2025Assignee: MICROSOFT TECHNOLOGY LICENSING, LLCInventors: Anton Victor Polinger, Marcin Stankiewicz, Isuru Chamara Pathirana, Kumar Rajeev, Isha Sharma, Glenn Frederick Evans, Matthew R. Wozniak
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Patent number: 12322743Abstract: An apparatus and configuring scheme where a paraelectric capacitive input circuit can be programmed to perform different logic functions by adjusting the switching threshold of the paraelectric capacitive input circuit. Digital inputs are received by respective capacitors on first terminals of those capacitors. The second terminals of the capacitors are connected to a summing node. A pull-up and pull-down device are coupled to the summing node. The pull-up and pull-down devices are controlled separately. During a reset phase, the pull-up and/or pull-down devices are turned on or off in a sequence, and inputs to the capacitors are set to condition the voltage on node n1. As such, a threshold for the capacitive input circuit is set. After the reset phase, an evaluation phase follows. In the evaluation phase, the output of the capacitive input circuit is determined based on the inputs and the logic function configured during the reset phase.Type: GrantFiled: December 15, 2021Date of Patent: June 3, 2025Assignee: Kepler Computing Inc.Inventors: Amrita Mathuriya, Rafael Rios, Ikenna Odinaka, Rajeev Kumar Dokania, Debo Olaosebikan, Sasikanth Manipatruni