Abstract: A flip chip interconnection structure is formed by mechanically interlocking joining surfaces of a first and second element. The first element, which may be a bump on an integrated circuit chip, includes a soft, deformable material with a low yield strength and high elongation to failure. The surface of the second element, which may for example be a substrate pad, is provided with asperities into which the first element deforms plastically under pressure to form the mechanical interlock.

Abstract: A flip chip interconnect pad layout has the die signal pads are arranged on the die surface near the perimeter of the die, and the die power and ground pads arranged on the die surface inboard from the signal pads; and has the signal pads on the corresponding package substrate arranged in a manner complementary to the die pad layout and the signal lines routed from the signal pads beneath the die edge away from the die footprint, and has the power and ground lines routed to vias beneath the die footprint. Also, a flip chip semiconductor package in which the flip chip interconnect pad layouts have the die signal pads situated in the marginal part of the die and the die power and ground pads arranged on the die surface inboard from the signal pads, and the corresponding package substrates have signal pads arranged in a manner complementary to the die pad layout and signal lines routed from the signal pads beneath the die edge away from the die footprint.

Abstract: A method for connecting a chip to a leadframe includes forming bumps on a die by a Au stud-bumping technique, and attaching the chip to the leadframe by thermo-compression of the bumps onto bonding fingers of the leadframe. Also a flip chip-in-leadframe package is made according to the method. The package provides improved electrical performance particularly for devices used in RF applications.

Abstract: A flip chip interconnection structure is formed by mechanically interlocking joining surfaces of a first and second element. The first element, which may be a bump on an integrated circuit chip, includes a soft, deformable material with a low yield strength and high elongation to failure. The surface of the second element, which may for example be a substrate pad, is provided with asperities into which the first element deforms plastically under pressure to form the mechanical interlock.

Abstract: A flip chip interconnection structure is formed by mechanically interlocking joining surfaces of a first and second element. The first element, which may be a bump on an integrated circuit chip, includes a soft, deformable material with a low yield strength and high elongation to failure. The surface of the second element, which may for example be a substrate pad, is provided with asperities into which the first element deforms plastically under pressure to form the mechanical interlock.

Abstract: A flip chip interconnection structure is formed by mechanically interlocking joining surfaces of a first and second element. The first element, which may be a bump on an integrated circuit chip, includes a soft, deformable material with a low yield strength and high elongation to failure. The surface of the second element, which may for example be a substrate pad, is provided with asperities into which the first element deforms plastically under pressure to form the mechanical interlock.

Abstract: A chip scale integrated circuit chip package includes a die mounted by flip chip interconnection to a package substrate. The package substrate is a laminate including a dielectric layer having a single conductive trace layer on a first surface thereof (the “circuit side” of the substrate) and an active ground plane overlying a second surface thereof (the “dielectric side” of the substrate), wherein the die is mounted on the circuit side of the dielectric layer, the ground plane is electrically connected to ground sites at the first surface of the dielectric layer through openings in the dielectric layer, and wherein second level interconnects are on the circuit side of the dielectric layer.

Abstract: A fluxing composition is disclosed. The composition comprises a high molecular weight carboxylic acid that forms a combination of carboxylate salts and unreacted acid anhydrides when applied to a solder alloy and exposed to temperatures in the range of about 150 to 350° C. in an inert atmosphere and a carrier fluid comprising a mixture of organic solvents that is heat stable and non-reactive with the solder alloy and has a high viscosity at room temperature. Also disclosed is an integrated circuit assembly comprising an integrated circuit comprising a chip attached to a substrate by a plurality of solder joints and a thin layer of a residue comprising the carboxylate salts and acid anhydride. The film of residue is formed concomitantly with the formation of the solder joints during the reflow cycle. Since the residue is reactive with an epoxy used in bonding the chip to the substrate, the usual process step of cleaning the flux residue prior to dispensing the epoxy is obviated.

Abstract: A method for connecting a chip to a leadframe includes forming bumps on a die by a Au stud-bumping technique, and attaching the chip to the leadframe by thermo-compression of the bumps onto bonding fingers of the leadframe. Also a flip chip-in-leadframe package is made according to the method. The package provides improved electrical performance particularly for devices used in RF applications.

Abstract: A method for forming metallurgical interconnections and polymer adhesion of a flip chip to a substrate includes providing a chip having a set of bumps formed on a bump side thereof and a substrate having a set of interconnect points on a metallization thereon, providing a measured quantity of a polymer adhesive in a middle region of the chip on the bump side, aligning the chip with the substrate so that the set of bumps aligns with the set of interconnect points, pressing the chip and the substrate toward one another so that a portion of the polymer adhesive contacts the substrate and the bumps contact the interconnect points, and heating the bumps to a temperature sufficiently high to form a metallurgical connection between the bumps and the interconnect points. Also, a flip chip package is made by the method. In some embodiments the metallurgical connection includes an alloy of gold and tin at the interface between the bumps and the interconnect points.

Abstract: A flip chip interconnection structure is formed by mechanically interlocking joining surfaces of a first and second element. The first element, which may be a bump on an integrated circuit chip, includes a soft, deformable material with a low yield strength and high elongation to failure. The surface of the second element, which may for example be a substrate pad, is provided with asperities into which the first element deforms plastically under pressure to form the mechanical interlock.

Abstract: A fluxing composition is disclosed. The composition comprises a high molecular weight carboxylic acid that forms a combination of carboxylate salts and unreacted acid anhydrides when applied to a solder alloy and exposed to temperatures in the range of about 150 to 350.degree. C. in an inert atmosphere and a carrier fluid comprising a mixture of organic solvents that is heat stable and non-reactive with the solder alloy and has a high viscosity at room temperature. Also disclosed is an integrated circuit assembly comprising an integrated circuit comprising a chip attached to a substrate by a plurality of solder joints and a thin layer of a residue comprising the carboxylate salts and acid anhydride. The film of residue is formed concomitantly with the formation of the solder joints during the reflow cycle. Since the residue is reactive with an epoxy used in bonding the chip to the substrate, the usual process step of cleaning the flux residue prior to dispensing the epoxy is obviated.

Abstract: An apparatus and method for aligning the conductive pads of a ceramic module with contact points of a socket. The apparatus includes a ceramic module having a plurality of conductive pads. A plurality of rigid spheres are attached to some of the plurality of conductive pads. A socket having apertures and conductive test points receives the ceramic module. The apertures receive the rigid spheres of the ceramic module and align the conductive pads in registration with the plurality of conductive test points.

Abstract: The present invention provides a novel I/O pad structure and layout methodology which allows the effective wire bonding pitch to be reduced by circumventing the usual constraints of wire bonding technology. The bonding pad layout of the present invention entails the use of two rows of pads on the chip periphery as opposed to the more conventional single row, in-line arrangement. The bonding pads are arranged in a novel way, by radial staggering, to ensure no overlapping of bonding wire trajectories, even when conventional lead frames are used for the package. Comparing the radially staggered arrangement of the bonding pads of the present invention to convention single row, in-line bonding pad configuration, in the radially staggered arrangement every other pad is moved inward in the radial direction to form a second row. The radial direction used is from a projection point, typically the die center, and is dependent on the I/O circuitry height and the total number of pins of the package.

Abstract: A system and method for providing a controlled impedance flex circuit includes providing an insulative flexible substrate having opposed first and second surfaces and having through holes extending from the first surface to the second surface. A pattern of conductive traces is formed on the first surface of the flexible substrate. A film of conductive adhesive is applied to the second surface and to the through holes. The through holes are aligned to contact ground traces in the pattern of conductive traces on the first surface. Thus, a ground plane is established for creating an environment for high frequency signal propagation. The conductive adhesive may be a b-stage epoxy or a thermoplastic material. In the preferred embodiment, a tape automated bonding frame is fabricated.

Abstract: An electrical interconnection between a flip chip and a substrate. The interconnection includes a substrate having conductive pads to which wire bumps are attached. Each wire bump includes an elastically deformable stub section attached to the ball section, and a pointed tip. The pointed tip pierces a soft conductive layer located on a conductive pads of a flip chip. The elastic deformation of the stub section provides for consistent electrical connections between the flip chip and the substrate when the flip chip and the substrate are non-planar. An adhesive is located between the flip chip and the substrate and encompasses the wire bumps.

Abstract: The present invention provides an easily reworkable demountable means of electrically interconnecting an integrated circuit die to a substrate. The electrical assembly is comprised of an integrated circuit die having contact areas on a first surface, a substrate having contact areas aligned with the contact areas of the die for providing electrical connection to the integrated circuit die, and a compression means for maintaining the integrated circuit die contacts in electrical communication with the contacts of the substrate. The compression means typically includes a two-part spring system which provides superior electrical contact by causing the curvature of the integrated circuit die to be in the same direction as the curvature of the substrate.

Abstract: A thermally and electrically enhanced surface mount package with up to at least 600 I/O connections, but possessing the flexibility and simplicity of conventional leadframes. The package includes an integrated circuit die having a plurality of bonding pads, a conductive substrate having a cavity formed therein for receiving the integrated circuit die, and a flexible circuit laminated on the conductive substrate. The flexible circuit includes at least a wiring pattern and an area array of bumps formed on pads at the periphery of the flexible circuit. The flexible circuit may include a plurality of openings through the flexible circuit beneath certain of the pads or traces of the wiring pattern so as to ground the certain of the pads (ground pads) or traces to the conductive substrate.

Abstract: A system and method for providing a controlled impedance flex circuit includes providing an insulative flexible substrate having opposed first and second surfaces and having through holes extending from the first surface to the second surface. A pattern of conductive traces is formed on the first surface of the flexible substrate. A film of conductive adhesive is applied to the second surface and to the through holes. The through holes are aligned to contact ground traces in the pattern of conductive traces on the first surface. Thus, a ground plane is established for creating an environment for high frequency signal propagation. The conductive adhesive may be a b-stage epoxy or a thermoplastic material. In the preferred embodiment, a tape automated bonding frame is fabricated.

Abstract: A thermally and electrically enhanced surface mount package with up to at least 600 I/O connections, but possessing the flexibility and simplicity of conventional leadframes. The package includes an integrated circuit die having a plurality of bonding pads, a conductive substrate having a cavity formed therein for receiving the integrated circuit die, and a flexible circuit laminated on the conductive substrate. The flexible circuit includes at least a wiring pattern and an area array of bumps formed on pads at the periphery of the flexible circuit. The flexible circuit may include a plurality of openings through the flexible circuit beneath certain of the pads or traces of the wiring pattern so as to ground the certain of the pads (ground pads) or traces to the conductive substrate.