Patents by Inventor Rajendra D. Pendse

Rajendra D. Pendse has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5262925
    Abstract: The invention is embodied in a TAB frame with wide spaced area array contacts. The area array contacts serve to transform the narrow pitch contacts which connect to a chip mounted on the tab frame into wide spaced TAB edge contacts. These area array contacts allow for the convenient connection of the TAB frame to a printed circuit board and eliminate the need for fine line printed circuit board technology to support the TAB assembly.
    Type: Grant
    Filed: June 9, 1992
    Date of Patent: November 16, 1993
    Assignee: Hewlett-Packard Company
    Inventors: Farid Matta, Kevin Douglas, Rajendra D. Pendse, Brahram Afshari, Kenneth D. Scholz
  • Patent number: 5162975
    Abstract: The invention is embodied in a demountable TAB assembly. By using two springs in series, the present invention is able to maintain reliable contact between the TAB frame and the printed circuit board even if the elastomeric spring relaxes. The present invention also incorporates a novel TAB frame using contacts formed into an area-array. This area-array concept eliminated the need for fine line printed circuit board technology to support the TAB assembly.
    Type: Grant
    Filed: October 15, 1991
    Date of Patent: November 10, 1992
    Assignee: Hewlett-Packard Company
    Inventors: Farid Matta, Kevin Douglas, Rajendra D. Pendse, Brahram Afshari, Kenneth D. Scholz
  • Patent number: 5049976
    Abstract: An integrated circuit package (10) has a layer (22) of silicon positioned between copper die attach pad (18) and silicon integrated circuit die (12). The layer (22) should have a thickness of about half that of the silicon die (12). The layer (22) should also extend symmetrically beyond the die (12). Such an extension provides a horizontal surface beyond the die (12) to which thermosetting encapsulating resin (20) will adhere to produce an enhanced stress reduction effect. Vertical edges (23) of the layer (22) also help to prevent stress of the die (12) by resisting force from the encapsulating resin (20) after it shrinks during curing.
    Type: Grant
    Filed: January 10, 1989
    Date of Patent: September 17, 1991
    Assignee: National Semiconductor Corporation
    Inventors: Jeffrey C. Demmin, Rajendra D. Pendse