Abstract: A flip chip interconnect is made by mating the interconnect bump directly onto a lead, rather than onto a capture pad. Also, a flip chip package includes a die having solder bumps attached to interconnect pads in an active surface, and a substrate having electrically conductive traces in a die attach surface, in which the bumps are mated directly onto the traces. In some embodiments the interconnection is formed without employing a solder mask. In some methods a curable adhesive is dispensed either onto the bumps on the die or onto the traces on the substrate; the adhesive is partly cured during the mating process, and the partly cured adhesive serves to confine the molten solder during a reflow process.

Abstract: A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. Also, a bond-on-lead or bond-on-narrow pad or bond on a small area of a contact pad interconnection includes such tapering flip chip interconnects. Also, methods for making the interconnect structure include providing a die having interconnect pads, providing a substrate having interconnect sites on a patterned conductive layer, providing a bump on a die pad, providing a fusible electrically conductive material either at the interconnect site or on the bump, mating the bump to the interconnect site, and heating to melt the fusible material.

Abstract: A flip chip interconnect has a tapering interconnect structure, and the area of contact of the interconnect structure with the site on the substrate metallization is less than the area of contact of the interconnect structure with the die pad. A solder mask has an opening over the interconnect site, and the solder mask makes contact with the interconnect structure, or is in close proximity to the interconnect structure, at the margin of the opening. The flip chip interconnect is provided with an underfill. During the underfill process, the contact (or near proximity) of the solder mask with the interconnect structure interferes with flow of the underfill material toward the substrate adjacent the site, resulting in formation of a void left unfilled by the underfill, adjacent the contact of the interconnect structure with the site on the substrate metallization. The void can help provide relief from strain induced by changes in temperature of the system.

Abstract: An integrated circuit package system includes providing a substrate having a bond finger thereon and forming a pedestal on a portion of the bond finger. A first die is mounted on the substrate and adjacent to the bond finger. A portion of the first die, a portion of the bond finger, and a portion of the pedestal are embedded in an resin layer with an exposed portion of the pedestal protruding from the resin layer. A second die is mounted on the first die and electrically coupled to the exposed portion of the pedestal.

Abstract: A semiconductor package comprises a base substrate with a semiconductor die mounted on a top side of the base substrate and an interposer substrate mounted on top of the die. The bottom side of the interposer substrate can be electrically coupled to the top side of the base substrate through vertical connectors. The top side of the interposer substrate is substantially exposed and comprises input/output (I/O) terminals for the mounting of additional electronic components. The base and interposer substrates can be configured with I/O terminals such that components mounted on the substrates can be electrically coupled through the vertical connectors. The base substrate also can be electrically coupled to an additional electronic component, such as a printed circuit board. Electrical connections can be “wrapped around” from the base substrate to the top of the interposer substrate. The vertical connectors can be positioned along multiple sides of the package.

Abstract: A semiconductor device has a semiconductor die mounted to a substrate with a plurality of composite interconnects formed between interconnect sites on the substrate and bump pads on the die. The interconnect sites are part of traces formed on the substrate. The interconnect site has a width between 1.0 and 1.2 times a width of the trace. The composite interconnect is tapered. The composite interconnects have a fusible portion connected to the interconnect site and non-fusible portion connected to the bump pad. The non-fusible portion can be gold, copper, nickel, lead solder, or lead-tin alloy. The fusible portion can be tin, lead-free alloy, tin-silver alloy, tin-silver-copper alloy, tin-silver-indium alloy, eutectic solder, or other tin alloys with silver, copper, or lead. An underfill material is deposited between the semiconductor die and substrate. A finish such as Cu-OSP can be formed over the substrate.

Abstract: A semiconductor wafer contains a plurality of semiconductor die. A plurality of interconnect bump pads is formed over the semiconductor die. A plurality of sacrificial bump pads is formed in proximity to and diagonally offset with respect to the interconnect bump pads. The sacrificial bump pads have a different diameter than the interconnect bump pads. A conductive link is formed between each interconnect bump pad and proximate sacrificial bump pad. The sacrificial bump pads, interconnect bump pads, and conductive link are formed concurrently or during bump formation. The wafer is electrically tested by contacting the sacrificial bump pads. The electrical test identifies known good die and defective die. The sacrificial bump pads and a portion of the conductive link are removed after wafer probing. Bumps are formed over the interconnect bump pads. The semiconductor wafer can be sold or transferred to a third party after wafer probing without bumps.

Abstract: A semiconductor package comprises a base substrate with a semiconductor die mounted on a top side of the base substrate and an interposer substrate mounted on top of the die. The bottom side of the interposer substrate can be electrically coupled to the top side of the base substrate through vertical connectors. The top side of the interposer substrate is substantially exposed and comprises input/output (I/O) terminals for the mounting of additional electronic components. The base and interposer substrates can be configured with I/O terminals such that components mounted on the substrates can be electrically coupled through the vertical connectors. The base substrate also can be electrically coupled to an additional electronic component, such as a printed circuit board. Electrical connections can be “wrapped around” from the base substrate to the top of the interposer substrate.

Abstract: A semiconductor device is made by forming a conductive layer over a temporary carrier. The conductive layer includes a wettable pad. A stud bump is formed over the wettable pad. The stud bump can be a stud bump or stacked bumps. A semiconductor die is mounted to the carrier. An encapsulant is deposited over the semiconductor die and around the stud bump. A first interconnect structure is formed over a first surface of the encapsulant. The first interconnect structure includes a first IPD and is electrically connected to the stud bump. The carrier is removed. A second interconnect structure is formed over a second surface of encapsulant opposite the first interconnect structure. The second interconnect structure includes a second IPD. The first or second IPD includes a capacitor, resistor, or inductor. The semiconductor devices are stackable and electrically connected through the stud bump.

Abstract: A flip chip interconnect pad layout has the die signal pads are arranged on the die surface near the perimeter of the die, and the die power and ground pads arranged on the die surface inboard from the signal pads; and has the signal pads on the corresponding package substrate arranged in a manner complementary to the die pad layout and the signal lines routed from the signal pads beneath the die edge away from the die footprint, and has the power and ground lines routed to vias beneath the die footprint. Also, a flip chip semiconductor package in which the flip chip interconnect pad layouts have the die signal pads situated in the marginal part of the die and the die power and ground pads arranged on the die surface inboard from the signal pads, and the corresponding package substrates have signal pads arranged in a manner complementary to the die pad layout and signal lines routed from the signal pads beneath the die edge away from the die footprint.

Abstract: A semiconductor device is made by providing a semiconductor die having a contact pad, forming a circular solder bump on the contact pad, providing a substrate having a trace line, disposing a non-circular solder resist opening over the trace line, placing the solder bump in proximity to the trace line, and reflowing the circular solder bump to metallurgically connect the circular solder bump to the trace line. The circular solder bump contacts less than an entire perimeter of the non-circular solder resist opening which creates one or more vents in areas where the circular solder bump is discontinuous with the non-circular solder resist opening. The non-circular solder resist opening can be a rectangle, triangle, ellipse, oval, star, and tear-drop. An underfill material is deposited under the first substrate. The underfill material penetrates through the vents to fill an area under the solder bump.

Abstract: A semiconductor device has a semiconductor die with an die bump pad and substrate with a trace line and integrated bump pad. Conductive bump material is deposited on the substrate bump pad or die bump pad. The semiconductor die over the substrate so that the bump material is disposed between the die bump pad and substrate bump pad. The bump material is reflowed without a solder mask around the die bump pad or substrate bump pad to form an interconnect. The bump material is self-confined within a footprint of the die bump pad or substrate bump pad. The bump material can be immersed in a flux solution prior to reflow to increase wettability. Alternatively, the interconnect includes a non-fusible base and fusible cap. The volume of bump material is selected so that a surface tension maintains self-confinement of the bump material within the bump pads during reflow.

Abstract: A method of manufacture of an integrated circuit packaging system is provided including: providing a substrate; and placing a patterned layer over the substrate for substantially removing crying warpage from the substrate.

Abstract: A semiconductor package includes a semiconductor die with a plurality of solder bumps formed on bump pads. A substrate has a plurality of contact pads each with an exposed sidewall. A solder resist is disposed opening over at least a portion of each contact pad. The solder bumps are reflowed to metallurgically and electrically connect to the contact pads. Each contact pad is sized according to a design rule defined by SRO+2*SRR?2X, where SRO is the solder resist opening, SRR is a solder registration for the manufacturing process, and X is a function of a thickness of the exposed sidewall of the contact pad. The value of X ranges from 5 to 20 microns. The solder bump wets the exposed sidewall of the contact pad and substantially fills an area adjacent to the exposed sidewall. The contact pad can be made circular, rectangular, or donut-shaped.

Abstract: A flip chip interconnect is made by mating the interconnect bump directly onto a lead, rather than onto a capture pad. Also, a flip chip package includes a die having solder bumps attached to interconnect pads in an active surface, and a substrate having electrically conductive traces in a die attach surface, in which the bumps are mated directly onto the traces. In some embodiments the interconnection is formed without employing a solder mask. In some methods a curable adhesive is dispensed either onto the bumps on the die or onto the traces on the substrate; the adhesive is partly cured during the mating process, and the partly cured adhesive serves to confine the molten solder during a reflow process.

Abstract: A method for forming metallurgical interconnections and polymer adhesion of a flip chip to a substrate includes providing a chip having a set of bumps formed on a bump side thereof and a substrate having a set of interconnect points on a metallization thereon, providing a measured quantity of a polymer adhesive in a middle region of the chip on the bump side, aligning the chip with the substrate so that the set of bumps aligns with the set of interconnect points, pressing the chip and the substrate toward one another so that a portion of the polymer adhesive contacts the substrate and the bumps contact the interconnect points, and heating the bumps to a temperature sufficiently high to form a metallurgical connection between the bumps and the interconnect points. Also, a flip chip package is made by the method. In some embodiments the metallurgical connection includes an alloy of gold and tin at the interface between the bumps and the interconnect points.

Abstract: A method of manufacture of an integrated circuit package-on-package system includes providing a base package and providing solder caps on the top of the base package configured to protrude above subsequent resin bleed, the resin bleed extending to an edge of the base package, and configured for merging with solder balls of a top package to form larger solder balls between such a top package and the base package.

Abstract: A flip chip interconnect pad layout has the die signal pads are arranged on the die surface near the perimeter of the die, and the die power and ground pads arranged on the die surface inboard from the signal pads; and has the signal pads on the corresponding package substrate arranged in a manner complementary to the die pad layout and the signal lines routed from the signal pads beneath the die edge away from the die footprint, and has the power and ground lines routed to vias beneath the die footprint. Also, a flip chip semiconductor package in which the flip chip interconnect pad layouts have the die signal pads situated in the marginal part of the die and the die power and ground pads arranged on the die surface inboard from the signal pads, and the corresponding package substrates have signal pads arranged in a manner complementary to the die pad layout and signal lines routed from the signal pads beneath the die edge away from the die footprint.

Abstract: A solder mask for flip chip interconnection has a common opening that spans a plurality of circuit elements. The solder mask allows confinement of the solder during the remelt stage of interconnection, yet it is within common design rules for solder mask patterning. Also, a substrate for flip chip interconnection includes a substrate having the common opening that spans a plurality of circuit elements. Also, a flip chip package includes a substrate having a common opening that spans a plurality of circuit elements.

Abstract: A package-on-package system is provided with a base package. Solder caps are provided on the top of the base package. The solder caps are configured to protrude above subsequent resin bleed, and are configured for merging with solder balls of a top package to form larger solder balls between such a top package and the base package.