Patents by Inventor Rajesh Khamankar

Rajesh Khamankar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020197886
    Abstract: An embodiment of the present invention is a method of forming an ultra-thin dielectric layer, the method comprising the steps of: providing a substrate having a semiconductor surface; forming an oxygen-containing layer on the semiconductor surface; exposing the oxygen-containing layer to a nitrogen-containing plasma to create a uniform nitrogen distribution throughout the oxygen-containing layer; and re-oxidizing and annealing the layer to stabilize the nitrogen distribution, heal plasma-induced damage, and reduce interfacial defect density.
    Type: Application
    Filed: June 20, 2001
    Publication date: December 26, 2002
    Inventors: Hiroaki Niimi, Rajesh Khamankar, James J. Chambers, Sunil Hattangady, Antonio L.P. Rotondaro
  • Patent number: 6342420
    Abstract: An apparatus and method for fabrication a hexagonally symmetric cell, (e.g., a dynamic random access memory cell (100)). The cell can comprise a bitline contact (38), storage node contacts (32) hexagonally surrounding the bitline contact (38), storage nodes (36) also surrounding the bitline contact (38), a wordline (30) portions of which form field effect transistor gates. Large distances between bitline contacts (38) and storage node contact (32) cause large problems during photolithography because dark areas are difficult to achieve when using Levenson Phaseshift. Because Levenson Phaseshift depends on wave cancellations between nearby features, commonly known as destructive interferences, the resultant printability of the pattern is largely a function of the symmetry and separation distances. When non-symmetries in the pattern occur, the result is weaker cancellations of fields (i.e. between features) and a large loss of image contrast and depth of focus during the printing step.
    Type: Grant
    Filed: April 3, 2000
    Date of Patent: January 29, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Akitoshi Nishimura, Yasutoshi Okuno, Rajesh Khamankar, Shane R. Palmer
  • Patent number: 6166408
    Abstract: An apparatus and method for fabrication a hexagonally symmetric cell, (e.g., a dynamic random access memory cell (100)). The cell can comprise a bitline contact (38), storage node contacts (32) hexagonally surrounding the bitline contact (38), storage nodes (36) also surrounding the bitline contact (38), a wordline (30) portions of which form field effect transistor gates. Large distances between bitline contacts (38) and storage node contacts (32) cause large problems during photolithography because dark areas are difficult to achieve when using Levenson Phaseshift. Because Levenson Phaseshift depends on wave cancellations between nearby features, commonly known as destructive interferences, the resultant printability of the pattern is largely a function of the symmetry and separation distances. When non-symmetries in the pattern occur, the result is weaker cancellations of fields (i.e. between features) and a large loss of image contrast and depth of focus during the printing step.
    Type: Grant
    Filed: December 18, 1998
    Date of Patent: December 26, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Akitoshi Nishimura, Yasutoshi Okuno, Rajesh Khamankar, Shane R. Palmer
  • Patent number: 6153490
    Abstract: A method for etching a feature in a platinum layer 834 overlying a second material 818 without substantially etching the second material. The method includes the the steps of: forming an adhesion-promoting layer 824 between the platinum layer and the second material; forming a hardmask layer 829 over the platinum layer; patterning and etching the hardmask layer in accordance with desired dimensions of the feature; and etching portions of the platinum layer not covered by the hardmask layer 832, the etching stopping on the adhesion-promoting layer. In further embodiments the adhesion-promoting and hardmask layers are Ti--Al--N including at least 1% of aluminum.
    Type: Grant
    Filed: June 26, 1998
    Date of Patent: November 28, 2000
    Assignee: Texas Instruments Incorporated
    Inventors: Guoqiang Xing, Scott R. Summerfelt, Rajesh Khamankar