Patents by Inventor Rajesh Narwal
Rajesh Narwal has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11827706Abstract: Provided herein are methods of treating B7-H1-expressing tumors comprising administering an effective amount of MEDI4736 or an antigen-binding fragment thereof.Type: GrantFiled: October 16, 2020Date of Patent: November 28, 2023Inventors: Rajesh Narwal, David Fairman, Paul Robbins, Meina Liang, Amy Schneider, Carlos Chavez, Carina Herl, Min Pak, Hong Lu, Marlon Rebelatto, Keith Steele, Anmarie Boutrin, Li Shi, Shengyan Hong, Brandon Higgs, Lorin Roskos
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Patent number: 11726514Abstract: An active compensation circuit for compensating the stability of a regulator is provided. The active compensation circuit presents an equivalent capacitance and an equivalent resistance and compensates stability of system using the equivalent capacitance and the equivalent resistance. The regulator includes a power transistor that receives a driving signal and channelize the required current to the Ips driven by this block. The regulator's stability is compensated using the active compensation circuit to provide an accurate output voltage without significantly compromising the accuracy (load regulation) and area of the system.Type: GrantFiled: April 27, 2021Date of Patent: August 15, 2023Assignee: STMicroelectronics International N.V.Inventors: Shashwat, Rajesh Narwal
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Publication number: 20230168300Abstract: An assembly for detecting a structural defect in a semiconductor die is provided. The assembly includes a defect-detection sensor and a microcontroller. The defect-detection sensor includes a plurality of resistive paths of electrical-conductive material in the semiconductor die, each of which has a first end and a second end and extends proximate a perimeter of the semiconductor die. The defect-detection sensor includes a plurality of signal-generation structures, each coupled to a respective resistive path and configured to supply a test signal to the resistive path. The microcontroller is configured to control the signal-generation structures to generate the test signals, acquire the test signals in each resistive paths, test an electrical feature of the resistive paths by performing an analysis of the test signals acquired and detect the presence of the structural defect in the semiconductor die based on a result of the analysis of the test signals acquired.Type: ApplicationFiled: November 8, 2022Publication date: June 1, 2023Applicants: STMICROELECTRONICS S.r.l., STMicroelectronics International N.V.Inventors: Mauro GIACOMINI, Fabio Enrico Carlo DISEGNI, Rajesh NARWAL, Pravesh Kumar SAINI, Mayankkumar HARESHBHAI NIRANJANI
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Publication number: 20230115328Abstract: Provided herein are methods of treating non-small cell lung cancers comprising administering an effective amount of MEDI4736 or an antigen-binding fragment thereof and tremelimumab or an antigen-binding fragment thereof.Type: ApplicationFiled: August 9, 2022Publication date: April 13, 2023Inventors: RAJESH NARWAL, PAUL ROBBINS, JOYSON KARAKUNNEL, MOHAMMED DAR
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Publication number: 20220350357Abstract: An active compensation circuit for compensating the stability of a regulator is provided. The active compensation circuit presents an equivalent capacitance and an equivalent resistance and compensates stability of system using the equivalent capacitance and the equivalent resistance. The regulator includes a power transistor that receives a driving signal and channelize the required current to the Ips driven by this block. The regulator's stability is compensated using the active compensation circuit to provide an accurate output voltage without significantly compromising the accuracy (load regulation) and area of the system.Type: ApplicationFiled: April 27, 2021Publication date: November 3, 2022Inventors: Shashwat, Rajesh Narwal
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Patent number: 11446377Abstract: Provided herein are methods of treating non-small cell lung cancers comprising administering an effective amount of MEDI4736 or an antigen-binding fragment thereof and tremelimumab or an antigen-binding fragment thereof.Type: GrantFiled: January 24, 2019Date of Patent: September 20, 2022Assignee: MEDIMMUNE, LLCInventors: Rajesh Narwal, Paul Robbins, Joyson Karakunnel, Mohammed Dar
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Publication number: 20220276302Abstract: Circuits and methods for testing voltage monitor circuits are provided. In one embodiment, a method includes setting voltage monitor circuits to test mode; setting, a monitor reference in each voltage monitor circuit, to a respective targeted threshold voltage using a corresponding trim code; ramping, a voltage provided to a subset of voltage monitor circuits, from a first voltage to a second voltage using a test voltage supply, voltages between the first voltage and the second voltage corresponding with targeted threshold voltages of the subset of voltage monitor circuits; determining, for each voltage monitor circuit in the subset of voltage monitor circuits, a voltage value of the test voltage supply resulting in a change in a logic state at an output of a corresponding voltage monitor circuit.Type: ApplicationFiled: May 16, 2022Publication date: September 1, 2022Inventors: Rajesh Narwal, Venkata Narayanan Srinivasan, Srinivas Dhulipalla
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Patent number: 11340292Abstract: Circuits and methods for testing voltage monitor circuits are provided. In one embodiment, a method includes setting voltage monitor circuits to test mode; setting, a monitor reference in each voltage monitor circuit, to a respective targeted threshold voltage using a corresponding trim code; ramping, a voltage provided to a subset of voltage monitor circuits, from a first voltage to a second voltage using a test voltage supply, voltages between the first voltage and the second voltage corresponding with targeted threshold voltages of the subset of voltage monitor circuits; determining, for each voltage monitor circuit in the subset of voltage monitor circuits, a voltage value of the test voltage supply resulting in a change in a logic state at an output of a corresponding voltage monitor circuit.Type: GrantFiled: July 9, 2019Date of Patent: May 24, 2022Assignee: STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Rajesh Narwal, Venkata Narayanan Srinivasan, Srinivas Dhulipalla
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Publication number: 20210171639Abstract: Provided herein are methods of treating B7-H1-expressing tumors comprising administering an effective amount of MEDI4736 or an antigen-binding fragment thereof.Type: ApplicationFiled: October 16, 2020Publication date: June 10, 2021Inventors: RAJESH NARWAL, DAVID FAIRMAN, PAUL ROBBINS, MEINA LIANG, AMY SCHNEIDER, CARLOS CHAVEZ, CARINA HERL, MIN PAK, HONG LU, MARLON REBELATTO, KEITH STEELE, ANMARIE BOUTRIN, LI SHI, SHENGYAN HONG, BRANDON HIGGS, LORIN ROSKOS
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Patent number: 10996266Abstract: Circuits and methods for testing voltage monitor circuits are provided. In an embodiment, an integrated circuit (IC) includes power management unit (PMU), a set-reset (S-R) latch circuit, a multiplexer, and an AND gate circuit. A voltage monitor circuit of the PMU generates an output signal based on a difference between a received reference voltage and a received sense voltage from a functional supply. A power on reset (PoR) generator of the PMU generates a PoR signal based on a power up condition of the PMU. The S-R latch circuit generates an enable signal based on the output signal of the comparator circuit and the PoR signal. The multiplexer passes-through the output signal of the comparator circuit during a functional condition of the PMU. The AND gate circuit generates an enable signal based on an output of the multiplexer and an output of the S-R latch circuit.Type: GrantFiled: August 9, 2019Date of Patent: May 4, 2021Assignee: STMICROELECTRONICS INTERNATIONAL N.V.Inventors: Venkata Narayanan Srinivasan, Rajesh Narwal, Srinivas Dhulipalla
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Publication number: 20210041496Abstract: Circuits and methods for testing voltage monitor circuits are provided. In an embodiment, an integrated circuit (IC) includes power management unit (PMU), a set-reset (S-R) latch circuit, a multiplexer, and an AND gate circuit. A voltage monitor circuit of the PMU generates an output signal based on a difference between a received reference voltage and a received sense voltage from a functional supply. A power on reset (PoR) generator of the PMU generates a PoR signal based on a power up condition of the PMU. The S-R latch circuit generates an enable signal based on the output signal of the comparator circuit and the PoR signal. The multiplexer passes-through the output signal of the comparator circuit during a functional condition of the PMU. The AND gate circuit generates an enable signal based on an output of the multiplexer and an output of the S-R latch circuit.Type: ApplicationFiled: August 9, 2019Publication date: February 11, 2021Inventors: Venkata Narayanan Srinivasan, Rajesh Narwal, Srinivas Dhulipalla
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Publication number: 20210011080Abstract: Circuits and methods for testing voltage monitor circuits are provided. In one embodiment, a method includes setting voltage monitor circuits to test mode; setting, a monitor reference in each voltage monitor circuit, to a respective targeted threshold voltage using a corresponding trim code; ramping, a voltage provided to a subset of voltage monitor circuits, from a first voltage to a second voltage using a test voltage supply, voltages between the first voltage and the second voltage corresponding with targeted threshold voltages of the subset of voltage monitor circuits; determining, for each voltage monitor circuit in the subset of voltage monitor circuits, a voltage value of the test voltage supply resulting in a change in a logic state at an output of a corresponding voltage monitor circuit.Type: ApplicationFiled: July 9, 2019Publication date: January 14, 2021Applicant: STMicroelectronics International N.V.Inventors: Rajesh Narwal, Venkata Narayanan Srinivasan, Srinivas Dhulipalla
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Patent number: 10886931Abstract: A circuit includes analog input nodes and switches selectively coupling each of the analog input nodes to a capacitive node. Each of the switches is controlled by a respective bit of a channel selection word. Level shifting circuits are respectively coupled in parallel with the switches. A sampling capacitor is coupled between an output node and ground, the output node being coupled to the capacitive node. An analog to digital converter operates to digitize voltages at the output node.Type: GrantFiled: July 24, 2020Date of Patent: January 5, 2021Assignee: STMicroelectronics International N.V.Inventors: Rajesh Narwal, Kavindu Shekhar Benjwal
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Patent number: 10829557Abstract: Provided herein are methods of treating B7-H1-expressing tumors comprising administering an effective amount of MEDI4736 or an antigen-binding fragment thereof.Type: GrantFiled: May 21, 2019Date of Patent: November 10, 2020Assignee: MEDIMMUNE LIMITEDInventors: Rajesh Narwal, David Fairman, Paul Robbins, Meina Liang, Amy Schneider, Carlos Chavez, Carina Herl, Min Pak, Hong Lu, Marlon Rebelatto, Keith Steele, Anmarie Boutrin, Li Shi, Shengyan Hong, Brandon Higgs, Lorin Roskos
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Patent number: 10771082Abstract: An analog-to-digital converter includes a sampling capacitor connected to a multiplexer output, discharge circuitry discharging the sampling capacitor during a first period beginning at a start of a sampling cycle, and level shifting circuitry charging the sampling capacitor to a voltage at a first analog input node modified by a mismatch voltage resulting from mismatch in threshold voltages between a first transistor connected to the first analog input node and a second transistor connected to the output node, during a second period beginning at expiration of the first period. A first switch connects the first analog input node to the output node to charge the sampling capacitor to the voltage at the first analog input node, at expiration of the second period, and disconnects the first analog input node from the output node at an end of the sampling cycle of the analog-to-digital converter.Type: GrantFiled: September 4, 2019Date of Patent: September 8, 2020Assignee: STMicroelectronics International N.V.Inventors: Rajesh Narwal, Kavindu Shekhar Benjwal
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Patent number: 10680587Abstract: An RC oscillator generates a periodic trigger signal, and a clock generator generates clock edges in response. A stuck-at-fault detection circuit detects a stuck-at-logic state of the periodic trigger signal and causes the RC oscillator to reset and causes a change in logic state of the periodic trigger signal. The RC oscillator includes first and second comparison circuits, a logic circuit receiving output from the first and second comparison circuits and generating the periodic trigger signal, and a clock generation circuit generating a clock signal therefrom. The stuck-at-fault detection circuit includes a capacitive node, charge circuitry charging the capacitive node based upon the periodic trigger signal, discharge circuitry discharging the capacitive node based upon the periodic trigger signal, and triggering circuitry asserting a reset signal to cause the RC oscillator to reset when the charge on the capacitive node indicates a stuck-at-logic state of the periodic trigger signal.Type: GrantFiled: July 5, 2018Date of Patent: June 9, 2020Assignee: STMicroelectronics International N.V.Inventors: Rajesh Narwal, Pravesh Kumar Saini
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Patent number: 10651641Abstract: A circuit includes an input terminal and a regulated supply line for supplying an electronic device with an electrostatic discharge protection and driver circuit for the electronic device. The supply line is coupled to the input terminal via the circuitry, so that current injected into the input terminal may produce a voltage increase on the regulated supply line. A comparator sensitive to the voltage at the input terminal and the voltage on the supply line is provided. A current sink coupled with the supply line and being activatable to sink current from the supply line is also provided. The comparator is configured for activating the current sink as a result of the voltage at the input terminal exceeding the voltage on the supply line of a certain intervention threshold.Type: GrantFiled: June 29, 2017Date of Patent: May 12, 2020Assignees: STMICROELECTRONICS INTERNATIONAL N.V., STMICROELECTRONICS S.R.L.Inventors: Mauro Giacomini, Rajesh Narwal, Pravesh Kumar Saini
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Publication number: 20200014372Abstract: An RC oscillator generates a periodic trigger signal, and a clock generator generates clock edges in response. A stuck-at-fault detection circuit detects a stuck-at-logic state of the periodic trigger signal and causes the RC oscillator to reset and causes a change in logic state of the periodic trigger signal. The RC oscillator includes first and second comparison circuits, a logic circuit receiving output from the first and second comparison circuits and generating the periodic trigger signal, and a clock generation circuit generating a clock signal therefrom. The stuck-at-fault detection circuit includes a capacitive node, charge circuitry charging the capacitive node based upon the periodic trigger signal, discharge circuitry discharging the capacitive node based upon the periodic trigger signal, and triggering circuitry asserting a reset signal to cause the RC oscillator to reset when the charge on the capacitive node indicates a stuck-at-logic state of the periodic trigger signal.Type: ApplicationFiled: July 5, 2018Publication date: January 9, 2020Applicant: STMicroelectronics International N.V.Inventors: Rajesh Narwal, Pravesh Kumar Saini
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Publication number: 20190338033Abstract: Provided herein are methods of treating B7-H1-expressing tumors comprising administering an effective amount of MEDI4736 or an antigen-binding fragment thereof.Type: ApplicationFiled: May 21, 2019Publication date: November 7, 2019Inventors: Rajesh Narwal, David Fairman, Paul Robbins, Meina Liang, Amy Schneider, Carlos Chavez, Carina Herl, Min Pak, Hong Lu, Marlon Rebelatto, Keith Steele, Anmarie Boutrin, Li Shi, Shengyan Hong, Brandon Higgs, Lorin Roskos
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Publication number: 20190240324Abstract: Provided herein are methods of treating non-small cell lung cancers comprising administering an effective amount of MEDI4736 or an antigen-binding fragment thereof and tremelimumab or an antigen-binding fragment thereof.Type: ApplicationFiled: January 24, 2019Publication date: August 8, 2019Inventors: RAJESH NARWAL, PAUL ROBBINS, JOYSON KARAKUNNEL, MOHAMMED DAR