Abstract: An assembly for detecting a structural defect in a semiconductor die is provided. The assembly includes a defect-detection sensor and a microcontroller. The defect-detection sensor includes a plurality of resistive paths of electrical-conductive material in the semiconductor die, each of which has a first end and a second end and extends proximate a perimeter of the semiconductor die. The defect-detection sensor includes a plurality of signal-generation structures, each coupled to a respective resistive path and configured to supply a test signal to the resistive path. The microcontroller is configured to control the signal-generation structures to generate the test signals, acquire the test signals in each resistive paths, test an electrical feature of the resistive paths by performing an analysis of the test signals acquired and detect the presence of the structural defect in the semiconductor die based on a result of the analysis of the test signals acquired.

Abstract: An example circuit and an electrical system utilizing test control circuitry to manage the transmission of electrical test signals between an integrated circuit and a main board are provided. The circuit includes test control circuitry configured to selectively transmit electrical test signals between an IC and a pad interface based on a plurality of asynchronous electrical supplies, at least one of which exceeds a maximum voltage rating of the test control circuitry. The test control circuitry includes first and second switching stage circuitry enabling electrical flow through the circuit based on first and second asynchronous electrical supply voltages. Intermediate biasing circuitry further defines an intermediate voltage between the first switching stage circuitry and the second switching stage circuitry.

Abstract: An example power management unit utilizing an example circuit to disable a voltage regulator is provided. The example circuit includes a voltage selection circuit and a power-down switching device. The voltage selection circuit configured to receive a first voltage source and a second voltage source to output a selected voltage based on the higher of the two input voltages. The voltage selection circuit utilizes a first transistor electrically connected in parallel with a second transistor between the first voltage source and the second voltage source to generate the selected voltage. The second transistor gate voltage at the second transistor gate is generated based at least in part on a voltage at the first transistor drain. The selected voltage is generated based on a voltage at the second transistor drain. The power-down switching device is configured to generate a voltage for a voltage regulator based on the selected voltage.

Abstract: A supply voltage detector of an integrated circuit is able to detect the state of a supply voltage upon startup with both high-speed and low overall power consumption. The supply voltage detector includes a comparator that generates an output voltage based on the current state of the supply voltage. The comparator includes a startup current booster that generates a supplemental current for the comparator while the supply voltage is ramping up. The start of current booster stops generating the supplemental current when the supply voltage reaches the expected steady-state value or a selected fraction or portion of the expected steady-state value.

Abstract: The present disclosure is directed to a fully analog voltage regulator circuit with reference modulation. The voltage regulator circuit includes a low-dropout regulator, a voltage-to-current convert, a resistor-capacitor filter circuit, and an operational amplifier voltage buffer. The voltage regulator circuit minimizes dropout voltage of the circuit by comparing the output voltage of the voltage regulator to a reference voltage and adjusting the output voltage of the op amp voltage buffer, accordingly. The voltage regulator circuit includes two operational amplifiers, wherein the negative input of a first of the two operational amplifiers is coupled to the negative input of a second of the two operational amplifiers through the resistor-capacitor filter circuit.

Abstract: Circuits and methods for testing voltage monitor circuits are provided. In one embodiment, a method includes setting voltage monitor circuits to test mode; setting, a monitor reference in each voltage monitor circuit, to a respective targeted threshold voltage using a corresponding trim code; ramping, a voltage provided to a subset of voltage monitor circuits, from a first voltage to a second voltage using a test voltage supply, voltages between the first voltage and the second voltage corresponding with targeted threshold voltages of the subset of voltage monitor circuits; determining, for each voltage monitor circuit in the subset of voltage monitor circuits, a voltage value of the test voltage supply resulting in a change in a logic state at an output of a corresponding voltage monitor circuit.

Abstract: An example power management unit utilizing an example circuit to disable a voltage regulator is provided. The example circuit includes a voltage selection circuit and a power-down switching device. The voltage selection circuit configured to receive a first voltage source and a second voltage source to output a selected voltage based on the higher of the two input voltages. The voltage selection circuit utilizes a first transistor electrically connected in parallel with a second transistor between the first voltage source and the second voltage source to generate the selected voltage. The second transistor gate voltage at the second transistor gate is generated based at least in part on a voltage at the first transistor drain. The selected voltage is generated based on a voltage at the second transistor drain. The power-down switching device is configured to generate a voltage for a voltage regulator based on the selected voltage.

Abstract: The present disclosure is directed to a fully analog voltage regulator circuit with reference modulation. The voltage regulator circuit includes a low-dropout regulator, a voltage-to-current convert, a resistor-capacitor filter circuit, and an operational amplifier voltage buffer. The voltage regulator circuit minimizes dropout voltage of the circuit by comparing the output voltage of the voltage regulator to a reference voltage and adjusting the output voltage of the op amp voltage buffer, accordingly. The voltage regulator circuit includes two operational amplifiers, wherein the negative input of a first of the two operational amplifiers is coupled to the negative input of a second of the two operational amplifiers through the resistor-capacitor filter circuit.

Abstract: A supply voltage detector of an integrated circuit is able to detect the state of a supply voltage upon startup with both high-speed and low overall power consumption. The supply voltage detector includes a comparator that generates an output voltage based on the current state of the supply voltage. The comparator includes a startup current booster that generates a supplemental current for the comparator while the supply voltage is ramping up. The start of current booster stops generating the supplemental current when the supply voltage reaches the expected steady-state value or a selected fraction or portion of the expected steady-state value.

Abstract: Provided herein are methods of treating B7-H1-expressing tumors comprising administering an effective amount of MEDI4736 or an antigen-binding fragment thereof.

Abstract: An active compensation circuit for compensating the stability of a regulator is provided. The active compensation circuit presents an equivalent capacitance and an equivalent resistance and compensates stability of system using the equivalent capacitance and the equivalent resistance. The regulator includes a power transistor that receives a driving signal and channelize the required current to the Ips driven by this block. The regulator's stability is compensated using the active compensation circuit to provide an accurate output voltage without significantly compromising the accuracy (load regulation) and area of the system.

Abstract: An assembly for detecting a structural defect in a semiconductor die is provided. The assembly includes a defect-detection sensor and a microcontroller. The defect-detection sensor includes a plurality of resistive paths of electrical-conductive material in the semiconductor die, each of which has a first end and a second end and extends proximate a perimeter of the semiconductor die. The defect-detection sensor includes a plurality of signal-generation structures, each coupled to a respective resistive path and configured to supply a test signal to the resistive path. The microcontroller is configured to control the signal-generation structures to generate the test signals, acquire the test signals in each resistive paths, test an electrical feature of the resistive paths by performing an analysis of the test signals acquired and detect the presence of the structural defect in the semiconductor die based on a result of the analysis of the test signals acquired.

Abstract: Provided herein are methods of treating non-small cell lung cancers comprising administering an effective amount of MEDI4736 or an antigen-binding fragment thereof and tremelimumab or an antigen-binding fragment thereof.

Abstract: An active compensation circuit for compensating the stability of a regulator is provided. The active compensation circuit presents an equivalent capacitance and an equivalent resistance and compensates stability of system using the equivalent capacitance and the equivalent resistance. The regulator includes a power transistor that receives a driving signal and channelize the required current to the Ips driven by this block. The regulator's stability is compensated using the active compensation circuit to provide an accurate output voltage without significantly compromising the accuracy (load regulation) and area of the system.

Abstract: Provided herein are methods of treating non-small cell lung cancers comprising administering an effective amount of MEDI4736 or an antigen-binding fragment thereof and tremelimumab or an antigen-binding fragment thereof.

Abstract: Circuits and methods for testing voltage monitor circuits are provided. In one embodiment, a method includes setting voltage monitor circuits to test mode; setting, a monitor reference in each voltage monitor circuit, to a respective targeted threshold voltage using a corresponding trim code; ramping, a voltage provided to a subset of voltage monitor circuits, from a first voltage to a second voltage using a test voltage supply, voltages between the first voltage and the second voltage corresponding with targeted threshold voltages of the subset of voltage monitor circuits; determining, for each voltage monitor circuit in the subset of voltage monitor circuits, a voltage value of the test voltage supply resulting in a change in a logic state at an output of a corresponding voltage monitor circuit.

Abstract: Circuits and methods for testing voltage monitor circuits are provided. In one embodiment, a method includes setting voltage monitor circuits to test mode; setting, a monitor reference in each voltage monitor circuit, to a respective targeted threshold voltage using a corresponding trim code; ramping, a voltage provided to a subset of voltage monitor circuits, from a first voltage to a second voltage using a test voltage supply, voltages between the first voltage and the second voltage corresponding with targeted threshold voltages of the subset of voltage monitor circuits; determining, for each voltage monitor circuit in the subset of voltage monitor circuits, a voltage value of the test voltage supply resulting in a change in a logic state at an output of a corresponding voltage monitor circuit.

Abstract: Provided herein are methods of treating B7-H1-expressing tumors comprising administering an effective amount of MEDI4736 or an antigen-binding fragment thereof.

Abstract: Circuits and methods for testing voltage monitor circuits are provided. In an embodiment, an integrated circuit (IC) includes power management unit (PMU), a set-reset (S-R) latch circuit, a multiplexer, and an AND gate circuit. A voltage monitor circuit of the PMU generates an output signal based on a difference between a received reference voltage and a received sense voltage from a functional supply. A power on reset (PoR) generator of the PMU generates a PoR signal based on a power up condition of the PMU. The S-R latch circuit generates an enable signal based on the output signal of the comparator circuit and the PoR signal. The multiplexer passes-through the output signal of the comparator circuit during a functional condition of the PMU. The AND gate circuit generates an enable signal based on an output of the multiplexer and an output of the S-R latch circuit.

Abstract: Circuits and methods for testing voltage monitor circuits are provided. In an embodiment, an integrated circuit (IC) includes power management unit (PMU), a set-reset (S-R) latch circuit, a multiplexer, and an AND gate circuit. A voltage monitor circuit of the PMU generates an output signal based on a difference between a received reference voltage and a received sense voltage from a functional supply. A power on reset (PoR) generator of the PMU generates a PoR signal based on a power up condition of the PMU. The S-R latch circuit generates an enable signal based on the output signal of the comparator circuit and the PoR signal. The multiplexer passes-through the output signal of the comparator circuit during a functional condition of the PMU. The AND gate circuit generates an enable signal based on an output of the multiplexer and an output of the S-R latch circuit.