Patents by Inventor Rajiv V. Joshi

Rajiv V. Joshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10998854
    Abstract: Semiconductor devices and methods relating to the semiconductor devices are provided. A semiconductor device includes a resonant clock circuit. The semiconductor device further includes an inductor. The semiconductor device also includes a magnetic layer formed of a magnetic material disposed in between a portion of the resonant clock circuit and the inductor. Clock signals of the resonant clock circuit are utilized by the magnetic layer.
    Type: Grant
    Filed: June 2, 2017
    Date of Patent: May 4, 2021
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce B. Doris, Rajiv V. Joshi, Naigang Wang
  • Patent number: 10797642
    Abstract: Semiconductor devices and methods relating to the semiconductor devices are provided. A semiconductor device includes a resonant clock circuit. The semiconductor device further includes an inductor. The semiconductor device also includes a magnetic layer formed of a magnetic material disposed in between a portion of the resonant clock circuit and the inductor. Clock signals of the resonant clock circuit are utilized by the magnetic layer.
    Type: Grant
    Filed: December 14, 2017
    Date of Patent: October 6, 2020
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce B. Doris, Rajiv V. Joshi, Naigang Wang
  • Patent number: 10755317
    Abstract: Disclosed aspects relate to managing a set of offers using a dialogue. An adaptive profile may be received with respect to a client. The adaptive profile may indicate a set of client profile data, a set of client event data, and a set of client context data. A dialogue may be established with the client based on the adaptive profile. A set of offers may be resolved by an offer management engine based on the dialogue. The set of offers may be presented to the client.
    Type: Grant
    Filed: March 11, 2017
    Date of Patent: August 25, 2020
    Assignee: International Business Machines Corporation
    Inventors: Swaminathan Balasubramanian, Avijit Chatterjee, Rajiv V. Joshi, John J. Thomas
  • Publication number: 20190370100
    Abstract: A mechanism is provided for reusing importance sampling for efficient cell failure rate estimation of process variations and other design considerations. First, the mechanism performs a search across circuit parameters to determine failures with respect to a set of performance variables. For a single failure region, the initial search may be a uniform sampling of the parameter space. Mixture importance sampling (MIS) efficiently may estimate the single failure region. The mechanism then finds a center of gravity for each metric and finds importance samples. Then, for each new origin corresponding to a process variation or other design consideration, the mechanism finds a suitable projection and recomputes new importance sampling (IS) ratios.
    Type: Application
    Filed: August 19, 2019
    Publication date: December 5, 2019
    Inventors: Rajiv V. Joshi, Rouwaida N. Kanj, Sani R. Nassif, Carl J. Radens
  • Patent number: 10452793
    Abstract: In one example, a method for evaluating a system includes obtaining a model of the system that defines a boundary between at least one failure region and a non-failure region for a performance indicator with respect to at least one variable of the system. In one embodiment, obtaining the model involves constructing a new model; however, in other embodiments, obtaining the model involves accepting or retrieving a pre-constructed model is input. The method further includes obtaining importance samples for the at least one variable that are biased to the at least one failure region, and calculating indicator values for the performance indicator by applying the importance samples to the model.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: October 22, 2019
    Assignee: International Business Machines Corporation
    Inventors: Rajiv V. Joshi, Yefim Shuf, Jonathan Sloan
  • Patent number: 10439046
    Abstract: The present invention provides for a method of fabricating a semiconductor device, the method includes depositing a nitride layer on an ETSOI layer; forming a dummy gate over the nitride layer; forming nitride gate spacers from the nitride layer; growing a sacrificial layer on the ETSOI layer, the sacrificial layer composing a material that can be at least partially converted to a metal layer by a metal-bearing gas; forming refractory metal contacts using the sacrificial layer and a consumptive process; depositing an oxide protect layer on the refractory metal contacts; removing the dummy gate using a mask and etch process combined with chemical-mechanical polishing (CMP); etching the ETSOI layer to form a U-shaped channel; and depositing the final gate stack into the U-shaped channel.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: October 8, 2019
    Assignee: International Business Machines Corporation
    Inventors: Robert H. Dennard, Rajiv V. Joshi, Richard Q. Williams
  • Publication number: 20190288091
    Abstract: The present invention provides for a method of fabricating a semiconductor device, the method includes depositing a nitride layer on an ETSOI layer; forming a dummy gate over the nitride layer; forming nitride gate spacers from the nitride layer; growing a sacrificial layer on the ETSOI layer, the sacrificial layer composing a material that can be at least partially converted to a metal layer by a metal-bearing gas; forming refractory metal contacts using the sacrificial layer and a consumptive process; depositing an oxide protect layer on the refractory metal contacts; removing the dummy gate using a mask and etch process combined with chemical-mechanical polishing (CMP); etching the ETSOI layer to form a U-shaped channel; and depositing the final gate stack into the U-shaped channel.
    Type: Application
    Filed: March 15, 2018
    Publication date: September 19, 2019
    Inventors: Robert H. Dennard, Rajiv V. Joshi, Richard Q. Williams
  • Patent number: 10387235
    Abstract: A mechanism is provided for reusing importance sampling for efficient cell failure rate estimation of process variations and other design considerations. First, the mechanism performs a search across circuit parameters to determine failures with respect to a set of performance variables. For a single failure region, the initial search may be a uniform sampling of the parameter space. Mixture importance sampling (MIS) efficiently may estimate the single failure region. The mechanism then finds a center of gravity for each metric and finds importance samples. Then, for each new origin corresponding to a process variation or other design consideration, the mechanism finds a suitable projection and recomputes new importance sampling (IS) ratios.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: August 20, 2019
    Assignee: International Buisness Machines Corporation
    Inventors: Rajiv V. Joshi, Rouwaida N. Kanj, Sani R. Nassif, Carl J. Radens
  • Patent number: 10387596
    Abstract: In one example, a method for evaluating a system includes constructing a macro-model of the system comprising a multiple-order polynomial equation that defines a boundary between at least one failure region and a non-failure region for a performance indicator with respect to at least one variable of the system. The method further includes obtaining importance samples for the at least one variable that are biased to the at least one failure region, and calculating indicator values for the performance indicator by applying the importance samples to the macro-model.
    Type: Grant
    Filed: August 26, 2014
    Date of Patent: August 20, 2019
    Assignee: International Business Machines Corporation
    Inventors: Rajiv V. Joshi, Emrah Acar, Colin J. Parris
  • Patent number: 10389356
    Abstract: A circuit and method are provided. The circuit and method are for providing a supply voltage. The circuit includes a first transistor and a second transistor, coupled to a static power supply that supplies a constant power supply voltage. The circuit further includes a magnetic inductor having a first terminal connected to a common node between the first transistor and the second transistor and a second terminal connected to the dynamic internal power supply node, to supply a dynamic internal power supply node with a boosted voltage relative to the constant power supply voltage by resonating with at least one capacitance coupled to the dynamic internal power supply node.
    Type: Grant
    Filed: April 25, 2018
    Date of Patent: August 20, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce B. Doris, Rajiv V. Joshi, Naigang Wang
  • Patent number: 10270443
    Abstract: Circuits and methods are provided. The circuits and methods are for providing a supply voltage to a dynamic internal power supply node of a group of other circuits. A circuit includes a first transistor and a second transistor, of different channel types, coupled in parallel to a static power supply that supplies a constant power supply voltage. The circuit further includes a magnetic inductor having a first terminal connected to a common node between the first transistor and the second transistor and a second terminal connected to the dynamic internal power supply node, to supply the dynamic internal power supply node with a boosted voltage having a magnitude greater than a magnitude of the constant power supply voltage by resonating with at least one capacitance coupled to the dynamic internal power supply node.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: April 23, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce B. Doris, Rajiv V. Joshi, Naigang Wang
  • Patent number: 10263519
    Abstract: A booster for a digital circuit block provides speed and reliability at lower static power supply voltages, reducing overall power consumption of the circuits. The booster includes a transistor that couples a dynamic power supply node to a static power supply and is disabled in response to a boost clock. An inductor and capacitance, which may be the block power supply shunt capacitance, coupled to the dynamic power supply resonates so that the voltage of the dynamic power supply increases in magnitude to a value greater the static power supply voltage. A boost transistor is included in some embodiments to couple an edge of the clock to the dynamic power supply, increasing the voltage rise. Another aspect of the booster includes multiple boost transistors controlled by different boost clock phases so that the resonant boost circuit is successively stimulated to increase the amount of voltage rise.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: April 16, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Rajiv V. Joshi, Matthew M. Ziegler
  • Patent number: 10256819
    Abstract: Circuits and methods are provided. The circuits and methods are for providing a supply voltage to a dynamic internal power supply node of a group of other circuits. A circuit includes a first transistor and a second transistor, of different channel types, coupled in parallel to a static power supply that supplies a constant power supply voltage. The circuit further includes a magnetic inductor having a first terminal connected to a common node between the first transistor and the second transistor and a second terminal connected to the dynamic internal power supply node, to supply the dynamic internal power supply node with a boosted voltage having a magnitude greater than a magnitude of the constant power supply voltage by resonating with at least one capacitance coupled to the dynamic internal power supply node.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: April 9, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Bruce B. Doris, Rajiv V. Joshi, Naigang Wang
  • Patent number: 10242387
    Abstract: Disclosed aspects relate to managing a set of offers using a dialogue. An adaptive profile may be received with respect to a client. The adaptive profile may indicate a set of client profile data, a set of client event data, and a set of client context data. A dialogue may be established with the client based on the adaptive profile. A set of offers may be resolved by an offer management engine based on the dialogue. The set of offers may be presented to the client.
    Type: Grant
    Filed: December 22, 2017
    Date of Patent: March 26, 2019
    Assignee: International Business Machines Corporation
    Inventors: Swaminathan Balasubramanian, Avijit Chatterjee, Rajiv V. Joshi, John J. Thomas
  • Patent number: 10169509
    Abstract: A system for conducting numerical analysis includes a processor that is configured to define a plurality of components in a circuit and a condition to be statistically analyzed, a module that is configured to perform a table look-up for individual components of the plurality of components, and a module that is configured to acquire a result for the condition to be statistically analyzed based on information in a table in which a component of the plurality of components is defined. A result of the statistical analysis provides a design of the circuit for a fabrication facility for manufacturing integrated circuits.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Emrah Acar, Rajiv V. Joshi, Tong Li
  • Patent number: 10169508
    Abstract: A method for conducting numerical analysis includes defining a plurality of components in a system and a condition to be statistically analyzed, performing a table look-up for individual components of the plurality of components, acquiring a result for the condition to be statistically analyzed based on information in a table when a component of the plurality of components is defined in the table, and designing a circuit from integrated circuits based on conducting the statistical analysis of the system. The designing the circuit from the integrated circuits is implemented in manufacturing the integrated circuits.
    Type: Grant
    Filed: November 30, 2017
    Date of Patent: January 1, 2019
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Emrah Acar, Rajiv V. Joshi, Tong Li
  • Publication number: 20180351506
    Abstract: Semiconductor devices and methods relating to the semiconductor devices are provided. A semiconductor device includes a resonant clock circuit. The semiconductor device further includes an inductor. The semiconductor device also includes a magnetic layer formed of a magnetic material disposed in between a portion of the resonant clock circuit and the inductor. Clock signals of the resonant clock circuit are utilized by the magnetic layer.
    Type: Application
    Filed: June 2, 2017
    Publication date: December 6, 2018
    Inventors: Bruce B. Doris, Rajiv V. Joshi, Naigang Wang
  • Publication number: 20180351507
    Abstract: Semiconductor devices and methods relating to the semiconductor devices are provided. A semiconductor device includes a resonant clock circuit. The semiconductor device further includes an inductor. The semiconductor device also includes a magnetic layer formed of a magnetic material disposed in between a portion of the resonant clock circuit and the inductor. Clock signals of the resonant clock circuit are utilized by the magnetic layer.
    Type: Application
    Filed: December 14, 2017
    Publication date: December 6, 2018
    Inventors: Bruce B. Doris, Rajiv V. Joshi, Naigang Wang
  • Publication number: 20180337678
    Abstract: Circuits and methods are provided. The circuits and methods are for providing a supply voltage to a dynamic internal power supply node of a group of other circuits. A circuit includes a first transistor and a second transistor, of different channel types, coupled in parallel to a static power supply that supplies a constant power supply voltage. The circuit further includes a magnetic inductor having a first terminal connected to a common node between the first transistor and the second transistor and a second terminal connected to the dynamic internal power supply node, to supply the dynamic internal power supply node with a boosted voltage having a magnitude greater than a magnitude of the constant power supply voltage by resonating with at least one capacitance coupled to the dynamic internal power supply node.
    Type: Application
    Filed: February 15, 2018
    Publication date: November 22, 2018
    Inventors: Bruce B. Doris, Rajiv V. Joshi, Naigang Wang
  • Publication number: 20180337679
    Abstract: A circuit and method are provided. The circuit and method are for providing a supply voltage. The circuit includes a first transistor and a second transistor, coupled to a static power supply that supplies a constant power supply voltage. The circuit further includes a magnetic inductor having a first terminal connected to a common node between the first transistor and the second transistor and a second terminal connected to the dynamic internal power supply node, to supply a dynamic internal power supply node with a boosted voltage relative to the constant power supply voltage by resonating with at least one capacitance coupled to the dynamic internal power supply node.
    Type: Application
    Filed: April 25, 2018
    Publication date: November 22, 2018
    Inventors: Bruce B. Doris, Rajiv V. Joshi, Naigang Wang