Abstract: A method of automatically generating structure files employing a full structure generator automated program is provided. An annotated device layout file is generated from a design layout by annotating the codes for design shapes with additional text representing the functionality of a physical structure associated with each design shape. Functioning individual semiconductor devices are identified from the annotated device layout file, and a circuit area including multiple interconnected semiconductor devices are identified. A front-end-of-line (FEOL) device structure file and a back-end-of-line (BEOL) device structure file are generated from layer by layer analysis of the components of the annotated device layout within the circuit area. Finite element meshes (FEMs) are generated for the FEOL and BEOL structure files and merged to provide a structure file that can be employed for simulation of semiconductor devices therein.

Abstract: A method for analyzing circuits includes identifying one or more device zones in a full device structure. The device zones provide areas of interest to be analyzed. A partial device is generated that representatively includes the one or more device zones. Analytical meshes of the partial device are reduced by employing physical characteristics of the full device structure. The partial device is simulated, using a processor, to obtain device output information in the areas of interest that is representative of the full device structure. Systems are also disclosed.

Abstract: A method for analyzing circuits includes identifying one or more device zones in a full device structure. The device zones provide areas of interest to be analyzed. A partial device is generated that representatively includes the one or more device zones. Analytical meshes of the partial device are reduced by employing physical characteristics of the full device structure. The partial device is simulated, using a processor, to obtain device output information in the areas of interest that is representative of the full device structure. Systems are also disclosed.

Abstract: An apparatus and method for combating the effects of bias temperature instability (BTI) and other variability in a memory cell. Bit lines connecting to a memory cell contain two alternate paths that criss-cross to connect a lower portion of a first bit line to an upper portion of a second bit line, and to connect a lower portion of the second bit line to an upper portion of the first bit line. Alternative to activating transistors on the bit lines to read and write to the memory cell, transistors on the alternative paths may be activated to read and write to the memory cell from the opposite bit line. In this fashion, the memory cell may be read through the bit lines to a sense amplifier where the bit values are latched. While the bit values remain latched in the sense amplifier, the transistors on the bit lines are deactivated and the transistors on the alternate paths are activated.

Abstract: A method of automatically generating structure files employing a full structure generator automated program is provided. An annotated device layout file is generated from a design layout by annotating the codes for design shapes with additional text representing the functionality of a physical structure associated with each design shape. Functioning individual semiconductor devices are identified from the annotated device layout file, and a circuit area including multiple interconnected semiconductor devices are identified. A front-end-of-line (FEOL) device structure file and a back-end-of-line (BEOL) device structure file are generated from layer by layer analysis of the components of the annotated device layout within the circuit area. Finite element meshes (FEMs) are generated for the FEOL and BEOL structure files and merged to provide a structure file that can be employed for simulation of semiconductor devices therein.

Abstract: A single finite element mesh is generated for predicting performance of an integrated circuit design. A plurality of sample points are identified for conducting a variability study on at least one parameter associated with the integrated circuit design. The sample points are selected to predict performance of the integrated circuit design when subject to variations in the at least one parameter due to variations in manufacturing processes to be used to manufacture the integrated circuit design. A parameterized netlist is generated corresponding to each of the sample points. A technology computer aided design (TCAD) simulation is run for each of the parameterized netlists, using the single finite element mesh for each of the parameterized netlists, until convergence is achieved, to obtain, for each of the parameterized netlists, at least one metric indicative of the performance of the integrated circuit design. A predicted design yield is developed for the integrated circuit design.

Abstract: A single finite element mesh is generated for predicting performance of an integrated circuit design. A plurality of sample points are identified for conducting a variability study on at least one parameter associated with the integrated circuit design. The sample points are selected to predict performance of the integrated circuit design when subject to variations in the at least one parameter due to variations in manufacturing processes to be used to manufacture the integrated circuit design. A parameterized netlist is generated corresponding to each of the sample points. A technology computer aided design (TCAD, e.g., finite element) simulation is run for each of the parameterized netlists, using the single finite element mesh for each of the parameterized netlists, until convergence is achieved, to obtain, for each of the parameterized netlists, at least one metric indicative of the performance of the integrated circuit design.

Abstract: Correlated failure distribution for memory arrays having different groupings of memory cells is estimated by constructing memory unit models for the groupings based on multiple parameters, establishing failure conditions of the memory unit model using fast statistical analysis, calculating a fail boundary of the parameters for each memory unit model based on its corresponding failure conditions, and constructing memory array models characterized by the fail boundaries. Operation of a memory array model is repeatedly simulated with random values of the parameters assigned to the memory cells and peripheral logic elements to identify memory unit failures for each simulated operation. A mean and a variance is calculated for each memory array model, and an optimal architecture can thereafter be identified by selecting the grouping exhibiting the best mean and variance, subject to any other circuit requirements such as power or area.

Abstract: A method of automatically generating structure files employing a full structure generator automated program is provided. An annotated device layout file is generated from a design layout by annotating the codes for design shapes with additional text representing the functionality of a physical structure associated with each design shape. Functioning individual semiconductor devices are identified from the annotated device layout file, and a circuit area including multiple interconnected semiconductor devices are identified. A front-end-of-line (FEOL) device structure file and a back-end-of-line (BEOL) device structure file are generated from layer by layer analysis of the components of the annotated device layout within the circuit area. Finite element meshes (FEMs) are generated for the FEOL and BEOL structure files and merged to provide a structure file that can be employed for simulation of semiconductor devices therein.

Abstract: Systems and methods for determining optimal memory device precharge voltages are provided herein. In addition, systems and methods for providing localized sense amplification and circuit assist circuitry are described herein. Embodiments provide for determining precharge multipliers that may be used to determine the optimal precharge voltage based on a precharge source voltage. According to embodiments, the precharge source voltage may be Vdd or Vcs. Optimizing the precharge voltage maximizes memory device performance and functional characteristics, including, but not limited to, stability, efficiency, power, writability, and reliability.

Abstract: At least one N-type transistor and at least one P-type transistor separate from the digital circuit are sized to represent the total area of the corresponding type transistors in the digital circuit. The gates of the N-type transistor and P-type transistors are set to voltages according to the corresponding off-state logic levels of the digital circuit. The N-type and P-type transistors form a portion of corresponding current mirror circuits, which can provide outputs to a leakage current monitor and/or a control circuit such as a comparator that determines when leakage current for the N-type or P-type devices has exceeded a threshold. The output of the measurement/control circuit can be used to determine a temperature of and/or control operation of the digital circuit or the system environment of the integrated circuit.

Abstract: Semiconductor structures are provided containing an electronic fuse (E-fuse) that includes a fuse element and at least one underlying tungsten contact that is used for programming the fuse element. In some embodiments, a pair of neighboring tungsten contacts is used for programming the fuse element. In another embodiment, an overlying conductive region can be used in conjunction with one of the underlying tungsten contacts to program the fuse element. In the disclosed structures, the fuse element is in direct contact with upper surfaces of a pair of underlying tungsten contacts. In one embodiment, the semiconductor structures may include an interconnect level located atop the fuse element. The interconnect level has a plurality of conductive regions embedded therein. In other embodiments, the fuse element is located within an interconnect level that is located atop the tungsten contacts.

Abstract: Methods and systems for migrating circuit layouts. A floorplan layout is built for a target circuit using a subset of constraints that characterize a layout structure of an original circuit. Shape-constraint-based scaling is used on the floorplan layout by scaling parts of the floorplan layout in accordance with a plurality of different scaling ratios such that portions of the floorplan layout are concurrently scaled with the plurality of different scaling ratios. Cells are placed at locations defined by the floorplan layout. The floorplan layout is checked with shape-constraint-based legalization using all of the constraints to produce a migrated layout.

Abstract: A method for repairing degraded field effect transistors includes forward biasing PN junctions of one of a source and a drain of a field effect transistor (FET), and a body of the FET. Charge is injected from a substrate to a gate region to neutralize charge in the gate region. The method is applicable to CMOS devices. Repair circuits are disclosed for implementing the repairs.

Abstract: An apparatus and method for combating the effects of bias temperature instability (BTI) in a memory cell. Bit lines connecting to a memory cell contain two alternate paths criss-crossing to connect a lower portion of a first bit line to an upper portion of a second bit line, and to connect a lower portion of the second bit line to an upper portion of the first bit line. Alternative to activating transistors on the bit lines to read and write to the memory cell, transistors on the alternative paths may be activated to read and write to the memory cell from the opposite bit lines. The memory cell may be read through the bit lines to a sense amplifier, the transistors on the bit lines are subsequently deactivated and the transistors on the alternate paths are activated to write transposed bit values to the memory cell, thereby reversing the biases.

Abstract: A single finite element mesh is generated for predicting performance of an integrated circuit design. A plurality of sample points are identified for conducting a variability study on at least one parameter associated with the integrated circuit design. The sample points are selected to predict performance of the integrated circuit design when subject to variations in the at least one parameter due to variations in manufacturing processes to be used to manufacture the integrated circuit design. A parameterized netlist is generated corresponding to each of the sample points. A technology computer aided design (TCAD) simulation is run for each of the parameterized netlists, using the single finite element mesh for each of the parameterized netlists, until convergence is achieved, to obtain, for each of the parameterized netlists, at least one metric indicative of the performance of the integrated circuit design. A predicted design yield is developed for the integrated circuit design.

Abstract: Methods and systems for migrating circuit layouts. A floorplan layout is built for a target circuit using a subset of constraints that characterize a layout structure of an original circuit. Shape-constraint-based scaling is used on the floorplan layout by scaling parts of the floorplan layout in accordance with a plurality of different scaling ratios such that portions of the floorplan layout are concurrently scaled with the plurality of different scaling ratios. Cells are placed at locations defined by the floorplan layout. The floorplan layout is checked with shape-constraint-based legalization using all of the constraints to produce a migrated layout.

Abstract: A failure probability for a system having multi-fail regions is computed by generating failure directions in a space whose dimensions are the system parameters under consideration. The failure directions are preferably uniform, forming radial slices. The failure directions may be weighted. The radial slices have fail boundaries defining fail regions comparable to broken shells. The distribution of the system parameters is integrated across the broken shell regions to derive a failure contribution for each failure direction. The failure probability is the sum of products of each failure contribution and its weight. Failure contributions are computed using equivalent expressions dependent on the number of dimensions, which can be used to build lookup tables for normalized fail boundary radii. The entire process can be iteratively repeated with successively increasing failure directions until the failure probability converges.

Abstract: Mechanisms are provided for modeling a plurality of devices of an integrated circuit design as a single statistically equivalent wide device. An integrated circuit design is analyzed to identify a portion of the integrated circuit design having the plurality of devices. For the plurality of devices, a statistical model of a single statistically equivalent wide device is generated which has a statistical distribution of at least one operating characteristic of the single statistically equivalent wide device that captures statistical operating characteristic distributions of individual devices in the plurality of devices. At least one statistical operating characteristic of the single statistically equivalent wide device is a complex non-linear function of the statistical operating characteristics of the individual devices. The integrated circuit design is modeled using the single statistically equivalent wide device.

Abstract: Mechanisms are provided for modeling a plurality of devices of an integrated circuit design as a single statistically equivalent wide device. An integrated circuit design is analyzed to identify a portion of the integrated circuit design having the plurality of devices. For the plurality of devices, a statistical model of a single statistically equivalent wide device is generated which has a statistical distribution of at least one operating characteristic of the single statistically equivalent wide device that captures statistical operating characteristic distributions of individual devices in the plurality of devices. At least one statistical operating characteristic of the single statistically equivalent wide device is a complex non-linear function of the statistical operating characteristics of the individual devices. The integrated circuit design is modeled using the single statistically equivalent wide device.