Abstract: Semiconductor devices and methods relating to the semiconductor devices are provided. A semiconductor device includes a resonant clock circuit. The semiconductor device further includes an inductor. The semiconductor device also includes a magnetic layer formed of a magnetic material disposed in between a portion of the resonant clock circuit and the inductor. Clock signals of the resonant clock circuit are utilized by the magnetic layer.

Abstract: Circuits and methods are provided. The circuits and methods are for providing a supply voltage to a dynamic internal power supply node of a group of other circuits. A circuit includes a first transistor and a second transistor, of different channel types, coupled in parallel to a static power supply that supplies a constant power supply voltage. The circuit further includes a magnetic inductor having a first terminal connected to a common node between the first transistor and the second transistor and a second terminal connected to the dynamic internal power supply node, to supply the dynamic internal power supply node with a boosted voltage having a magnitude greater than a magnitude of the constant power supply voltage by resonating with at least one capacitance coupled to the dynamic internal power supply node.

Abstract: A circuit and method are provided. The circuit and method are for providing a supply voltage. The circuit includes a first transistor and a second transistor, coupled to a static power supply that supplies a constant power supply voltage. The circuit further includes a magnetic inductor having a first terminal connected to a common node between the first transistor and the second transistor and a second terminal connected to the dynamic internal power supply node, to supply a dynamic internal power supply node with a boosted voltage relative to the constant power supply voltage by resonating with at least one capacitance coupled to the dynamic internal power supply node.

Abstract: Circuits and methods are provided. The circuits and methods are for providing a supply voltage to a dynamic internal power supply node of a group of other circuits. A circuit includes a first transistor and a second transistor, of different channel types, coupled in parallel to a static power supply that supplies a constant power supply voltage. The circuit further includes a magnetic inductor having a first terminal connected to a common node between the first transistor and the second transistor and a second terminal connected to the dynamic internal power supply node, to supply the dynamic internal power supply node with a boosted voltage having a magnitude greater than a magnitude of the constant power supply voltage by resonating with at least one capacitance coupled to the dynamic internal power supply node.

Abstract: Disclosed aspects relate to managing a set of offers using a dialogue. An adaptive profile may be received with respect to a client. The adaptive profile may indicate a set of client profile data, a set of client event data, and a set of client context data. A dialogue may be established with the client based on the adaptive profile. A set of offers may be resolved by an offer management engine based on the dialogue. The set of offers may be presented to the client.

Abstract: Disclosed aspects relate to managing a set of offers using a dialogue. An adaptive profile may be received with respect to a client. The adaptive profile may indicate a set of client profile data, a set of client event data, and a set of client context data. A dialogue may be established with the client based on the adaptive profile. A set of offers may be resolved by an offer management engine based on the dialogue. The set of offers may be presented to the client.

Abstract: A computer-implemented method and computing system are provided for failure prediction of a batch of manufactured objects. The method includes classifying, by, a processor sing a simulation, a set of samples with uniformly distributed parameter values, to generate sample classifications for the batch of manufactured objects. The method further includes determining, by the processor, a centroid of failing ones of the samples in the set, based on the sample classifications. The method also includes generating, by the processor, a new set of samples with a distribution around the centroid of the failing ones of the sample in the set. The method additionally includes populating, by the processor, a nearest neighbor vector space using the new set of samples. The method further includes classifying, by the processor, the new set of samples by performing a nearest neighbor search on the nearest neighbor vector space using a distance metric.

Abstract: A computer-implemented method and computing system are provided for failure prediction of a batch of manufactured objects. The method includes classifying, by a processor using a simulation, a set of samples with uniformly distributed parameter values, to generate sample classifications for the batch of manufactured objects. The method further includes determining, by the processor, a centroid of failing ones of the samples in the set, based on the sample classifications. The method also includes generating, by the processor, a new set of samples with a distribution around the centroid of the failing ones of the sample in the set. The method additionally includes populating, by the processor, a nearest neighbor vector space using the new set of samples. The method further includes classifying, by the processor, the new set of samples by performing a nearest neighbor search on the nearest neighbor vector space using a distance metric.

Abstract: Circuits and methods are provided. The circuits and methods are for providing a supply voltage to a dynamic internal power supply node of a group of other circuits. A circuit includes a first transistor and a second transistor, of different channel types, coupled in parallel to a static power supply that supplies a constant power supply voltage. The circuit further includes a magnetic inductor having a first terminal connected to a common node between the first transistor and the second transistor and a second terminal connected to the dynamic internal power supply node, to supply the dynamic internal power supply node with a boosted voltage having a magnitude greater than a magnitude of the constant power supply voltage by resonating with at least one capacitance coupled to the dynamic internal power supply node.

Abstract: A method for conducting numerical analysis includes defining a plurality of components in a system and a condition to be analyzed, performing a table look-up for components of the plurality of components, acquiring a result for the condition to be analyzed based on information in a table in which a component of the plurality of components is defined, and conducting the analysis of the system using the result based on the information in the table for the component.

Abstract: A system for conducting numerical analysis includes a processor that is configured to define a plurality of components in a circuit and a condition to be analyzed, a module that is configured to perform a table look-up for components of the plurality of components, a module that is configured to acquire a result for the condition to be analyzed based on information in a table in which a component of the plurality of components is defined, and a module that is configured to conduct the analysis of the circuit using the result based on the information in the table for the component.

Abstract: A method for conducting numerical analysis includes defining a plurality of components in a system and a condition to be statistically analyzed, performing a table look-up for individual components of the plurality of components, acquiring a result for the condition to be statistically analyzed based on information in a table when a component of the plurality of components is defined in the table, and designing a circuit from integrated circuits based on conducting the statistical analysis of the system. The designing the circuit from the integrated circuits is implemented in manufacturing the integrated circuits.

Abstract: A system for conducting numerical analysis includes a processor that is configured to define a plurality of components in a circuit and a condition to be statistically analyzed, a module that is configured to perform a table look-up for individual components of the plurality of components, and a module that is configured to acquire a result for the condition to be statistically analyzed based on information in a table in which a component of the plurality of components is defined. A result of the statistical analysis provides a design of the circuit for a fabrication facility for manufacturing integrated circuits.

Abstract: An system and method are configured to degrade a memory cell PFET voltage based on a sensor reading of a current operating point. This will enable additional control over the SRAM device, particularly during a write operation. In one embodiment, a system of SRAM memory devices is configured as a smart sensor with real-time corrective circuit action. The system and method samples write and read timing operations and is adaptable by performing real-time corrective action. The degrading of PFET voltage to reduce it strength and improve write characteristics include an implementation that includes a charge pump controllable for altering by decreasing a voltage applied to the PFET of a selected memory cell. In a further embodiment, an edge detector is built into the circuit that real-time assesses the strength of the memory write operation. In a further implementation, control logic functions as a Finite State Machine.

Abstract: A system for conducting numerical analysis includes a processor that is configured to define a plurality of components in a circuit and a condition to be analyzed, a module that is configured to perform a table look-up for components of the plurality of components, a module that is configured to acquire a result for the condition to be analyzed based on information in a table in which a component of the plurality of components is defined, and a module that is configured to conduct the analysis of the circuit using the result based on the information in the table for the component.

Abstract: A method for conducting numerical analysis includes defining a plurality of components in a system and a condition to be analyzed, performing a table look-up for components of the plurality of components, acquiring a result for the condition to be analyzed based on information in a table in which a component of the plurality of components is defined, and conducting the analysis of the system using the result based on the information in the table for the component.

Abstract: A booster for a digital circuit block provides speed and reliability at lower static power supply voltages, reducing overall power consumption of the circuits. The booster includes a transistor that couples a dynamic power supply node to a static power supply and is disabled in response to a boost clock. An inductor and capacitance, which may be the block power supply shunt capacitance, coupled to the dynamic power supply resonates so that the voltage of the dynamic power supply increases in magnitude to a value greater the static power supply voltage. A boost transistor is included in some embodiments to couple an edge of the clock to the dynamic power supply, increasing the voltage rise. Another aspect of the booster includes multiple boost transistors controlled by different boost clock phases so that the resonant boost circuit is successively stimulated to increase the amount of voltage rise.

Abstract: An system and method are configured to degrade a memory cell PFET voltage based on a sensor reading of a current operating point. This will enable additional control over the SRAM device, particularly during a write operation. In one embodiment, a system of SRAM memory devices is configured as a smart sensor with real-time corrective circuit action. The system and method samples write and read timing operations and is adaptable by performing real-time corrective action. The degrading of PFET voltage to reduce it strength and improve write characteristics include an implementation that includes a charge pump controllable for altering by decreasing a voltage applied to the PFET of a selected memory cell. In a further embodiment, an edge detector is built into the circuit that real-time assesses the strength of the memory write operation. In a further implementation, control logic functions as a Finite State Machine.

Abstract: A system for conducting numerical analysis includes a processor that is configured to define a plurality of components in a circuit and a condition to be analyzed, a module that is configured to perform a table look-up for components of the plurality of components, a module that is configured to acquire a result for the condition to be analyzed based on table information when a component of the plurality of components is defined in a table and when the table includes the condition to be analyzed, and a module that is configured to conduct the analysis of the circuit using the result based on the table information for the component.

Abstract: A method for predicting a condition in a circuit under design includes obtaining a set comprising first static noise margin curve for the circuit and a second static noise margin curve for the circuit, wherein the second static noise margin curve is complementary to the first static noise margin curve, matching the set to a two-dimensional model of a cell, and predicting the condition in accordance with hardware characterization data corresponding to the cell.