Abstract: A row redundancy system is provided for replacing faulty wordlines of a memory array having a plurality of banks. The row redundancy system includes a remote fuse bay storing at least one faulty address corresponding to a faulty wordline of the memory array; a row fuse array for storing row fuse information corresponding to at least one bank of the memory array; and a copy logic module for copying at least one faulty address stored in the remote fuse bay into the row fuse array; wherein the copy logic module is programmed to copy the at least one faulty address into the row fuse information stored in the row fuse array corresponding to a predetermined number of banks in accordance with a selectable repair field size.

Abstract: Techniques are provided for fuse/anti-fuse structures, including an inner conductor structure, an insulating layer spaced outwardly of the inner conductor structure, an outer conductor structure disposed outwardly of the insulating layer, and a cavity-defining structure that defines a cavity, with at least a portion of the cavity-defining structure being formed from at least one of the inner conductor structure, the insulating layer, and the outer conductor stricture Methods of making and programming the fuse/anti-fuse structures are also provided.

Abstract: A semiconductor device includes a semiconductor material having two crystal orientations. The semiconductor material forms an active area of the device. A device channel is formed on the two crystal orientations, which include a first region formed in a first crystal orientation surface of the semiconductor material, and a second region formed in a second crystal orientation surface of the semiconductor material wherein the first crystal orientation surface forms an angle with the second crystal orientation surface and the device channel covers at least an intersection of the angle.

Abstract: A system and method for scaling a circuit design to a new technology includes designating a first set of components including design scaled elements having a designed scaling in two dimensions to render the first set of components inactive for scaling of a second set of components. The second set of components includes pitch-matched circuits. The second set of components is scaled. Then, the second set of components is designated to render the second set of components inactive for scaling of the first set of components. The first set of components is scaled in accordance with a plurality of scale factors including scaling the design scaled elements in accordance with reference scale factors and scaling other components in the first set of components in accordance with one of the reference scale factors.

Abstract: Methods and apparatus are provided for read/write control and bit selection with false read suppression in an SRAM. According to one aspect of the invention, a bit select circuit is provided for an SRAM. The disclosed bit select circuit includes one or more transistors controlled by a write control gate signal to prevent data from being read from one or more data cells during a write operation. The transistors can include, for example, a pair of gated transistors controlled by the write control gate signal. The write control gate signal prevents data from being read from one or more data cells while the write control gate signal is in a predefined state.

Abstract: A memory cell for interconnection with READ and WRITE word lines and READ and WRITE bit lines includes a logical storage element such as a flip-flop formed by a first inverter and a second inverter cross-coupled to the first inverter. The storage element has first and second terminals and a storage element supply voltage terminal configured for interconnection with a first supply voltage. A WRITE access device is configured to selectively interconnect the first terminal to the WRITE bit line under control of the WRITE word line, and a pair of series READ access devices are configured to ground the READ bit line when the READ word line is active and the second terminal is at a high logical level. A logical “one” can be written to the storage element when a second supply voltage, greater than the first supply voltage, is applied to the WRITE word line, substantially without the use of a complementary WRITE bit line.

Abstract: A test circuit and programmable voltage divider that may be used in the test circuit. The programmable voltage divider develops a voltage difference signal that may be digitally selected. The test circuit may be used to test and characterize sense amplifiers. The programmable voltage divider develops a signal with a selected polarity and magnitude that is provided to a sense amplifier being tested. The sense amplifier is set and its output latched. The latch contents are checked against an expected value. The difference voltage may be changed and the path retested to find passing and failing points.

Abstract: A memory cell for interconnection with READ and WRITE word lines and READ and WRITE bit lines includes a logical storage element such as a flip-flop formed by a first inverter and a second inverter cross-coupled to the first inverter. The storage element has first and second terminals and a storage element supply voltage terminal configured for interconnection with a first supply voltage. A WRITE access device is configured to selectively interconnect the first terminal to the WRITE bit line under control of the WRITE word line, and a pair of series READ access devices are configured to ground the READ bit line when the READ word line is active and the second terminal is at a high logical level.

Abstract: A system and computer program for efficient cell failure rate estimation in cell arrays provides an efficient mechanism for raising the performance of memory arrays beyond present levels/yields. An initial search is performed across cell circuit parameters to determine failures with respect to a set of performance variables. For a single failure region the initial search can be a uniform sampling of the parameter space and when enough failure points have been accumulated, a mean is chosen from the mean of the detected failure points. Mixture importance sampling (MIS) is then performed to efficiently estimate the single failure region. For multiple failure regions, a particular failure region is selected by varying the memory circuit cell parameters along a random set of vectors until failures are detected, thus identifying the boundary of the failure region of interest as the closest failure region. A new mean is chosen for MIS in conformity with the location of the detected boundary.

Abstract: There is provided a method for managing a multi-level power supply. The method includes comparing a voltage level (Vs1) of a lower voltage supply bus to a voltage level (Vs2) of a higher voltage supply bus, and routing current from the lower voltage supply bus to the higher voltage supply bus if Vs2<Vs1. The lower and higher voltage supply busses provide power to a complementary metal oxide semiconductor (CMOS) circuit. The method prevents a latch-up of the CMOS circuit. There is also provided a circuit that employs the method.

Abstract: In a memory circuit, data from all cells along a selected word line is read. Then, the read data is written back to half-selected cells and new data is written to the selected cells in the next cycle. In cases where a READ bit line (RBL) and WRITE bit line (WBL) are decoupled, RBL and WBL can be accessed simultaneously. Hence, the WRITE in the n-th cycle can be delayed to the n+1-th cycle as far as there is no data hazard such as reading data from memory before correct data are actually written to memory. As a result, there is no bandwidth loss, although the latency of the WRITE operation increases. WRITE stability issues in previous configurations with decoupled RBL and WBL are thus addressed.

Abstract: A row redundancy system is provided for replacing faulty wordlines of a memory array having a plurality of banks. The row redundancy system includes a remote fuse bay storing at least one faulty address corresponding to a faulty wordline of the memory array; a row fuse array for storing row fuse information corresponding to at least one bank of the memory array; and a copy logic module for copying at least one faulty address stored in the remote fuse bay into the row fuse array; the copy logic module is programmed to copy the at least one faulty address into the row fuse information stored in the row fuse array corresponding to a predetermined number of banks in accordance with a selectable repair field size.

Abstract: A multi-threshold integrated circuit (IC) that may be supplied by multiple supplies, with an array of latches such as an array static random access memory (SRAM) cells and a CMOS SRAM with improved stability and reduced subthreshold leakage. Selected devices (NFETs and/or PFETs) in array cells and support logic, e.g., in the data path and in non-critical logic, are tailored for lower gate and subthreshold leakage. Normal base FETs have a base threshold and tailored FETs have a threshold above. In a multi-supply chip, circuits with tailored FETs are powered by an increased supply voltage.

Abstract: A semiconductor structure having a body capacitance plate, which is formed with a process that assures that the body capacitance plate is self-aligned to both the source line (SL) diffusion and the bitline diffusion is provided. Thus the amount of overlap between the SL and the bitline diffusions and the body capacitance plate is precisely controlled. More specifically, the present invention forms the structure of a 1T-capacitorless SOI body charge storage cell having sidewall capacitor plates using a process that assures that there is 1) minimal overlap between plate and source/drain diffusions, and 2) that the minimal overlap obtained in the present invention is precisely controlled and is not subject to alignment tolerances. The inventive cell results in larger signal margin, improved performance, smaller chip size, and reduced dynamic power dissipation relative to the prior art.

Abstract: A method and computer program for efficient cell failure rate estimation in cell arrays provides an efficient mechanism for raising the performance of memory arrays beyond present levels/yields. An initial search is performed across cell circuit parameters to determine failures with respect to a set of performance variables. For a single failure region the initial search can be a uniform sampling of the parameter space and when enough failure points have been accumulated, a mean is chosen from the mean of the detected failure points. Mixture importance sampling (MIS) is then performed to efficiently estimate the single failure region. For multiple failure regions, a particular failure region is selected by varying the memory circuit cell parameters along a random set of vectors until failures are detected, thus identifying the boundary of the failure region of interest as the closest failure region. A new mean is chosen for MIS in conformity with the location of the detected boundary.

Abstract: A method for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A ring oscillator implemented in a row of memory cells and having outputs connected to one or more bitlines along with other memory cells that are substantially identical to the ring oscillator cells is operated by the method. Logic may be included for providing a fully functional memory array, so that the cells other than the ring oscillator cells can be used for storage when the ring oscillator row wordlines are disabled. One or both power supply rails of individual cross-coupled inverter stages forming static memory cells used in the ring oscillator circuit may be isolated from each other in order to introduce a voltage asymmetry so that circuit asymmetry effects on delay can be evaluated.

Abstract: A novel semiconductor SRAM cell structure that includes at least two pull-up transistors, two pull-down transistors, and two pass-gate transistors. In one embodiment, an 8T SRAM cell structure implements a series gating feature for implementing Column Select (CS) and Row Select (WL) cell storage access with enhanced stability. Particularly, the 8-T approach adds two pass-gates, two series connected transistor devices connected at complementary nodes of two cross-coupled inverters, to control column select and row (word) select. In the other embodiment, a 9T SRAM cell structure includes a transmission gate to implement Column Select (CS) and Row Select (WL) cell storage access with enhanced stability. The 9-T approach adds three transistors to perform ANDING function to separate the row select and column select signal functions. Both methods improve stability by eliminating half-select mode and facilitate rail to rail data transfer in and out of the SRAM cell without disturbing the other cells.

Abstract: A method of fabricating a semiconductor device includes etching a substrate to form a recess, the substrate being formed on a backside of a semiconductor wafer, forming pores in the substrate in an area of the recess, and forming in the recess a material having a thermal conductivity which is greater than a thermal conductivity of the substrate. In another aspect, a method of fabricating a semiconductor device includes etching a substrate formed on a backside of a semiconductor wafer to form a recess in the substrate, and forming a sputter film in the recess, the sputter film including a first material having a coefficient of thermal expansion (CTE) which is at least substantially equal to a CTE of the substrate, and a second material having a thermal conductivity which is greater than a thermal conductivity of the substrate.

Abstract: A level converter for interfacing two circuits supplied by different supply voltages, and integrated circuit including the level converter interfacing circuit in two different voltage islands. A first buffer is supplied by a virtual supply and receives an input signal from a lower voltage circuit. The first buffer drives a second buffer, which is supplied by a higher supply voltage. An output from the second buffer switches a supply select to selectively pass the higher supply voltage or a reduced supply voltage to the first buffer.

Abstract: A metal-insulator-metal (MIM) capacitor including a metal layer, an insulating layer formed on the metal layer, at least a first opening and at least a second opening formed in the first insultaing layer, a dielectric layer formed in the first opening, a conductive material deposited in the first and second openings, and a first metal plate formed over the first opening and a second metal plate formed over the second opening. A method for fabricating the MIM capacitor, includes forming the first metal layer, forming the insulating layer on the first metal layer, forming at least the first opening and at least the second opening in the first insultaing layer, depositing a mask over the second opening, forming the dielectric layer in the first opening, removing the mask, depositing the conductive material in the first and second openings, and depositing a second metal layer over the first and second openings.