Abstract: A silicon on insulator (SOI) CMOS circuit, macro and integrated circuit (IC) chip. The chip or macro may include be an SRAM in partially depleted (PD) SOI CMOS. Most field effect transistors (FETs) do not have body contacts. FETs otherwise exhibiting a sensitivity to history effects have body contacts. The body contact for each such FET is connected to at least one other body contact. A back bias voltage may be provided to selected FETs.

Abstract: Silicon on insulator (SOI) field effect transistors (FET) with a shared body contact, a SRAM cell and array including the SOI FETs and the method of forming the SOI FETs. The SRAM cell has a hybrid SOI/bulk structure wherein the source/drain diffusions do not penetrate to the underlying insulator layer, resulting in a FET in the surface of an SOI layer with a body or substrate contact formed at a shared contact. FETs are formed on SOI silicon islands located on a BOX layer and isolated by shallow trench isolation (STI). NFET islands in the SRAM cells include a body contact to a P-type diffusion in the NFET island. Each NFET in the SRAM cells include at least one shallow source/drain diffusion that is shallower than the island thickness. A path remains under the shallow diffusions between NFET channels and the body contact. The P-type body contact diffusion is a deep diffusion, the full thickness of the island. Bit line diffusions shared by SRAM cells on adjacent wordlines may be deep diffusions.

Abstract: An integrated circuit that may include an array such as a static random access memory (SRAM) with high threshold device array devices and in selected other devices to reduce leakage. Devices with high threshold have a thicker gate oxide or a high k dielectric gate oxide that is selected based on threshold voltage (VT) variations with gate oxide dielectric type or gate oxide thickness for the particular technology, e.g., PD SOI CMOS. High threshold devices may be used in non-core circuits, e.g., test circuits. Also, non-critical paths may be identified and a non-critical path margin identified. A thicker device threshold is selected for non-critcal path FETs based on the non-critical path margin. Non-critical path delays are re-checked. FETs are formed with the selected thicker gate oxide for any non-critical paths passing the re-check and in array FETs with non-selected FETs being formed with normal gate oxide thickness.

Abstract: A CMOS storage array such as a static random access memory (SRAM) and a sense amplifier. The SRAM may be in partially depleted (PD) silicon on insulator (SOI) and may include fully depleted (FD) FETs. A power line supply select at each row selectively increases cell supply voltage to a full supply voltage when the row is selected. A word line decoder selects a row of cells that are provided the supply voltage and cells in remaining rows are provided a reduced supply voltage. Leakage is substantially lower in said remaining rows than in said selected row. The sense amplifier may include cross coupled FD NFETs sensing stored data. A read/write-select in each bit path selectively blocks cell writes when cell contents are not being changed. Power is not expended unnecessarily writing to cells.

Abstract: A memory cell includes at least one active device for selectively connecting a supply voltage node to a power line. The power line couples capacitive elements through the at least one active device to the supply voltage node to maintain a high state while accessing a storage node. The high state is provided by a boost created by the addition of the capacitive elements.

Abstract: A read and write assist and restore circuit for a memory device includes a first device, which is responsive to a potential on a bit line such that the potential on the bit line activates the first device. A second device is driven by the first device such that when the first device is activated, a change in the bit line potential is reinforced with positive feedback by the second device during a wordline active period to enable write-back of data lost as a result of threshold voltage fluctuations in memory cell transistors coupled to the bit line.

Abstract: A 64-bit adder implemented in partially depleted silicon on insulator technology and having two levels of lookahead uses a dynamic eight-bit carry module containing a cascode evaluation tree employing a chain of source followers that feeds a sense amplifier, thereby obtaining benefits from high initial drive, low variation in body voltage, resulting in low variation in history-dependent delay, reduced noise sensitivity and noise-based delay.

Abstract: A self-timed data communication system for a wide data width semiconductor memory system having a plurality of data paths is provided. The data communication system includes a central data path including at least one junction circuit configured for exchanging data signals between the central data path and the plurality of data paths of the at least one data path. A respective one junction circuit of the at least one junction circuit includes circuitry for controlling resetting the respective one junction circuit for preparation of a subsequent data transfer through the respective one junction circuit in accordance with receipt of an input junction monitor signal indicating that data has been transferred to the respective one junction circuit. The data communication system further includes a plurality of data banks configured for storing data, wherein a corresponding data bank of the plurality of data banks is connected to a respective one data path of the plurality of data paths.

Abstract: A timing system for controlling timing of data transfers within a semiconductor memory system is provided. The timing system includes a programming circuit for generating a bias signal, wherein the bias signal is biased in accordance with an incoming data transfer address corresponding to a memory address of the memory system, and a delay module for receiving the bias signal and generating an output clock signal, wherein the output clock signal is delayed in accordance with the bias signal.

Abstract: A CMOS storage array such as a static random access memory (SRAM) and a sense amplifier. The SRAM may be in partially depleted (PD) silicon on insulator (SOI) and may include fully depleted (FD) FETs. A power line supply select at each row selectively increases cell supply voltage to a full supply voltage when the row is selected. A word line decoder selects a row of cells that are provided the supply voltage and cells in remaining rows are provided a reduced supply voltage. Leakage is substantially lower in said remaining rows than in said selected row. The sense amplifier may include cross coupled FD NFETs sensing stored data. A read/write-select in each bit path selectively blocks cell writes when cell contents are not being changed. Power is not expended unnecessarily writing to cells.

Abstract: An integrated circuit that may include an array such as a static random access memory (SRAM) with high threshold device array devices and in selected other devices to reduce leakage. Devices with high threshold have a thicker gate oxide or a high k dielectric gate oxide that is selected based on threshold voltage (VT) variations with gate oxide dielectric type or gate oxide thickness for the particular technology, e.g., PD SOI CMOS. High threshold devices may be used in non-core circuits, e.g., test circuits. Also, non-critical paths may be identified and a non-critical path margin identified. A thicker device threshold is selected for non-critcal path FETs based on the non-critical path margin. Non-critical path delays are re-checked. FETs are formed with the selected thicker gate oxide for any non-critical paths passing the re-check and in array FETs with non-selected FETs being formed with normal gate oxide thickness.

Abstract: A MOSFET logic circuit for performing a logic AND operation is presented including three transistors, wherein at least two input signals are provided to the circuit and an output signal indicative of an AND operation performed on a first and second input signal of the at least two input signals is output from the circuit. In another embodiment, a MOSFET true and complement signal generating signal is presented including at least one MOSFET inverter logic circuit, and first and second MOSFET AND logic circuits, wherein each of the first and second AND logic circuits includes three transistors. The true and complement signal generating circuit receives first and second input signals and outputs a true signal and a complement signal indicative of the first input signal.

Abstract: A 64-bit adder implemented in partially depleted silicon on insulator technology and having two levels of lookahead uses a dynamic eight-bit carry module containing a cascode evaluation tree employing a chain of source followers that feeds a sense amplifier, thereby obtaining benefits from high initial drive, low variation in body voltage, resulting in low variation in history-dependent delay, reduced noise sensitivity and noise-based delay.

Abstract: A DRAM array is provided capable of being interchanged between single-cell and twin-cell array operation for storing data in a single-cell or a twin-cell array format, respectively. Preferably, the DRAM array is operated in the single-cell array format during one operating mode and the DRAM array is operated in the twin-cell array format during another operating mode. Wordline decoding circuitry is included for interchanging the DRAM array between single-cell and twin-cell array operation. The wordline decoding circuitry includes a pre-decoder circuit for receiving a control signal and outputting logic outputs to wordline activation circuitry. The wordline activation circuitry then activates at least one wordline traversing the array for interchanging memory cells within the DRAM array between single-cell array operation and twin-cell array operation. Methods are also provided for converting data stored within the DRAM array from the single-cell to the twin-cell array format, and vice versa.

Abstract: A T-RAM array having a planar cell structure is presented. The T-RAM array includes n-MOS and p-MOS support devices which are fabricated by sharing process implant steps with T-RAM cells of the T-RAM array. A method is also presented for fabricating the T-RAM array having the planar cell structure. The method entails simultaneously fabricating a first portion of a T-RAM cell and the n-MOS support device; simultaneously fabricating a second portion of the T-RAM cell and the p-MOS support device; and finishing the fabrication of the T-RAM cell by interconnecting the T-RAM cell with the p-MOS and n-MOS support devices. The first portion of the T-RAM cell is a transfer gate and the second portion of the T-RAM cell is a gated-lateral thyristor storage element. Accordingly, process steps in fabricating the T-RAM cells are shared with process steps in fabricating the n-MOS and p-MOS support devices. The n-MOS and p-MOS support devices refer to sense amplifiers, wordline drivers, column and row decoders, etc.

Abstract: An SRAM system is provided having an array of SRAM cells including at least one circuit receiving a first power voltage and a power control circuit for supplying a second power voltage to at least one selected circuit of the at least one circuit. The system is one of a memory array and a logic system, and a circuit of the at least one circuit is one of a memory cell of the memory array, a sense amplifier of the memory array and a path of the logic system. A method is also provided for providing a power supply voltage to at least one circuit of a system.

Abstract: A 64-bit adder implemented in partially depleted silicon on insulator technology and having two levels of lookahead uses a dynamic eight-bit carry module containing a differential pass-gate evaluation tree employing a chain of source followers that feeds a sense amplifier, thereby obtaining benefits from high initial drive, low variation in body voltage, resulting in low variation in history-dependent delay, reduced noise sensitivity and noise-based delay.

Abstract: Silicon on insulator (SOI) field effect transistors (FET) with a shared body contact, a SRAM cell and array including the SOI FETs and the method of forming the SOI FETs. The SRAM cell has a hybrid SOI/bulk structure wherein the source/drain diffusions do not penetrate to the underlying insulator layer, resulting in a FET in the surface of an SOI layer with a body or substrate contact formed at a shared contact. FETs are formed on SOI silicon islands located on a BOX layer and isolated by shallow trench isolation (STI). NFET islands in the SRAM cells include a body contact to a P-type diffusion in the NFET island. Each NFET in the SRAM cells include at least one shallow source/drain diffusion that is shallower than the island thickness. A path remains under the shallow diffusions between NFET channels and the body contact. The P-type body contact diffusion is a deep diffusion, the full thickness of the island. Bit line diffusions shared by SRAM cells on adjacent wordlines may be deep diffusions.

Abstract: A static random access memory (SRAM) with cells in one portion having a higher beta ratio than the remaining cells of the array. In a first portion, cells have a low &bgr; ratio for high performance. A second portion of the array contains SRAM cells with a higher &bgr; ratio that are more stable than the cells in the first portion, but are somewhat slower.

Abstract: A static random access memory (SRAM) with cells in one portion having a higher beta ratio than the remaining cells of the array. In a first portion, cells have a low &bgr; ratio for high performance. A second portion of the array contains SRAM cells with a higher &bgr; ratio that are more stable than the cells in the first portion, but are somewhat slower.