Abstract: Techniques are provided for fuse/anti-fuse structures, including an inner conductor structure, an insulating layer spaced outwardly of the inner conductor structure, an outer conductor structure disposed outwardly of the insulating layer, and a cavity-defining structure that defines a cavity, with at least a portion of the cavity-defining structure being formed from at least one of the inner conductor structure, the insulating layer, and the outer conductor structure. Methods of making and programming the fuse/anti-fuse structures are also provided.

Abstract: A method (and structure) that selectively forms a dielectric chamber on an electronic device by forming a dummy structure over a semiconductor substrate, depositing a dielectric layer over the dummy structure, forming an opening through the dielectric layer to the dummy structure, and removing the dummy structure to form the dielectric chamber.

Abstract: Bitline variable methods and circuits for evaluating static memory cell dynamic stability provide a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the bitline pre-charge voltage of a static random access memory (SRAM) memory cell, operating the cell and observing changes in performance caused by the changes in the bitline voltage, the dynamic stability of the SRAM cell can be studied over designs and operating environments. Alternatively or in combination, the loading at the outputs of the cell can altered in order to affect the performance of the cell. In addition, cell power supply voltages can be split and set to different levels in order to study the effect of cell asymmetry in combination with bitline pre-charge voltage differences.

Abstract: A compiler is provided for compiling at least one array or bank unit of a DRAM macro such that electrical performance, including cycle time, access time, setup time, among other properties, is optimized. The compiler compiles the DRAM macro according to inputted information. The compiler receives an input capacity and configuration for the DRAM macro. A compiler algorithm determines a number of wordlines and bitlines required to create the DRAM macro of the input capacity. The compiler algorithm optimizes the cycle time and access time of the DRAM macro by properly configuring a support unit of the DRAM macro based upon the number of wordlines and bitlines.

Abstract: The present invention relates to a novel semiconductor SRAM cell structure that includes at least two pull-up transistors, two pull-down transistors, and two pass-gate transistors. In one embodiment, an 8T SRAM cell structure implements a series gating feature for implementing Column Select (CS) and Row Select (WL) cell storage access with enhanced stability. Particularly, the 8-T approach adds two pass-gates, two series connected transistor devices connected at complementary nodes of two cross-coupled inverters, to control column select and row (word) select. In the other embodiment, a 9T SRAM cell structure includes a transmission gate to implement Column Select (CS) and Row Select (WL) cell storage access with enhanced stability. The 9-T approach adds three transistors to perform ANDING function to separate the row select and column select signal functions.

Abstract: Internally asymmetric methods and circuits for evaluating static memory cell dynamic stability provide a mechanism for raising the performance of memory arrays beyond present levels/yields. By altering the internal symmetry of a static random access memory (SRAM) memory cell, operating the cell and observing changes in performance caused by the asymmetric operation, the dynamic stability of the SRAM cell can be studied over designs and operating environments. The asymmetry can be introduced by splitting one or both power supply rail inputs to the cell and providing differing power supply voltages or currents to each cross-coupled stage. Alternatively or in combination, the loading at the outputs of the cell can altered in order to affect the performance of the cell. A memory array with at least one test cell can be fabricated in a production or test wafer and internal nodes of the memory cell can be probed to provide further information.

Abstract: A multi-threshold integrated circuit (IC) that may be supplied by multiple supplies, with an array of latches such as an array static random access memory (SRAM) cells and a CMOS SRAM with improved stability and reduced subthreshold leakage. Selected devices (NFETs and/or PFETs) in array cells and support logic, e.g., in the data path and in non-critical logic, are tailored for lower gate and subthreshold leakage. Normal base FETs have a base threshold and tailored FETs have a threshold above. In a multi-supply chip, circuits with tailored FETs are powered by an increased supply voltage.

Abstract: An Integrated Circuit (IC) chip that may be a bulk CMOS IC chip with silicon on insulator (SOI) Field Effect Transistors (FETs) and method of making the chip. The IC chip includes areas with pockets of buried insulator strata and FETs formed on the strata are SOI FETs. The SOI FETs may include Partially Depleted SOI (PD-SOI) FETs and Fully Depleted SOI (FD-SOI) FETs and the chip may include bulk FETs as well. The FETs are formed by contouring the surface of a wafer, conformally implanting oxygen to a uniform depth, and planarizing to remove the Buried OXide (BOX) in bulk FET regions.

Abstract: A random access memory includes a memory cell having an access device. The access device is switched on or off in accordance with a signal on a wordline to conduct a memory operation through the access device. A logic circuit is coupled to the wordline to delay or gate the wordline signal until an enable signal has arrived at the logic circuit. The access device improves stability and eliminates early read problems.

Abstract: A low power consumption pipeline circuit architecture has power partitioned pipeline stages. The first pipeline stage is non-power-gated for fast response in processing input data after receipt of a valid data signal. A power-gated second pipeline stage has two power-gated modes. Normally the power rail in the power-gated second pipeline stage is charged to a first voltage potential of a pipeline power supply. In the first power gated mode, the power rail is charged to a threshold voltage below the first voltage potential to reduce leakage. In the second power gated mode, the power rail is decoupled from the first voltage potential. A power-gated third pipeline stage has its power rail either coupled to the first voltage potential or power-gated where its power rail is decoupled from the first voltage potential. The power rail of the second power-gated pipeline stage charges to the first voltage potential before the third power-gated pipeline stage.

Abstract: Techniques are provided for selectively biasing wells in a circuit, such as a Complementary Metal Oxide Semiconductor (CMOS) circuit, that has two types of transistors, one type formed on a substrate and another type formed on the wells. For example, the circuit can be a memory circuit, and the selective well bias can be changed depending on whether a READ or WRITE operation is being conducted. In another aspect, cells in a memory circuit can be subjected to variable bias depending on conditions, such as, again, whether a READ or WRITE operation is underway.

Abstract: The present invention generally concerns fabrication methods and device architectures for use in memory circuits, and more particularly concerns hybrid silicon-on-insulator (SOI) and bulk architectures for use in memory circuits. Once aspect of the invention concerns CMOS SRAM cell architectures where at least one pair of adjacent NFETs in an SRAM cell have body regions linked by a leakage path diffusion region positioned beneath shallow source/drain diffusions, where the leakage path diffusion region extends from the bottom of the source/drain diffusion to the buried oxide layer, and at least one pair of NFETs from adjacent SRAM cells which have body regions linked by a similar leakage path diffusion region beneath adjacent source/drain diffusions.

Abstract: A channel 16 of a FinFET 10 has a channel core 24 and a channel envelope 32, each made from a semiconductor material defining a different lattice structure to exploit strained silicon properties. A gate is coupled to the channel envelope through a gate dielectric. Exemplary materials are Si and SixGe1-x, wherein 78<x<92. The channel core 24 has a top surface 26 of width wc and an upstanding surface 28, 30 of height hc, preferably oriented 90° to one another. The channel envelope 32 is in contact with the top 26 and upstanding surfaces 28, 30 so that the area of interface is increased as compared to contact only along the top surface 26, improving electrical conductivity and gate 18 control over the channel 16. The height hc can be tailored to enable a smaller scale FET 10 within a stabilized SRAM. Various methods of making the channel 16 are disclosed, including a mask and etch method, a handle wafer/carrier wafer method, and a shallow trench method.

Abstract: A random access memory includes a memory cell having an access device. The access device is switched on or off in accordance with a signal on a wordline to conduct a memory operation through the access device. A logic circuit is coupled to the wordline to delay or gate the wordline signal until an enable signal has arrived at the logic circuit. The access device improves stability and eliminates early read problems.

Abstract: A multi-port register file, integrated circuit (IC) chip including one or more multi-port register files and method of reading data from the multi-port register file. The supply to storage latches in multi-port register file is selectively bootstrapped above the supply voltage during accesses.

Abstract: Disclosed is a temperature sensor for an integrated circuit having at least one field effect transistor (FET) having a polysilicon gate, in which a current and a voltage is supplied to the polysilicon gate, changes in the current and the voltage of the polysilicon gate are monitored, wherein the polysilicon gate of the at least one FET is electrically isolated from other components of the integrated circuit, and the changes in the current or voltage are used to calculate a change in resistance of the polysilicon gate, and the change in resistance of the polysilicon gate is used to calculate a temperature change within the integrated circuit.

Abstract: A CMOS static random access memory (SRAM) cell array, an integrated chip including the array and a method of accessing cells in the array with improved cell stability. Bit lines connected to half selected cells in the array are floated during cell accesses for improved cell stability.

Abstract: A CMOS static random access memory (SRAM) and a bit select for the SRAM. The bit select includes a dual single-ended sense receiving a difference signal on a bit line pair and selectively sensing signals developing on each bit line independently of the other. Single ended outputs from the dual-ended sense are provided to an output driver. The output driver provides a pair of selectively-complementary output signals.

Abstract: A random access memory includes a logic circuit coupled to a power supply of a column having a memory cell. The logic circuit adjusts the supply voltage for the memory cell in the column in accordance with a control signal. A control circuit is coupled to the logic circuit, which generates the control signal in accordance with an operation type and whether the column is selected, such that the logic circuit selects the supply voltage in accordance with the control signal. The cell may include high mobility devices to improve performance.

Abstract: A method for forming a CMOS well structure including forming a plurality of first conductivity type wells over a substrate, each of the plurality of first conductivity type wells formed in a respective opening in a first mask. A cap is formed over each of the first conductivity type wells, and the first mask is removed. Sidewall spacers are formed on sidewalls of each of the first conductivity type wells. A plurality of second conductivity type wells are formed, each of the plurality of second conductivity type wells are formed between respective first conductivity type wells. A plurality of shallow trench isolations are formed between the first conductivity type wells and second conductive type wells. The plurality of first conductivity type wells are formed by a first selective epitaxial growth process, and the plurality of second conductivity type wells are formed by a second selective epitaxial growth process.