Patents by Inventor Rajiv V. Joshi

Rajiv V. Joshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20020186050
    Abstract: A MOSFET logic circuit for performing a logic AND operation is presented including three transistors, wherein at least two input signals are provided to the circuit and an output signal indicative of an AND operation performed on a first and second input signal of the at least two input signals is output from the circuit. In another embodiment, a MOSFET true and complement signal generating signal is presented including at least one MOSFET inverter logic circuit, and first and second MOSFET AND logic circuits, wherein each of the first and second AND logic circuits includes three transistors. The true and complement signal generating circuit receives first and second input signals and outputs a true signal and a complement signal indicative of the first input signal.
    Type: Application
    Filed: June 7, 2001
    Publication date: December 12, 2002
    Applicant: International Business Machines Corporation
    Inventors: Rajiv V. Joshi, Ruchir Puri
  • Patent number: 6492662
    Abstract: A T-RAM array having a plurality of T-RAM cells is presented where each T-RAM cell has dual vertical devices. Each T-RAM cell has a vertical thyristor and a vertical transfer gate. The top surface of each thyristor is coplanar with the top surface of each transfer gate within the T-RAM array to provide a planar cell structure for the T-RAM array. A method is also presented for fabricating the T-RAM array having the vertical thyristors, the vertical transfer gates and the planar cell structure.
    Type: Grant
    Filed: April 16, 2001
    Date of Patent: December 10, 2002
    Assignee: IBM Corporation
    Inventors: Louis L. Hsu, Rajiv V. Joshi
  • Publication number: 20020171101
    Abstract: A flash memory array having a plurality of bitlines, at least one wordline and a plurality of flash memory flash memory elements, wherein each flash memory element includes two transistors for storing two bits, and wherein each flash memory element is positioned between a pair of adjacent bitlines. A method is also presented for fabricating the flash memory array having the plurality of flash memory elements, wherein each flash memory element is configured for storing two bits.
    Type: Application
    Filed: May 18, 2001
    Publication date: November 21, 2002
    Applicant: International Business machines Corporation
    Inventors: Louis L. Hsu, Rajiv V. Joshi, Carl Radens, Jack A. Mandelman, William R. Tonti
  • Publication number: 20020170019
    Abstract: A compiler is provided for compiling at least one array or bank unit of a DRAM macro such that electrical performance, including cycle time, access time, setup time, among other properties, is optimized. The compiler compiles the DRAM macro according to inputted information. The compiler receives an input capacity and configuration for the DRAM macro. A compiler algorithm determines a number of wordlines and bitlines required to create the DRAM macro of the input capacity. The compiler algorithm optimizes the cycle time and access time of the DRAM macro by properly configuring a support unit of the DRAM macro based upon the number of wordlines and bitlines.
    Type: Application
    Filed: February 26, 2001
    Publication date: November 14, 2002
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Louis L. Hsu, Rajiv V. Joshi, John A. Fifield, Wayne F. Ellis
  • Publication number: 20020151130
    Abstract: A T-RAM array having a plurality of T-RAM cells is presented where each T-RAM cell has dual vertical devices. Each T-RAM cell has a vertical thyristor and a vertical transfer gate. The top surface of each thyristor is coplanar with the top surface of each transfer gate within the T-RAM array to provide a planar cell structure for the T-RAM array. A method is also presented for fabricating the T-RAM array having the vertical thyristors, the vertical transfer gates and the planar cell structure.
    Type: Application
    Filed: April 16, 2001
    Publication date: October 17, 2002
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Louis L. Hsu, Rajiv V. Joshi
  • Publication number: 20020141219
    Abstract: A dataline wiring structural system is provided for an eDRAM which suppresses coupling and switching noise associated with datalines by providing a plurality of metal levels upon which the datalines are positioned. Each of the datalines carrying a differential signal includes at least one vertical twist in which the true and complementary signal components of the differential signal change position from one metal level of the plurality of metal levels to another level.
    Type: Application
    Filed: March 29, 2001
    Publication date: October 3, 2002
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Louis L. Hsu, Rajiv V. Joshi, David R. Hanson
  • Publication number: 20020138688
    Abstract: A DRAM array is provided capable of being interchanged between single-cell and twin-cell array operation for storing data in a single-cell or a twin-cell array format, respectively. Preferably, the DRAM array is operated in the single-cell array format during one operating mode and the DRAM array is operated in the twin-cell array format during another operating mode. Wordline decoding circuitry is included for interchanging the DRAM array between single-cell and twin-cell array operation. The wordline decoding circuitry includes a pre-decoder circuit for receiving a control signal and outputting logic outputs to wordline activation circuitry. The wordline activation circuitry then activates at least one wordline traversing the array for interchanging memory cells within the DRAM array between single-cell array operation and twin-cell array operation. Methods are also provided for converting data stored within the DRAM array from the single-cell to the twin-cell array format, and vice versa.
    Type: Application
    Filed: February 15, 2001
    Publication date: September 26, 2002
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Louis L. Hsu, Rajiv V. Joshi, Fariborz Assaderaghi
  • Publication number: 20020136072
    Abstract: A hierarchical bitline DRAM architecture system is disclosed having a DRAM array which includes master and local bitlines for achieving a DRAM chip having low-power consumption, high-density and small size without affecting the chip's performance, including high random access speed and short cycle time. The DRAM array is designed to be noise-free and to prevent data from being lost during read/write operations. The DRAM array includes a folded-bitline differential sensing scheme and high array efficiency. The DRAM array has a minimum amount of sense amplifiers as compared to conventional DRAMs to save chip area and conserve power. The DRAM array is capable of storing data in both the single-cell and twin-cell array format and is interchangeable between single-cell and twin-cell array operation.
    Type: Application
    Filed: March 21, 2001
    Publication date: September 26, 2002
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Louis L. Hsu, Rajiv V. Joshi
  • Patent number: 6456521
    Abstract: A hierarchical bitline DRAM architecture system is disclosed having a DRAM array which includes master and local bitlines for achieving a DRAM chip having low-power consumption, high-density and small size without affecting the chip's performance, including high random access speed and short cycle time. The DRAM array is designed to be noise-free and to prevent data from being lost during read/write operations. The DRAM array includes a folded-bitline differential sensing scheme and high array efficiency. The DRAM array has a minimum amount of sense amplifiers as compared to conventional DRAMs to save chip area and conserve power. The DRAM array is capable of storing data in both the single-cell and twin-cell array format and is interchangeable between single-cell and twin-cell array operation.
    Type: Grant
    Filed: March 21, 2001
    Date of Patent: September 24, 2002
    Assignee: International Business Machines Corporation
    Inventors: Louis L. Hsu, Rajiv V. Joshi
  • Publication number: 20020133789
    Abstract: The present invention provides a temperature programmable timing delay system utilizing circuitry for generating a band-gap reference and for sensing the on-chip temperature of an integrated circuit chip. The circuitry outputs the sensed temperature as a binary output which is received by a programmable table circuit of the timing delay system. The programmable table circuit outputs a binary output corresponding to the received binary output. The timing delay system further includes a temperature dependent timing delay circuit having inputs for receiving the binary output of the programmable table circuit and an output for outputting a timing delay signal for delaying a clock by a timing delay corresponding to the binary output of the programmable table circuit. The band-gap reference can be a temperature independent band-gap reference voltage having a constant-voltage value or a temperature dependent band-gap reference current having a constant-current value.
    Type: Application
    Filed: January 5, 2001
    Publication date: September 19, 2002
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Louis L. Hsu, Rajiv V. Joshi, John A. Fifield
  • Patent number: 6452855
    Abstract: A DRAM array is provided capable of being interchanged between single-cell and twin-cell array operation for storing data in a single-cell or a twin-cell array format, respectively. Preferably, the DRAM array is operated in the single-cell array format during one operating mode and the DRAM array is operated in the twin-cell array format during another operating mode. Switching circuitry is included for interchanging between single-cell and twin-cell array operation, and vice versa. Methods are also provided for converting data stored within the DRAM array from the single-cell to the twin-cell array format, and vice versa.
    Type: Grant
    Filed: January 5, 2001
    Date of Patent: September 17, 2002
    Assignee: International Business Machines Corp.
    Inventors: Louis L. Hsu, Rajiv V. Joshi, John A. Fifield, Wayne F. Ellis
  • Patent number: 6445626
    Abstract: A column redundancy architecture system for an embedded DRAM (eDRAM) having a wide data bandwidth and wide internal bus width is disclosed which provides column redundancy to defective datalines of the eDRAM. Internally generated column addresses of defective columns of each micro cell block are stored in a memory device during eDRAM array testing. Two redundancy reroute mechanisms are disclosed. The first redundancy reroute mechanism selects at least one defective dataline of the eDRAM and directly replaces the defective dataline(s) with at least one redundancy dataline. The second redundancy reroute mechanism discards the defective dataline column and replaces it with an adjacent dataline column. The dataline columns following the defective dataline column are then replaced with the next adjacent dataline columns including a redundancy dataline column.
    Type: Grant
    Filed: March 29, 2001
    Date of Patent: September 3, 2002
    Assignee: IBM Corporation
    Inventors: Louis L. Hsu, Rajiv V. Joshi, Gregory J. Fredeman
  • Patent number: 6445638
    Abstract: A dual-port, folded-bitline DRAM architecture system is presented which prioritizes two simultaneous access requests slated for a DRAM cell of a data array prior to performing at least one of the access requests to prevent affecting the integrity of the data while suppressing noise due to wordline-to-bitline coupling, bitline-to-bitline coupling, and bitline-to-substrate coupling. If the two access requests are write-read, the system prioritizes the two access requests as being equal to each other. The system then simultaneously performs the write and read access by accessing the corresponding DRAM cell through the first port to write the data while simultaneously writing the data through to an output bus, which is equivalent to a read access. In another embodiment of the present invention, a dual-port, shared-address bus DRAM architecture system is presented which also prioritizes two simultaneous access requests slated for the DRAM cell of a data array.
    Type: Grant
    Filed: September 19, 2000
    Date of Patent: September 3, 2002
    Assignee: International Business Machines Corporation
    Inventors: Louis L. Hsu, Rajiv V. Joshi, Radens Carl
  • Patent number: 6442735
    Abstract: A computer program product method of circuit design of a multiple input circuit, macro or chip, especially for silicon on insulator (SOI) circuits. For a multiple input circuit, an object list of items corresponding to circuit devices is created. The items model local effects on corresponding circuit elements. The circuit is analyzed using Static or DC analysis to provide initial local effects on circuit devices, including body effects and local heat effects. The initial local effects are passed to the circuit model for transient analysis. The local effects from checked transient results are checked and updated. The transient response is rerun and the local effects are updated until the change in local effects is below an upper limit. For added efficiency, unswitching devices may be eliminated from the iterative analysis and analysis may be limited to the period when switching occurs.
    Type: Grant
    Filed: March 15, 2000
    Date of Patent: August 27, 2002
    Assignee: International Business Machines Corp.
    Inventors: Rajiv V. Joshi, Karl E. Kroell
  • Publication number: 20020100918
    Abstract: A T-RAM array having a planar cell structure is presented. The T-RAM array includes n-MOS and p-MOS support devices which are fabricated by sharing process implant steps with T-RAM cells of the T-RAM array. A method is also presented for fabricating the T-RAM array having the planar cell structure. The method entails simultaneously fabricating a first portion of a T-RAM cell and the n-MOS support device; simultaneously fabricating a second portion of the T-RAM cell and the p-MOS support device; and finishing the fabrication of the T-RAM cell by interconnecting the T-RAM cell with the p-MOS and n-MOS support devices. The first portion of the T-RAM cell is a transfer gate and the second portion of the T-RAM cell is a gated-lateral thyristor storage element. Accordingly, process steps in fabricating the T-RAM cells are shared with process steps in fabricating the n-MOS and p-MOS support devices. The n-MOS and p-MOS support devices refer to sense amplifiers, wordline drivers, column and row decoders, etc.
    Type: Application
    Filed: January 26, 2001
    Publication date: August 1, 2002
    Inventors: Louis L. Hsu, Rajiv V. Joshi, Fariborz Assaderaghi, Dan Moy, Werner Rausch, James Culp
  • Publication number: 20020096359
    Abstract: The present invention provides for globally aligning microelectronic circuit systems, such as communication devices and chips, fabricated on or bonded to the front and back sides of one or more substrates to provide for wireless communications between the circuit systems through the one or more substrates. In one embodiment, two circuit systems situated on opposite sides of a substrate are aligned to provide for wireless communications between the two circuit systems through the substrate. In another embodiment, communication devices situated on one or more substrates are aligned to provide for wireless communications between the communication devices through the one or more substrates. In another embodiment, two chips situated on opposite sides of a transparent substrate are aligned to provide for wireless communications between the two chips through the transparent substrate.
    Type: Application
    Filed: January 25, 2001
    Publication date: July 25, 2002
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Louis L. Hsu, Rajiv V. Joshi, Carl Radens, Jack A. Mandelman, Tsorng-Dih Yuan
  • Publication number: 20020093030
    Abstract: A T-RAM array having a planar cell structure is presented which includes a plurality of T-RAM cells. Each of the plurality of T-RAM cells is fabricated by using doped polysilicon to form a self-aligned diffusion region to create a low-contact resistance p+ diffusion region. A silicided p+ polysilicon wire is preferably used to connect each of the plurality of the T-RAM cells to a reference voltage Vref. A self-aligned junction region is formed between every two wordlines by implanting a n+ implant into a gap between every two wordlines. The self-aligned junction region provides for a reduction in the T-RAM cell size from a cell size of 8F2 for a prior art T-RAM cell to a cell size of less than or equal to 6F2. Preferably, the T-RAM array is built on a semiconductor silicon-on-insulator (SOI) wafer to reduce junction capacitance and improve scalability.
    Type: Application
    Filed: January 16, 2001
    Publication date: July 18, 2002
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Louis L. Hsu, Rajiv V. Joshi, Fariborz Assaderaghi
  • Publication number: 20020089872
    Abstract: A DRAM array is provided capable of being interchanged between single-cell and twin-cell array operation for storing data in a single-cell or a twin-cell array format, respectively. Preferably, the DRAM array is operated in the single-cell array format during one operating mode and the DRAM array is operated in the twin-cell array format during another operating mode. Switching circuitry is included for interchanging between single-cell and twin-cell array operation, and vice versa. Methods are also provided for converting data stored within the DRAM array from the single-cell to the twin-cell array format, and vice versa.
    Type: Application
    Filed: January 5, 2001
    Publication date: July 11, 2002
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Louis L. Hsu, Rajiv V. Joshi, John A. Fifield, Wayne F. Ellis
  • Patent number: 6396324
    Abstract: A clock system is provided capable of using an external system clock for driving at least one charge circuit of a semiconductor memory unit for restoring and refreshing a data array of the memory unit. The clock system, in one embodiment, includes a plurality of control circuits each having a clock select circuit which has as an input the external system clock, an internal clock generator circuit for generating an internal system clock, and a multiplexer. The multiplexer has as inputs an output of the clock select circuit, i.e., the external system clock, and an output of the internal clock generator circuit, i.e., the internal system clock. The multiplexer outputs either the external system clock or the internal system clock to the at least one charge circuit according to at least one control signal transmitted by a central processing unit to the clock select circuit.
    Type: Grant
    Filed: May 8, 2000
    Date of Patent: May 28, 2002
    Assignee: International Business Machines Corporation
    Inventors: Louis L. Hsu, Rajiv V. Joshi, Richard M. Parent, Matthew R. Wordeman
  • Publication number: 20020057126
    Abstract: A low-voltage, low-power DC voltage generator system is provided having two negative voltage pump circuits for generating voltages for operating negative wordline and substrate bias charge pump circuits, a reference generator for generating a reference voltage, and a two-stage cascaded positive pump system having a first stage pump circuit and a second stage pump circuit. The first stage converts a supply voltage to a higher voltage level, e.g., one volt to 1.5 volts, to be used for I/O drivers, and the second stage converts the output voltage from the first stage to a higher voltage level, e.g., from 1.5 volts to about 2.5 volts, for operating a boost wordline charge pump circuit. The DC voltage generator system further includes a micro pump circuit for providing a voltage level which is greater than one-volt to be used as reference voltages, even when an operating voltage of the DC voltage generator system is at or near one-volt.
    Type: Application
    Filed: January 3, 2002
    Publication date: May 16, 2002
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Louis L. Hsu, Rajiv V. Joshi, Russell J. Houghton, Wayne F. Ellis, Jeffrey H. Dreibelbis