Patents by Inventor Rajiv Yadav Ranjan

Rajiv Yadav Ranjan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8772886
    Abstract: A spin transfer torque memory random access memory (STTMRAM) element is capable of switching states when electrical current is applied thereto for storing data and includes the following layers. An anti-ferromagnetic layer, a fixed layer formed on top of the anti-ferromagnetic layer, a barrier layer formed on top of the second magnetic layer of the fixed layer, and a free layer including a first magnetic layer formed on top of the barrier layer, a second magnetic layer formed on top of the first magnetic layer, a non-magnetic insulating layer formed on top of the second magnetic layer and a third magnetic layer formed on top of the non-magnetic insulating layer. A capping layer is formed on top of the non-magnetic insulating layer.
    Type: Grant
    Filed: May 2, 2011
    Date of Patent: July 8, 2014
    Assignee: Avalanche Technology, Inc.
    Inventors: Yiming Huai, Rajiv Yadav Ranjan, Ioan Tudosa, Roger Klas Malmhall, Yuchen Zhou
  • Publication number: 20140170776
    Abstract: Fabrication methods using Ion Beam Etching (IBE) for MRAM cell memory elements are described. In embodiments of the invention the top electrode and MTJ main body are etched with one mask using reactive etching such as RIE or magnetized inductively coupled plasma (MICP) for improved selectivity, then the bottom electrode is etched using IBE as specified in various alternative embodiments which include selection of incident angles, wafer rotational rate profiles and optional passivation layer deposited prior to the IBE. The IBE according to the invention etches the bottom electrode without the need for an additional mask by using the layer stack created by the first etching phase as the mask. This makes the bottom electrode self-aligned to MTJ. The IBE also achieves MTJ sidewall cleaning without the need for an additional step.
    Type: Application
    Filed: December 4, 2013
    Publication date: June 19, 2014
    Applicant: Avalanche Technology Inc.
    Inventors: Kimihiro Satoh, Dong Ha Jung, Jing Zhang, Benjamin Chen, Yiming Huai, Rajiv Yadav Ranjan, Yuchen Zhou
  • Patent number: 8724379
    Abstract: A multi-state low-current-switching magnetic memory element (magnetic memory element) comprising a free layer, two stacks, and a magnetic tunneling junction is disclosed. The stacks and magnetic tunneling junction are disposed upon surfaces of the free layer, with the magnetic tunneling junction located between the stacks. The stacks pin magnetic domains within the free layer, creating a free layer domain wall. A current passed from stack to stack pushes the domain wall, repositioning the domain wall within the free layer. The position of the domain wall relative to the magnetic tunnel junction corresponds to a unique resistance value, and passing current from a stack to the magnetic tunnel junction reads the magnetic memory element's resistance. Thus, unique memory states may be achieved by moving the domain wall.
    Type: Grant
    Filed: April 5, 2013
    Date of Patent: May 13, 2014
    Assignee: Avalanche Technology, Inc.
    Inventors: Rajiv Yadav Ranjan, Roger Klaus Malmhall, Parviz Keshtbod
  • Patent number: 8724413
    Abstract: A multi-state current-switching magnetic memory element includes a stack of magnetic tunneling junction (MTJ) separated by a non-magnetic layer for storing more than one bit of information, wherein different levels of current applied to the memory element cause switching to different states.
    Type: Grant
    Filed: September 16, 2011
    Date of Patent: May 13, 2014
    Assignee: Avalanche Technology, Inc.
    Inventors: Rajiv Yadav Ranjan, Mahmud Assar, Parviz Keshtbod
  • Patent number: 8711613
    Abstract: A flash-RAM memory includes non-volatile random access memory (RAM) formed on a monolithic die and non-volatile page-mode memory formed on top of the non-volatile RAM, the non-volatile page-mode memory and the non-volatile RAM reside on the monolithic die. The non-volatile RAM is formed of stacks of magnetic memory cells arranged in three-dimensional form for higher density and lower costs.
    Type: Grant
    Filed: May 10, 2013
    Date of Patent: April 29, 2014
    Assignee: Avalanche Technology, Inc.
    Inventors: Rajiv Yadav Ranjan, Parviz Keshtbod, Mahmud Assar
  • Patent number: 8687418
    Abstract: An embodiment of the present invention includes a non-volatile storage unit comprising a first and second N-diffusion well separated by a distance of P-substrate. A first isolation layer is formed upon the first and second N-diffusion wells and the P-substrate. A nano-pillar charge trap layer is formed upon the first isolation layer and includes conductive nano-pillars interspersed between non-conducting regions. The storage unit further includes a second isolation layer formed upon the nano-pillar charge trap layer; and at least one word line formed upon the second isolation layer and above a region of nano-pillar charge trap layer. The nano-pillar charge trap layer is operative to trap charge upon application of a threshold voltage. Subsequently, the charge trap layer may be read to determine any charge stored in the non-volatile storage unit, where presence or absence of stored charge in the charge trap layer corresponds to a bit value.
    Type: Grant
    Filed: November 20, 2009
    Date of Patent: April 1, 2014
    Assignee: Avalanche Technology, Inc.
    Inventors: Rajiv Yadav Ranjan, Ebrahim Abedifard, Petro Estakhri, Parviz Keshtbod
  • Publication number: 20140027697
    Abstract: A STTMRAM element includes a magnetization layer made of a first free layer and a second free layer, separated by a non-magnetic separation layer (NMSL), with the first and second free layers each having in-plane magnetizations that act on each other through anti-parallel coupling. The direction of the magnetization of the first and second free layers each is in-plane prior to the application of electrical current to the STTMRAM element and thereafter, the direction of magnetization of the second free layer becomes substantially titled out-of-plane and the direction of magnetization of the first free layer switches. Upon electrical current being discontinued to the STTMRAM element, the direction of magnetization of the second free layer remains in a direction that is substantially opposite to that of the first free layer.
    Type: Application
    Filed: June 19, 2013
    Publication date: January 30, 2014
    Inventors: Yuchen Zhou, Yiming Huai, Jing Zhang, Rajiv Yadav Ranjan, Roger Klas Malmhall
  • Patent number: 8633720
    Abstract: High-frequency resonance method is used to measure magnetic parameters of magnetic thin film stacks that show magnetoresistance including MTJs and giant magnetoresistance spin valves. The thin film sample can be unpatterned. Probe tips are electrically connected to the surface of the film (or alternatively one probe tip can be punched into the thin film stack) and voltage measurements are taken while injecting high frequency oscillating current between them to cause a change in electrical resistance when one of the layers in the magnetic film stack changes direction. A measured resonance curve can be determined from voltages at different current frequencies. The damping, related to the width of the resonance curve peak, is determined through curve fitting. In embodiments of the invention a variable magnetic field is also applied to vary the resonance frequency and extract the magnetic anisotropy and/or magnetic saturation of the magnetic layers.
    Type: Grant
    Filed: June 21, 2011
    Date of Patent: January 21, 2014
    Assignee: Avalanche Technology Inc.
    Inventors: Ioan Tudosa, Yuchen Zhou, Jing Zhang, Rajiv Yadav Ranjan, Yiming Huai
  • Publication number: 20140015078
    Abstract: A spin transfer torque memory random access memory (STTMRAM) element is capable of switching states when electrical current is applied thereto for storing data and includes the following layers. An anti-ferromagnetic layer, a fixed layer formed on top of the anti-ferromagnetic layer, a barrier layer formed on top of the second magnetic layer of the fixed layer, and a free layer including a first magnetic layer formed on top of the barrier layer, a second magnetic layer formed on top of the first magnetic layer, a nonmagnetic insulating layer formed on top of the second magnetic layer and a third magnetic layer formed on top of the non-magnetic insulating layer. A capping layer is formed on top of the non-magnetic insulating layer.
    Type: Application
    Filed: September 16, 2013
    Publication date: January 16, 2014
    Applicant: Avalanche Technology Inc.
    Inventors: Yiming Huai, Rajiv Yadav Ranjan, Roger Klas Malmhall, Yuchen Zhou
  • Publication number: 20140017818
    Abstract: In accordance with a method of the present invention, a method of manufacturing a magnetic random access memory (MRAM) cell and a corresponding structure thereof are disclosed to include a multi-stage manufacturing process. The multi-stage manufacturing process includes performing a front end on-line (FEOL) stage to manufacture logic and non-magnetic portions of the memory cell by forming an intermediate interlayer dielectric (ILD) layer, forming intermediate metal pillars embedded in the intermediate ILD layer, depositing a conductive metal cap on top of the intermediate ILD layer and the metal pillars, performing magnetic fabrication stage to make a magnetic material portion of the memory cell being manufactured, and performing back end on-line (BEOL) stage to make metal and contacts of the memory cell being manufactured.
    Type: Application
    Filed: September 16, 2013
    Publication date: January 16, 2014
    Applicant: Avalanche Technology, Inc.
    Inventors: Rajiv Yadav RANJAN, Parviz KESHTBOD, Roger Klas MALMHALL
  • Publication number: 20140011296
    Abstract: One embodiment of the present invention includes a diode-addressable current-induced magnetization switching (CIMS) memory element including a magnetic tunnel junction (MTJ) and a diode formed on top of the MTJ for addressing the MTJ.
    Type: Application
    Filed: September 3, 2013
    Publication date: January 9, 2014
    Applicant: Avalanche Technology, Inc.
    Inventors: Rajiv Yadav Ranjan, Parviz Keshtbod
  • Patent number: 8611147
    Abstract: A spin-torque transfer memory random access memory (STTMRAM) element, employed in a STTMRAM array, receives electric current for storage of digital information, the STTMRAM element has a magnetic tunnel junction (MTJ). The MTJ includes an anti-ferromagnetic (AF) layer, a fixed layer having a magnetization that is substantially fixed in one direction and that comprises a first magnetic layer, an AF coupling layer and a second magnetic layer, a barrier layer formed upon the fixed layer, and a free layer. The free layer is synthetic and has a high-polarization magnetic layer, a low-crystallization magnetic layer, a non-magnetic separation layer, and a magnetic layer, wherein during a write operation, a bidirectional electric current is applied across the STTMRAM element to switch the magnetization of the free layer between parallel and anti-parallel states relative to the magnetization of the fixed layer.
    Type: Grant
    Filed: March 22, 2013
    Date of Patent: December 17, 2013
    Assignee: Avalanche Technology, Inc.
    Inventors: Rajiv Yadav Ranjan, Roger Klas Malmhall, Yiming Huai
  • Patent number: 8598576
    Abstract: A spin toque transfer magnetic random access memory (STTMRAM) element comprises a reference layer, formed on a substrate, with a fixed perpendicular magnetic component. A junction layer is formed on top of the reference layer and a free layer is formed on top of the junction layer with a perpendicular magnetic orientation, at substantially its center of the free layer and switchable. A spacer layer is formed on top of the free layer and a fixed layer is formed on top of the spacer layer, the fixed layer has a fixed perpendicular magnetic component opposite to that of the reference layer. The magnetic orientation of the free layer switches relative to that of the fixed layer. The perpendicular magnetic components of the fixed layer and the reference layer substantially cancel each other and the free layer has an in-plane edge magnetization field.
    Type: Grant
    Filed: February 16, 2011
    Date of Patent: December 3, 2013
    Assignee: Avalanche Technology, Inc.
    Inventors: Yuchen Zhou, Yiming Huai, Rajiv Yadav Ranjan
  • Patent number: 8593862
    Abstract: A spin-torque transfer memory random access memory (STTMRAM) element includes a fixed layer formed on top of a substrate and a tunnel layer formed upon the fixed layer and a composite free layer formed upon the tunnel barrier layer and made of an iron platinum alloy with at least one of X or Y material, X being from a group consisting of: boron (B), phosphorous (P), carbon (C), and nitride (N) and Y being from a group consisting of: tantalum (Ta), titanium (Ti), niobium (Nb), zirconium (Zr), tungsten (W), silicon (Si), copper (Cu), silver (Ag), aluminum (Al), chromium (Cr), tin (Sn), lead (Pb), antimony (Sb), hafnium (Hf) and bismuth (Bi), molybdenum (Mo) or rhodium (Ru), the magnetization direction of each of the composite free layer and fixed layer being substantially perpendicular to the plane of the substrate.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: November 26, 2013
    Assignee: Avalanche Technology, Inc.
    Inventors: Rajiv Yadav Ranjan, Roger Klas Malmhall
  • Patent number: 8574928
    Abstract: Fabrication methods for MRAM are described wherein any re-deposited metal on the sidewalls of the memory element pillars is cleaned before the interconnection process is begun. In embodiments the pillars are first fabricated, then a dielectric material is deposited on the pillars over the re-deposited metal on the sidewalls. The dielectric material substantially covers any exposed metal and therefore reduces sources of re-deposition during subsequent etching. Etching is then performed to remove the dielectric material from the top electrode and the sidewalls of the pillars down to at least the bottom edge of the barrier. The result is that the previously re-deposited metal that could result in an electrical short on the sidewalls of the barrier is removed. Various embodiments of the invention include ways of enhancing or optimizing the process. The bitline interconnection process proceeds after the sidewalls have been etched clean as described.
    Type: Grant
    Filed: April 10, 2012
    Date of Patent: November 5, 2013
    Assignee: Avalanche Technology Inc.
    Inventors: Kimihiro Satoh, Yiming Huai, Yuchen Zhou, Jing Zhang, Dong Ha Jung, Ebrahim Abedifard, Rajiv Yadav Ranjan, Parviz Keshtbod
  • Publication number: 20130286723
    Abstract: A spin toque transfer magnetic random access memory (STTMRAM) element comprises a reference layer, which can be a single layer structure or a synthetic multi-layer structure, formed on a substrate, with a fixed perpendicular magnetic component. A junction layer is formed on top of the reference layer and a free layer is formed on top of the junction layer with a perpendicular magnetic orientation, at substantially its center of the free layer and switchable. A spacer layer is formed on top of the free layer and a fixed layer is formed on top of the spacer layer, the fixed layer has a fixed perpendicular magnetic component opposite to that of the reference layer. The magnetic orientation of the free layer switches relative to that of the fixed layer. The perpendicular magnetic components of the fixed layer and the reference layer substantially cancel each other and the free layer has an in-plane edge magnetization field.
    Type: Application
    Filed: June 26, 2013
    Publication date: October 31, 2013
    Inventors: Yuchen Zhou, Yiming Huai, Rajiv Yadav Ranjan, Jing Zhang
  • Publication number: 20130282963
    Abstract: A flash-RAM memory includes non-volatile random access memory (RAM) formed on a monolithic die and non-volatile page-mode memory formed on top of the non-volatile RAM, the non-volatile page-mode memory and the non-volatile RAM reside on the monolithic die. The non-volatile RAM is formed of stacks of magnetic memory cells arranged in three-dimensional form for higher density and lower costs.
    Type: Application
    Filed: May 10, 2013
    Publication date: October 24, 2013
    Inventors: Rajiv Yadav Ranjan, Parviz Keshtbod, Mahmud Assar
  • Patent number: 8565010
    Abstract: A spin toque transfer magnetic random access memory (STTMRAM) element comprises a reference layer formed on a substrate, with a fixed perpendicular magnetic component. A junction layer is formed on top of the reference layer and a free layer is formed on top of the junction layer with a perpendicular magnetic orientation, at substantially its center of the free layer and switchable. A spacer layer is formed on top of the free layer and a fixed layer is formed on top of the spacer layer, the fixed layer has a fixed perpendicular magnetic component opposite to that of the reference layer. The magnetic orientation of the free layer switches relative to that of the fixed layer. The perpendicular magnetic components of the fixed layer and the reference layer substantially cancel each other and the free layer has an in-plane edge magnetization field.
    Type: Grant
    Filed: May 2, 2011
    Date of Patent: October 22, 2013
    Assignee: Avalanche Technology, Inc.
    Inventors: Yuchen Zhou, Yiming Huai, Rajiv Yadav Ranjan, Jing Zhang
  • Publication number: 20130267042
    Abstract: Fabrication methods for MRAM are described wherein any re-deposited metal on the sidewalls of the memory element pillars is cleaned before the interconnection process is begun. In embodiments the pillars are first fabricated, then a dielectric material is deposited on the pillars over the re-deposited metal on the sidewalls. The dielectric material substantially covers any exposed metal and therefore reduces sources of re-deposition during subsequent etching. Etching is then performed to remove the dielectric material from the top electrode and the sidewalls of the pillars down to at least the bottom edge of the barrier. The result is that the previously re-deposited metal that could result in an electrical short on the sidewalls of the barrier is removed. Various embodiments of the invention include ways of enhancing or optimizing the process. The bitline interconnection process proceeds after the sidewalls have been etched clean as described.
    Type: Application
    Filed: April 10, 2012
    Publication date: October 10, 2013
    Inventors: Kimihiro Satoh, Yiming Huai, Yuchen Zhou, Jing Zhang, Dong Ha Jung, Ebrahim Abedifard, Rajiv Yadav Ranjan, Parviz Keshtbod
  • Publication number: 20130258764
    Abstract: A multi-state spin-torque transfer magnetic random access memory (STTMRAM) is formed on a film and includes a first magnetic tunneling junctions (MTJ) having a first fixed layer, a first sub-magnetic tunnel junction (sub-MTJ) layer and a first free layer. The first fixed layer and first free layer each have a first magnetic anisotropy. The STTMRAM further includes a non-magnetic spacing layer formed on top of the first MTJ layer and a second MTJ formed on top of the non-magnetic spacing layer. The second MTJ has a second fixed layer, a second sub-MTJ layer and a second free layer. The second fixed and second free layers each have a second magnetic anisotropy, wherein at least one of the first or second magnetic anisotropy is perpendicular to the plane of the film.
    Type: Application
    Filed: May 13, 2013
    Publication date: October 3, 2013
    Applicant: Avalanche Technology, Inc.
    Inventors: Rajiv Yadav Ranjan, Parviz Keshtbod