Abstract: A metal-insulator-metal (MIM) capacitor including a metal layer, an insulating layer formed on the metal layer, at least a first opening and at least a second opening formed in the first insultaing layer, a dielectric layer formed in the first opening, a conductive material deposited in the first and second openings, and a first metal plate formed over the first opening and a second metal plate formed over the second opening. A method for fabricating the MIM capacitor, includes forming the first metal layer, forming the insulating layer on the first metal layer, forming at least the first opening and at least the second opening in the first insultaing layer, depositing a mask over the second opening, forming the dielectric layer in the first opening, removing the mask, depositing the conductive material in the first and second openings, and depositing a second metal layer over the first and second openings.

Abstract: There is provided a method for managing a multi-level power supply. The method includes comparing a voltage level (Vs1) of a lower voltage supply bus to a voltage level (Vs2) of a higher voltage supply bus, and routing current from the lower voltage supply bus to the higher voltage supply bus if Vs2<Vs1. The lower and higher voltage supply busses provide power to a complementary metal oxide semiconductor (CMOS) circuit. The method prevents a latch-up of the CMOS circuit. There is also provided a circuit that employs the method.

Abstract: A field effect transistor (FET), integrated circuit (IC) chip including the FETs and a method of forming the FETs. The FETs include a thin channel with raised source/drain (RSD) regions at each end on an insulator layer, e.g., on an ultra-thin silicon on insulator (SOI) chip. Isolation trenches at each end of the FETs, i.e., at the end of the RSD regions, isolate and define FET islands. Insulating sidewalls at each RSD region sandwich the FET gate between the RSD regions. The gate dielectric may be a high K dielectric. Salicide on the RSD regions and, optionally, on the gates reduce device resistances.

Abstract: A channel 16 of a FinFET 10 has a channel core 24 and a channel envelope 32, each made from a semiconductor material defining a different lattice structure to exploit strained silicon properties. A gate is coupled to the channel envelope through a gate dielectric. Exemplary materials are Si and SixGe1-x, wherein 78<x<92. The channel core 24 has a top surface 26 of width wc and an upstanding surface 28, 30 of height hc, preferably oriented 90° to one another. The channel envelope 32 is in contact with the top 26 and upstanding surfaces 28, 30 so that the area of interface is increased as compared to contact only along the top surface 26, improving electrical conductivity and gate 18 control over the channel 16. The height hc can be tailored to enable a smaller scale FET 10 within a stabilized SRAM. Various methods of making the channel 16 are disclosed, including a mask and etch method, a handle wafer/carrier wafer method, and a shallow trench method.

Abstract: A method (and structure) that selectively forms a dielectric chamber on an electronic device by forming a dummy structure over a semiconductor substrate, depositing a dielectric layer over the dummy structure, forming an opening through the dielectric layer to the dummy structure, and removing the dummy structure to form the dielectric chamber.

Abstract: An integrated circuit (IC), random access memory on an IC and method of neutralizing device floating body effects. A floating body effect monitor monitors circuit/array activity and selectively provides an indication of floating body effect manifestation from inactivity, including the lapse of time since the most recent activity or memory access. A pulse generator generates a neutralization pulse in response to an indication of inactivity. A neutralization pulse distribution circuit passes the neutralization pulse to blocks in the circuit path or to array cells.

Abstract: Bit and write decode/drivers, a random access memory (RAM) including the decode/drivers and an IC with a static RAM (SRAM) including the decode/drivers. The decode/drivers are clocked by a local clock and each produce access pulses wider than corresponding clock pulses. The bit decode/driver produces bit select pulses that are wider than a word select pulse and the write decode/driver produces write pulses that are wider than the bit select pulses for stable self timed RAM write accesses.

Abstract: A row redundancy system is provided for replacing faulty wordlines of a memory array having a plurality of banks. The row redundancy system includes a remote fuse bay storing at least one faulty address corresponding to a faulty wordline of the memory array; a row fuse array for storing row fuse information corresponding to at least one bank of the memory array; and a copy logic module for copying at least one faulty address stored in the remote fuse bay into the row fuse array; wherein the copy logic module is programmed to copy the at least one faulty address into the row fuse information stored in the row fuse array corresponding to a predetermined number of banks in accordance with a selectable repair field size.

Abstract: A level converter for interfacing two circuits supplied by different supply voltages, and integrated circuit including the level converter interfacing circuit in two different voltage islands. A first buffer is supplied by a virtual supply and receives an input signal from a lower voltage circuit. The first buffer drives a second buffer, which is supplied by a higher supply voltage. An output from the second buffer switches a supply select to selectively pass the higher supply voltage or a reduced supply voltage to the first buffer.

Abstract: A method for forming a CMOS well structure including forming a plurality of first conductivity type wells over a substrate, each of the plurality of first conductivity type wells formed in a respective opening in a first mask. A cap is formed over each of the first conductivity type wells, and the first mask is removed. Sidewall spacers are formed on sidewalls of each of the first conductivity type wells. A plurality of second conductivity type wells are formed, each of the plurality of second conductivity type wells are formed between respective first conductivity type wells. A plurality of shallow trench isolations are formed between the first conductivity type wells and second conductive type wells. The plurality of first conductivity type wells are formed by a first selective epitaxial growth process, and the plurality of second conductivity type wells are formed by a second selective epitaxial growth process.

Abstract: A method (and structure) that selectively forms a dielectric chamber on an electronic device by forming a dummy structure over a semiconductor substrate, depositing a dielectric layer over the dummy structure, forming an opening through the dielectric layer to the dummy structure, and removing the dummy structure to form the dielectric chamber.

Abstract: A CMOS static random access memory (SRAM) cell array, an integrated chip including the array and a method of accessing cells in the array with improved cell stability.

Abstract: Methods for designing a 6T SRAM cell having greater stability and/or a smaller cell size are provided. A 6T SRAM cell has a pair access transistors (NFETs), a pair of pull-up transistors (PFETs), and a pair of pull-down transistors (NFETs), wherein the access transistors have a higher threshold voltage than the pull-down transistors, which enables the SRAM cell to effectively maintain a logic “0” during access of the cell thereby increasing the stability of the cell, especially for cells during “half select.” Further, a channel width of a pull-down transistor can be reduced thereby decreasing the size of a high performance six transistor SRAM cell without effecting cell the stability during access. And, by decreasing the cell size, the overall design layout of a chip may also be decreased.

Abstract: A multi-threshold integrated circuit (IC) that may be supplied by multiple supplies, with an array of latches such as an array static random access memory (SRAM) cells and a CMOS SRAM with improved stability and reduced subthreshold leakage. Selected devices (NFETs and/or PFETs) in array cells and support logic, e.g., in the data path and in non-critical logic, are tailored for lower gate and subthreshold leakage. Normal base FETs have a base threshold and tailored FETs have a threshold above. In a multi-supply chip, circuits with tailored FETs are powered by an increased supply voltage.

Abstract: A composite object group (COG) data structure embodied in a computer-readable medium for building a control system that has both a clock cycle and event processing is provided. An interface for passing information to and from the COG data structure is provided. One or more data flow objects are provided in the COG to accept input data and to produce output data on the clock cycle. The data flow object is connected to the interface and provides sampled-data processing for the control system. One or more state machine objects are provided in the COG; each includes a plurality of states and a plurality of transitions between the states that are each triggered by an event. The state machine object provides event-driven processing for the control system, whereby the COG data structure provides both sampled-data and event-driven processing for the control system.

Abstract: Loadless 4T SRAM cells, and methods for operating such SRAM cells, which can provide highly integrated semiconductor memory devices while providing increased performance with respect to data stability and increased I/O speed for data access operations. A loadless 4T SRAM cell comprises a pair of access transistors and a pair of pull-down transistors, all of which are implemented as N-channel transistors (NFETs or NMOSFETS). The access transistors have lower threshold voltages than the pull-down transistors, which enables the SRAM cell to effectively maintain a logic “1” potential during standby. The pull-down transistors have larger channel widths as compared to the access transistors, which enables the SRAM cell to effectively maintain a logic “0” potential at a given storage node during a read operation.

Abstract: A multi-threshold integrated circuit (IC) with reduced subthreshold leakage and method of reducing leakage. Selectable supply switching devices (NFETs and/or PFETS) between a logic circuit and supply connections (Vdd and Ground) for the circuit have higher thresholds than normal circuit devices. Some devices may have thresholds lowered when the supply switching devices are on. Header/footer devices with further higher threshold voltages and widths may be used to further increase off resistance and maintain/reduce on resistance. Alternatively, high threshold devices may be stacked to further reduce leakage to a point achieved for an even higher threshold. Intermediate supply connects at the devices may have decoupling capacitance and devices may be tapered for optimum stack height and an optimum taper ratio to minimize circuit leakage and circuit delay.

Abstract: A metal-insulator-metal (MIM) capacitor including a metal layer, an insulating layer formed on the metal layer, at least a first opening and at least a second opening formed in the first insultaing layer, a dielectric layer formed in the first opening, a conductive material deposited in the first and second openings, and a first metal plate formed over the first opening and a second metal plate formed over the second opening. A method for fabricating the MIM capacitor, includes forming the first metal layer, forming the insulating layer on the first metal layer, forming at least the first opening and at least the second opening in the first insultaing layer, depositing a mask over the second opening, forming the dielectric layer in the first opening, removing the mask, depositing the conductive material in the first and second openings, and depositing a second metal layer over the first and second openings.

Abstract: A channel 16 of a FinFET 10 has a channel core 24 and a channel envelope 32, each made from a semiconductor material defining a different lattice structure to exploit strained silicon properties. A gate is coupled to the channel envelope through a gate dielectric. Exemplary materials are Si and SixGe1-x, wherein 78<x<92. The channel core 24 has a top surface 26 of width wc and an upstanding surface 28, 30 of height hc, preferably oriented 90° to one another. The channel envelope 32 is in contact with the top 26 and upstanding surfaces 28, 30 so that the area of interface is increased as compared to contact only along the top surface 26, improving electrical conductivity and gate 18 control over the channel 16. The height hc can be tailored to enable a smaller scale FET 10 within a stabilized SRAM. Various methods of making the channel 16 are disclosed, including a mask and etch method, a handle wafer/carrier wafer method, and a shallow trench method.

Abstract: A sense amplifier for a memory device comprising: a first sensing stage comprising a first sensing device and a second sensing device operably connected to a first sense line and a second sense line respectively, to reduce the capacitive load on the first sense line and second sense line. A source terminal of the sensing device is connected to a switchable current sink with drain terminal thereof connected to an input of a second sensing stage. The sense amplifier also includes a second sensing stage comprising cross-coupled inverters responsive to the first sensing stage, the second sensing stage is activated by a sense enable signal following a selected delay, and an output driver responsive to the second sensing stage.