Patents by Inventor Rajive Joshi

Rajive Joshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9950033
    Abstract: The invention relates to the use of an Engrailed protein as a medicament for increasing dopamine synthesis by dopaminergic neurons, in particular in the management of conditions associated with a decrease of dopamine levels without loss of dopaminergic neurons.
    Type: Grant
    Filed: February 29, 2012
    Date of Patent: April 24, 2018
    Assignees: Centre National de la Recherche Scientifique, College de France
    Inventors: Alain Prochiantz, Kenneth Moya, Rajiv Joshi
  • Publication number: 20170335320
    Abstract: The invention relates to the use of a reverse-transcriptase inhibitor in the prevention or treatment of a degenerative disease.
    Type: Application
    Filed: October 30, 2015
    Publication date: November 23, 2017
    Inventors: Alain Prochiantz, Julia Fuchs, Rajiv Joshi, François Xavier Blaudin De The, Hocine Rekaik, Olivia Massiani-Beaudoin
  • Publication number: 20160277338
    Abstract: Publisher-side content based filtering methods and systems are provided to select which subscribers shall receive each data-message sent by a publisher using an Object Management Group (OMG) Real-Time Publish-Subscribe (RTPS) protocol. Methods and systems are provided for writer-side content based filtering and data distribution from a publisher to a plurality of subscribers using an Object Management Group (OMG) Real-Time Publish-Subscribe (RTPS) protocol. Methods and systems are provided for performing scalable content-based filtering and distribution from a publisher to a plurality of subscribers using to the Object Management Group (OMG) Real-Time Publish-Subscribe (RTPS) protocol.
    Type: Application
    Filed: May 27, 2016
    Publication date: September 22, 2016
    Inventors: Fernando Crespo Sanchez, Jan Van Bruaene, Tron Sjur Kindseth, Gerardo Pardo-Castellote, Roshan Krishnan, Rajive Joshi
  • Patent number: 9386081
    Abstract: Publisher-side content based filtering methods and systems are provided to select which subscribers shall receive each data-message sent by a publisher using an Object Management Group (OMG) Real-Time Publish-Subscribe (RTPS) protocol. Methods and systems are provided for writer-side content based filtering and data distribution from a publisher to a plurality of subscribers using an Object Management Group (OMG) Real-Time Publish-Subscribe (RTPS) protocol. Methods and systems are provided for performing scalable content-based filtering and distribution from a publisher to a plurality of subscribers using the Object Management Group (OMG) Real-Time Publish-Subscribe (RTPS) protocol.
    Type: Grant
    Filed: August 29, 2014
    Date of Patent: July 5, 2016
    Assignee: Real-Time Innovations, Inc.
    Inventors: Fernando Crespo Sanchez, Jan Van Bruaene, Tron Sjur Kindseth, Gerardo Pardo-Castellote, Roshan Krishnan, Rajive Joshi
  • Publication number: 20150067059
    Abstract: Publisher-side content based filtering methods and systems are provided to select which subscribers shall receive each data-message sent by a publisher using an Object Management Group (OMG) Real-Time Publish-Subscribe (RTPS) protocol. Methods and systems are provided for writer-side content based filtering and data distribution from a publisher to a plurality of subscribers using an Object Management Group (OMG) Real-Time Publish-Subscribe (RTPS) protocol. Methods and systems are provided for performing scalable content-based filtering and distribution from a publisher to a plurality of subscribers using the Object Management Group (OMG) Real-Time Publish-Subscribe (RTPS) protocol.
    Type: Application
    Filed: August 29, 2014
    Publication date: March 5, 2015
    Inventors: Fernando Crespo Sanchez, Jan Van Bruaene, Tron Sjur Kindseth, Gerardo Pardo-Castellote, Roshan Krishnan, Rajive Joshi
  • Publication number: 20150057231
    Abstract: The invention relates to the use of an Engrailed protein as a medicament for increasing dopamine synthesis by dopaminergic neurons, in particular in the management of conditions associated with a decrease of dopamine levels without loss of dopaminergic neurons
    Type: Application
    Filed: February 29, 2012
    Publication date: February 26, 2015
    Applicants: COLLEGE DE FRANCE, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
    Inventors: Alain Prochiantz, Kenneth Moya, Rajiv Joshi
  • Patent number: 8671135
    Abstract: A method of providing transports for a data distribution middleware over a plurality of transport networks is provided. A data distribution middleware with a pluggable transport layer is provided. A plurality of transport plugins in the transport layer are provided. Aliases are assigned to each of the transport plugins of the plurality of transport plugins, wherein at least one of the transport plugins of the plurality of transport plugins has a plurality of aliases.
    Type: Grant
    Filed: April 24, 2006
    Date of Patent: March 11, 2014
    Assignee: Real-Time Innovations, Inc.
    Inventors: Rajive Joshi, Henry Choi, Gerardo Pardo-Castellote, Stefaan Sonck Thiebaut
  • Patent number: 8327374
    Abstract: Techniques for execution of multiple threads in a multithreaded computing programming environment are disclosed. The techniques are especially well suited for environments that use multilayered programming architecture where a higher layer can build on the functions provided by a lower layer where the delay time is an important consideration. In one aspect, the conceptual notion of a “Worker” effectively serves to represent the thread-specific execution context for a thread of execution (“thread”) in a multithreaded computing environment. Another aspect, provides the notion of an Exclusion Area (EA) as logical lock that serves to protect shared resources in a multithreaded environment. The combination of the worker and EA are used to provide a powerful framework that, among other things, allows minimizing of the delay time.
    Type: Grant
    Filed: August 25, 2010
    Date of Patent: December 4, 2012
    Assignee: Real-Time Innovations, Inc.
    Inventors: Stephen Jisoo Rhee, Elaine Yee Ting Sin, Gerardo Pardo-Castellote, Stefaan Sonck Thiebaut, Rajive Joshi
  • Patent number: 8255359
    Abstract: Aspects of the advancement provide for information to be synchronized in an asynchronous manner among two or more computing devices.
    Type: Grant
    Filed: December 23, 2009
    Date of Patent: August 28, 2012
    Assignee: Visto Corporation
    Inventors: Sean M. Quinlan, Daniel J. Mendez, Rajiv Joshi, Yuri Ardulov
  • Patent number: 8069144
    Abstract: Aspects of the invention provide for information to be synchronized in an asynchronous manner among two or more computing devices.
    Type: Grant
    Filed: June 9, 2010
    Date of Patent: November 29, 2011
    Assignee: Visto Corporation
    Inventors: Sean Quinlan, Daniel J. Mendez, Rajiv Joshi, Yuri Ardulov
  • Patent number: 7827559
    Abstract: Techniques for execution of multiple threads in a multithreaded computing programming environment are disclosed. The techniques are especially well suited for environments that use multilayered programming architecture where a higher layer can build on the functions provided by a lower layer where the delay time is an important consideration. In one aspect, the conceptual notion of a “Worker” effectively serves to represent the thread-specific execution context for a thread of execution (“thread”) in a multithreaded computing environment. Another aspect, provides the notion of an Exclusion Area (EA) as logical lock that serves to protect shared resources in a multithreaded environment. The combination of the worker and EA are used to provide a powerful framework that, among other things, allows minimizing of the delay time.
    Type: Grant
    Filed: April 24, 2006
    Date of Patent: November 2, 2010
    Assignee: Real-Time Innovations, Inc.
    Inventors: Stephen Jisoo Rhee, Elaine Yee Ting Sin, Gerardo Pardo-Castellote, Stefaan Sonck Thiebaut, Rajive Joshi
  • Publication number: 20100268844
    Abstract: Aspects of the invention provide for information to be synchronized in an asynchronous manner among two or more computing devices.
    Type: Application
    Filed: June 9, 2010
    Publication date: October 21, 2010
    Applicant: VISTO CORPORATION
    Inventors: Sean QUINLAN, Daniel J. Mendez, Rajiv Joshi, Yuri Ardulov
  • Patent number: 7783853
    Abstract: A method of operating real-time middleware associated with at least one node of a data distribution system is provided. At least one pool of a plurality of fixed block size units of memory of the node is allocated (e.g., via an operating system call). Based on loan requests for dynamic memory elements on behalf of a user application executing on the node, an indication of at least one of the allocated fixed block size units to be lent is provided. A list of which allocated fixed block size units are being lent from the pool is maintained, including maintaining the list based on return requests, on behalf of the user application executing on the node, of fixed block size units of the pool. Substantially all of the dynamic memory elements of the real-time middleware associated with the node are provided from the at least one pool of allocated fixed block size units based on the loan requests on behalf of the user application.
    Type: Grant
    Filed: April 24, 2006
    Date of Patent: August 24, 2010
    Assignee: Real-Time Innovations, Inc.
    Inventors: Stephen Jisoo Rhee, Yi Dai, Gerardo Pardo-Castellote, Rajive Joshi
  • Patent number: 7752166
    Abstract: Aspects of the invention provide for information to be synchronized in an asynchronous manner among two or more computing devices.
    Type: Grant
    Filed: November 15, 2002
    Date of Patent: July 6, 2010
    Assignee: Visto Corporation
    Inventors: Sean Quinlan, Daniel J. Mendez, Rajiv Joshi, Yuri Ardulov
  • Publication number: 20100100641
    Abstract: Aspects of the advancement provide for information to be synchronized in an asynchronous manner among two or more computing devices.
    Type: Application
    Filed: December 23, 2009
    Publication date: April 22, 2010
    Applicant: VISTO CORPORATION
    Inventors: Sean M. QUINLAN, Daniel J. Mendez, Rajiv Joshi, Yuri Ardulov
  • Patent number: 7533128
    Abstract: A bridge to integrate representation of global data space in Data Distribution Service (DDS) and Data Management Systems (DBMS). The DDS concept of a keyed topic and a type is mapped to the DBMS notion of a keyed table and schema representing data-object instances. Rules are specified for translating between a DBMS table record and the DDS wire format representation. Four bridge components are possible: Bridge-DDS-DBMS-Publication to store outgoing published data; Bridge-DDSDBMS-Subscription to store incoming subscribed data; Bridge-DBMS-DDS-Publication to publish changes to a DBMS table; and Bridge-DBMS-DDS-Subscription to update a DBMS Table based on received data subscriptions from the network. Mechanisms are provided for preventing publication of data seen by DDS, and for preventing application of changes already made in a DBMS table.
    Type: Grant
    Filed: October 18, 2005
    Date of Patent: May 12, 2009
    Assignee: Real-Time Innovations, Inc.
    Inventors: Fernando Crespo Sanchez, Rajive Joshi, Gerardo Pardo-Castellote
  • Publication number: 20080105898
    Abstract: A channel 16 of a FinFET 10 has a channel core 24 and a channel envelope 32, each made from a semiconductor material defining a different lattice structure to exploit strained silicon properties. A gate is coupled to the channel envelope through a gate dielectric. Exemplary materials are Si and SiXGe1?x, wherein 78<x<92. The channel core 24 has a top surface 26 of width wc and an upstanding surface 28, 30 of height hc, preferably oriented 90° to one another. The channel envelope 32 is in contact with the top 26 and upstanding surfaces 28, 30 so that the area of interface is increased as compared to contact only along the top surface 26, improving electrical conductivity and gate 18 control over the channel 16. The height hc, can be tailored to enable a smaller scale FET 10 within a stabilized SRAM. Various methods of making the channel 16 are disclosed, including a mask and etch method, a handle wafer/carrier wafer method, and a shallow trench method.
    Type: Application
    Filed: January 7, 2008
    Publication date: May 8, 2008
    Inventors: Rajiv Joshi, Richard Williams
  • Publication number: 20080105969
    Abstract: A method of fabricating a semiconductor device includes etching a substrate formed on a backside of a semiconductor wafer to form a recess in the substrate, and forming a sputter film in the recess, the sputter film including a first material having a coefficient of thermal expansion (CTE) which is at least substantially equal to a CTE of the substrate, and a second material having a thermal conductivity which is greater than a thermal conductivity of the substrate.
    Type: Application
    Filed: December 27, 2007
    Publication date: May 8, 2008
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Louis Hsu, Rajiv Joshi, Jack Mandelman
  • Publication number: 20080105900
    Abstract: A channel 16 of a FinFET 10 has a channel core 24 and a channel envelope 32, each made from a semiconductor material defining a different lattice structure to exploit strained silicon properties. A gate is coupled to the channel envelope through a gate dielectric. Exemplary materials are Si and SixGe1-x, wherein 78<x<92. The channel core 24 has a top surface 26 of width wc and an upstanding surface 28, 30 of height hc, preferably oriented 90° to one another. The channel envelope 32 is in contact with the top 26 and upstanding surfaces 28, 30 so that the area of interface is increased as compared to contact only along the top surface 26, improving electrical conductivity and gate 18 control over the channel 16. The height hc can be tailored to enable a smaller scale FET 10 within a stabilized SRAM. Various methods of making the channel 16 are disclosed, including a mask and etch method, a handle wafer/carrier wafer method, and a shallow trench method.
    Type: Application
    Filed: January 7, 2008
    Publication date: May 8, 2008
    Inventors: Rajiv Joshi, Richard Williams
  • Publication number: 20080094878
    Abstract: A ring oscillator row circuit for evaluating memory cell performance provides for circuit delay and performance measurements in an actual memory circuit environment. A ring oscillator is implemented with a row of memory cells and has outputs connected to one or more bitlines along with other memory cells that are substantially identical to the ring oscillator cells. Logic may be included for providing a fully functional memory array, so that the cells other than the ring oscillator cells can be used for storage when the ring oscillator row wordlines are disabled. One or both power supply rails of individual cross-coupled inverter stages forming static memory cells used in the ring oscillator circuit may be isolated from each other in order to introduce a voltage asymmetry so that circuit asymmetry effects on delay can be evaluated.
    Type: Application
    Filed: December 22, 2007
    Publication date: April 24, 2008
    Inventors: Rajiv Joshi, Qiuyi Ye, Yuen Chan, Anirudh Devgan