Patents by Inventor Rajive Joshi

Rajive Joshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210194427
    Abstract: A remotely powered low power oscillator. According to an embodiment of the present invention, a method comprises an oscillator core, in a first environment, generating an oscillating signal; a power management system, in a second environment, supplying power to the oscillator core to operate the oscillator core; a sensing system, in the first environment, sensing one or more parameters of the oscillator core, and generating one or more signals representing said one or more parameters; transmitting the one or more signals from the sensing system to the second environment; and using the one or more signals in the second environment to control the power supplied to the oscillator core from the power management system.
    Type: Application
    Filed: December 24, 2019
    Publication date: June 24, 2021
    Inventors: Sudipto Chakraborty, Rajiv Joshi, Steven J. Holmes, Bruce B. Doris
  • Patent number: 11037650
    Abstract: A first voltage may be applied to a memory in a neural network. The memory may include one or more memory cells. A processor may determine that a first memory cell in the memory is faulty at the first voltage. The first voltage may be a low voltage. The processor may identify a first factor in the neural network. The first factor may have a low criticality in the neural network. The processor may determine to store the first factor in the first memory cell. The processor may store the first factor in the first memory cell.
    Type: Grant
    Filed: January 28, 2020
    Date of Patent: June 15, 2021
    Assignee: International Business Machines Corporation
    Inventors: Alper Buyuktosunoglu, Swagath Venkataramani, Rajiv Joshi, Karthik V. Swaminathan, Schuyler Eldridge, Pradip Bose
  • Publication number: 20210175407
    Abstract: A within-chip magnetic field control device is formed in proximity to a Josephson Junction (JJ) structure. The within-chip magnetic field control device includes wiring structures that are located laterally adjacent to the JJ structure. In some embodiments, the magnetic field control device also includes, in addition to the wiring structures, a conductive plate that is connected to the wiring structures and is located beneath the JJ structure. Use of electrical current through the wiring structures induces, either directly or indirectly, a magnetic field into the JJ structure. The strength of the field can be modulated by the amount of current passing through the wiring structures. The magnetic field can be turned off as needed by ceasing to allow current to flow through the wiring structures.
    Type: Application
    Filed: December 6, 2019
    Publication date: June 10, 2021
    Inventors: Steven J. Holmes, Bruce B. Doris, Matthias Georg Gottwald, Rajiv Joshi, Sudipto Chakraborty
  • Publication number: 20210174858
    Abstract: A structure of a memory device is described. The structure can include an array of memory cells. A memory cell can include at least one metal-oxide-semiconductor (MOS) element, where a source terminal of the at least one MOS element is connected to a drain terminal of the MOS element. The source terminal being connected to the drain terminal can cause the at least one MOS element to exhibit capacitive behavior for storing electrical energy. A first transistor can be connected to the at least one MOS element, where an activation of the first transistor can facilitate a write operation to the memory cell. A second transistor can be connected to the at least one MOS element, where an activation of the second transistor can facilitate a read operation from the memory cell.
    Type: Application
    Filed: December 9, 2019
    Publication date: June 10, 2021
    Inventors: Rajiv Joshi, Sudipto Chakraborty
  • Patent number: 11024354
    Abstract: Circuits and methods are disclosed that, in embodiments, may be used for low power memory signal readout. In an embodiment, the circuit comprises a front end stage including an impedance conversion network for receiving a signal and providing voltage or current gain, and a wideband multiplier for receiving an output signal from the impedance conversion network and converting the output signal to differential output signals; and a baseband stage including a voltage mode mixer for receiving the differential output signals from the wideband multiplier and providing voltage gain, and a bandpass filter/amplifier for receiving a mixer output signal from the voltage mode mixer and filtering and amplifying the mixer output signal; and wherein DC voltages of the front-end stage are biased independently of a biasing of DC voltages of the baseband stage.
    Type: Grant
    Filed: December 27, 2019
    Date of Patent: June 1, 2021
    Assignee: International Business Machines Corporation
    Inventors: Sudipto Chakraborty, Rajiv Joshi, Steven J. Holmes, Bruce B. Doris
  • Patent number: 11025234
    Abstract: Methods and systems for regulating supply voltage is described. In an example, a device can receive unregulated supply. The device can be connected to a ring oscillator and an integrated circuit. The device can be configured to regulate the unregulated supply to a first voltage. The device can be further configured to provide the regulated supply to the ring oscillator, where the ring oscillator operates with the regulated supply. The device can be further configured to, in response to a change in the regulated supply from the first voltage to a second voltage, adjust the changed regulated supply to return to the first voltage to cause the ring oscillator to operate with a constant regulated supply having the first voltage.
    Type: Grant
    Filed: February 24, 2020
    Date of Patent: June 1, 2021
    Assignee: International Business Machines Corporation
    Inventors: Sudipto Chakraborty, Rajiv Joshi, Steven J. Holmes, Bruce B. Doris
  • Publication number: 20210151848
    Abstract: A high input impedance magnetic balun/transformer having a phase balancing network (PBN) and method of operating. The balun is fully configurable and trimmable post fabrication using independently adjustable resistive and reactive parts by changing the resistance of a programmed transistor, e.g., NMOS. Parallel connected legs each having a field effect transistors (FETs) that make up NMOS device alter the impedance at the balun output terminals. The ground terminal of a secondary winding or coil at an unbalanced, single-ended side is connected to a phase balancing network. The phase balancing network includes at least two parallel legs, each leg having a resistive element in the form of a transistor device and at least one leg including a capacitive element. The transistor device at a leg can be operated in a linear region to trim the resistance and capacitances at the unbalanced side in order to achieve proper phase balancing and amplitude matching.
    Type: Application
    Filed: December 28, 2020
    Publication date: May 20, 2021
    Inventors: Sudipto Chakraborty, Rajiv Joshi, Steven J. Holmes, Bruce B. Doris
  • Publication number: 20210050829
    Abstract: An analog front-end (AFE) circuit for conditioning a sensor signal is disclosed. The AFE circuit includes a first stage configured to amplify and filter the sensor signal. The first stage comprises a biquadratic filter comprising a first plurality of DC-coupled transconductance amplifiers. The AFE further includes a second stage configured to further amplify and filter the amplified sensor signal, and to compensate a direct current (DC) offset of the first stage. The second stage comprises a second plurality of AC-coupled transconductance amplifiers. Each transconductance amplifier of the first plurality and of the second plurality has a programmable transconductance and comprises a plurality of subthreshold-biased transistors.
    Type: Application
    Filed: August 14, 2019
    Publication date: February 18, 2021
    Inventors: Sudipto Chakraborty, Rajiv Joshi
  • Patent number: 10903544
    Abstract: A high input impedance magnetic balun/transformer having a phase balancing network (PBN) and method of operating. The balun is fully configurable and trimmable post fabrication using independently adjustable resistive and reactive parts by changing the resistance of a programmed transistor, e.g., NMOS. Parallel connected legs each having a field effect transistors (FETs) that make up NMOS device alter the impedance at the balun output terminals. The ground terminal of a secondary winding or coil at an unbalanced, single-ended side is connected to a phase balancing network. The phase balancing network includes at least two parallel legs, each leg having a resistive element in the form of a transistor device and at least one leg including a capacitive element. The transistor device at a leg can be operated in a linear region to trim the resistance and capacitances at the unbalanced side in order to achieve proper phase balancing and amplitude matching.
    Type: Grant
    Filed: April 25, 2019
    Date of Patent: January 26, 2021
    Assignee: International Business Machines Corporation
    Inventors: Sudipto Chakraborty, Rajiv Joshi, Steven J. Holmes, Bruce B. Doris
  • Patent number: 10879923
    Abstract: Methods and systems to implement a multiply and accumulate (MAC) unit is described. In an example, a device can include a current mode digital-to-analog converter (DAC) configured to multiply an input signal with an input current to generate a signal. The device can further include a current divider coupled to the current mode DAC. The current divider can be configured to divide the signal into at least a first current having a first amplitude and a second current having a second amplitude. The device can further include a mixer configured to multiply the second current with a clock signal to generate a third current. The third signal can be combined with the first signal via a current summing node to generate an output signal. The output signal can be outputted to another device.
    Type: Grant
    Filed: January 6, 2020
    Date of Patent: December 29, 2020
    Assignee: International Business Machines Corporation
    Inventors: Sudipto Chakraborty, Rajiv Joshi
  • Patent number: 10833685
    Abstract: A voltage controlled oscillator (VCO) circuit and method achieves linearized frequency tuning over an extended range of analog tuning voltage by implementing a magnetic balun/transformer for biasing and coupling varactor elements. An active negative transconductance circuit of cross-coupled transistors have drains connected with a resonant tank circuit and at least a first varactor element having ends connected to respective first ends of respective first coils of a respective first and second magnetic balun. Respective second ends of respective first coils of respective first and second baluns are connected to a first reference supply voltage. A second varactor element has ends connecting respective first ends of respective second coils of said first and second baluns. A sinking of a bias current through the resonant tank circuit and the transconductance circuit generates an oscillating signal. A calibration method achieves precise VCO gain over wide tuning voltage range, thereby enhancing VCO linearity.
    Type: Grant
    Filed: June 19, 2019
    Date of Patent: November 10, 2020
    Assignee: International Business Machines Corporation
    Inventors: Sudipto Chakraborty, Rajiv Joshi, Steven J. Holmes, Bruce B. Doris
  • Publication number: 20200343614
    Abstract: A high input impedance magnetic balun/transformer having a phase balancing network (PBN) and method of operating. The balun is fully configurable and trimmable post fabrication using independently adjustable resistive and reactive parts by changing the resistance of a programmed transistor, e.g., NMOS. Parallel connected legs each having a field effect transistors (FETs) that make up NMOS device alter the impedance at the balun output terminals. The ground terminal of a secondary winding or coil at an unbalanced, single-ended side is connected to a phase balancing network. The phase balancing network includes at least two parallel legs, each leg having a resistive element in the form of a transistor device and at least one leg including a capacitive element. The transistor device at a leg can be operated in a linear region to trim the resistance and capacitances at the unbalanced side in order to achieve proper phase balancing and amplitude matching.
    Type: Application
    Filed: April 25, 2019
    Publication date: October 29, 2020
    Inventors: Sudipto Chakraborty, Rajiv Joshi, Steven J. Holmes, Bruce B. Doris
  • Publication number: 20200168290
    Abstract: A first voltage may be applied to a memory in a neural network. The memory may include one or more memory cells. A processor may determine that a first memory cell in the memory is faulty at the first voltage. The first voltage may be a low voltage. The processor may identify a first factor in the neural network. The first factor may have a low criticality in the neural network. The processor may determine to store the first factor in the first memory cell. The processor may store the first factor in the first memory cell.
    Type: Application
    Filed: January 28, 2020
    Publication date: May 28, 2020
    Inventors: Alper Buyuktosunoglu, Swagath Venkataramani, Rajiv Joshi, Karthik V. Swaminathan, Schuyler Eldridge, Pradip Bose
  • Patent number: 10607715
    Abstract: A first voltage may be applied to a memory in a neural network. The memory may include one or more memory cells. A processor may determine that a first memory cell in the memory is faulty at the first voltage. The first voltage may be a low voltage. The processor may identify a first factor in the neural network. The first factor may have a low criticality in the neural network. The processor may determine to store the first factor in the first memory cell. The processor may store the first factor in the first memory cell.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: March 31, 2020
    Assignee: International Business Machines Corporation
    Inventors: Alper Buyuktosunoglu, Swagath Venkataramani, Rajiv Joshi, Karthik V. Swaminathan, Schuyler Eldridge, Pradip Bose
  • Patent number: 10342851
    Abstract: The invention relates to the use of an Engrailed protein as a medicament for increasing dopamine synthesis by dopaminergic neurons, in particular in the management of conditions associated with a decrease of dopamine levels without loss of dopaminergic neurons.
    Type: Grant
    Filed: March 16, 2018
    Date of Patent: July 9, 2019
    Assignees: Centre National de la Recherche Scientifique, College de France
    Inventors: Alain Prochiantz, Kenneth Moya, Rajiv Joshi
  • Publication number: 20190205793
    Abstract: Method and apparatus for generating profiles using machine learning and influencing online interactions are provided. The methods include generating a user profile specifying a plurality of attribute values for a plurality of principle attributes, by processing a corpus of electronic documents using a first trained machine learning model. In an embodiment, the method further comprises generating a provider profile specifying a plurality of attribute values for the plurality of principle attributes, for each of a plurality of providers, by processing a respective corpus of electronic documents associated with each respective provider using a second trained machine learning model. A plurality of match coefficients based on comparing the user profile and the plurality of provider profiles are determined. Finally, one or more online interactions between the user and the target provider are influenced based on the determined match coefficients.
    Type: Application
    Filed: December 28, 2017
    Publication date: July 4, 2019
    Inventors: Swaminathan BALASUBRAMANIAN, Avijit CHATTERJEE, Rajiv JOSHI, John J. THOMAS
  • Publication number: 20190205950
    Abstract: Method and apparatus for generating profiles using machine learning and influencing online interactions are provided. The methods include receiving, from a first user of a plurality of users, a first set of electronic documents, where each electronic document in the first set of electronic documents corresponds to a respective user in the plurality of users. The methods also include identifying a plurality of user profiles, where each of the plurality of user profiles was generated by processing a corpus of electronic documents associated with each respective user using a first trained machine learning model. The methods include determining a plurality of match coefficients, based on comparing a plurality of user profiles associated with each respective user in the plurality of users, filtering the first set of electronic documents based on the plurality of match coefficients, and providing the filtered first set of electronic documents to the first user.
    Type: Application
    Filed: December 28, 2017
    Publication date: July 4, 2019
    Inventors: Swaminathan BALASUBRAMANIAN, Avijit CHATTERJEE, Rajiv JOSHI, John J. THOMAS
  • Publication number: 20180358110
    Abstract: A first voltage may be applied to a memory in a neural network. The memory may include one or more memory cells. A processor may determine that a first memory cell in the memory is faulty at the first voltage. The first voltage may be a low voltage. The processor may identify a first factor in the neural network. The first factor may have a low criticality in the neural network. The processor may determine to store the first factor in the first memory cell. The processor may store the first factor in the first memory cell.
    Type: Application
    Filed: June 13, 2017
    Publication date: December 13, 2018
    Inventors: Alper Buyuktosunoglu, Swagath Venkataramani, Rajiv Joshi, Karthik V. Swaminathan, Schuyler Eldridge, Pradip Bose
  • Patent number: 10100307
    Abstract: The invention relates to the use of a reverse-transcriptase inhibitor in the prevention or treatment of a degenerative disease.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: October 16, 2018
    Assignees: Centre National de la Recherche Scientifique, Institut National de la Sante et de la Recherche Medicale (INSERM), College de France, Sorbonne Universite
    Inventors: Alain Prochiantz, Julia Fuchs, Rajiv Joshi, François Xavier Blaudin De The, Hocine Rekaik, Olivia Massiani-Beaudoin
  • Publication number: 20180271937
    Abstract: The invention relates to the use of an Engrailed protein as a medicament for increasing dopamine synthesis by dopaminergic neurons, in particular in the management of conditions associated with a decrease of dopamine levels without loss of dopaminergic neurons.
    Type: Application
    Filed: March 16, 2018
    Publication date: September 27, 2018
    Applicants: Centre National de la Recherche Scientifique, College de France
    Inventors: Alain Prochiantz, Kenneth Moya, Rajiv Joshi