Abstract: A method of Back-End-Of-Line processing of a semiconductor device is provided including providing a layout for metal lines of a metallization layer of the semiconductor device, determining a semi-isolated metal line in the provided layout and shifting at least a portion of the determined semi-isolated metal line.

Abstract: A system and method for generating a mixed-reality environment is provided. The system and method provides a user-worn sub-system communicatively connected to a synthetic object computer module. The user-worn sub-system may utilize a plurality of user-worn sensors to capture and process data regarding a user's pose and location. The synthetic object computer module may generate and provide to the user-worn sub-system synthetic objects based information defining a user's real world life scene or environment indicating a user's pose and location. The synthetic objects may then be rendered on a user-worn display, thereby inserting the synthetic objects into a user's field of view. Rendering the synthetic objects on the user-worn display creates the virtual effect for the user that the synthetic objects are present in the real world.

Abstract: In one embodiment, an aerospace system is provided. The aerospace system comprises at least one display unit configured to display flight data and a memory configured to store one or more flight plan associations. Each flight plan association is an association between a data link message and a respective waypoint in a flight plan. The aerospace system also comprises a processing unit configured to determine when each respective waypoint in the flight plan is reached based on a comparison of current location data to the flight plan. When each respective waypoint is reached, the processing unit is configured to identify any data link messages associated with the respective waypoint based on the flight plan associations and to direct the at least one display unit to display a respective notification for each identified data link message associated with the respective waypoint.

Abstract: A negative bit line boost circuit for a memory is configured to control a write multiplexer and a write assist transistor so that charge from a boost capacitor positively charges a bit line following a write assist period.

Abstract: Maskable level shifter circuits and memories are provided. Memories may include a plurality of memory cells and a bitline coupled to the plurality of memory cells. The memories includes a maskable level shifter configured to receive write data and a mask signal. A maskable level shifter includes a level shifter configured to level shift the write data and output the level shifted write data to the bitline when the mask signal is inactive and a masking circuit configured to remove power from the level shifter when the mask signal is active. Another maskable level shifter includes a level shifter configured to level shift the write data and output the level shifted write data to the bitline when the mask signal is inactive and a masking circuit configured to output a predetermined state to the bitline when the mask signal is active.

Abstract: Biofeedback virtual reality sleep assistant technologies monitor one or more physiological parameters while presenting an immersive environment. The presentation of the immersive environment changes over time in response to changes in the values of the physiological parameters. The changes in the presentation of the immersive environment are configured using biofeedback technology and are designed to promote sleep.

Abstract: The present invention discloses a catalytic process for the manufacture of hydrogen and hydrocarbons simultaneously in the same reactor from renewable source, i.e. lipids, glycerides and fatty acids from plant, animal or algae oil, where in the multiple unstaurations in the renewable feedstock and the catalytic intermediates produced in the process from renewable feedstock is converted catalytically using simultaneous combination of in-situ occurring reactions. These in-situ occurring reactions are simultaneous combination of hydroconversion, reforming and water gas shift reactions wherein the reaction is performed in the presence of one or more metal sulfides form of metals of Group VI and/or Group IX and/or Group X elements, specifically comprises of one or more active metal combinations such as Co, W, Mo, Ni, P, with Pt, Pd encapsulated inside sodalite cages for prevention against poisoning from sulfur based compounds.

Abstract: The present disclosure provides methods for inducing an immune response to hepatitis C virus (HCV) in an individual. The present disclosure provides methods for treating an HCV infection in an individual.

Abstract: Micro-Electro-Mechanical System (MEMS) devices for harvesting sound energy and methods for fabricating MEMS devices for harvesting sound energy are provided. In an embodiment, a method for fabricating a MEMS device for harvesting sound energy includes forming a pressure sensitive MEMS structure disposed over a semiconductor substrate and including a suspended structure in a cavity. Further, the method includes etching the semiconductor substrate to form an acoustic port through the semiconductor substrate configured to allow acoustic pressure to deflect the suspended structure.

Abstract: A memory circuit includes a set of subarrays of memory cells and a set of write assist circuits for generating negative voltages on bitlines pertaining to the set of subarrays, respectively. A set of distinct signals initiate the write assist circuits in generating the negative voltages for subarrays, respectively. The distinct signals may have particular state to cause a subset of the write assist circuits to generate the negative voltages if the corresponding subarrays are target of a writing operation, and another state to cause another subset of the write assist circuits to not generate the negative voltages if the corresponding subarrays are not target of the writing operation. This avoids the unnecessary generation of negative voltages for subarrays that are not the target of a writing operation so as to reduce power consumption. The generation of the distinct signals may be based on a set of write mask signals.

Abstract: The present disclosure relates to a system, method, and kit for particle detection and analysis. Devices disclosed herein may include at least an optical source, a fludic chip containing a multiplex bead array, and a detection module, wherein the sample flows within the fludic chip past a detection window, where the cells or particles are imaged by an image acquisition and analysis module that may include an optical detector. The image acquisition and analysis module counts the labeled particles and software allows for analysis of bead population.

Abstract: A method, computer-readable storage device and apparatus for routing traffic in a reconfigurable optical add-drop multiplexer layer of a dense wavelength division multiplexing network are disclosed. For example, the method determines the reconfigurable optical add-drop multiplexer layer has asymmetric traffic, and routes the asymmetric traffic in the reconfigurable optical add-drop multiplexer layer over a plurality of asymmetrical optical connections, wherein the plurality of asymmetrical optical connections is provided with only uni-directional equipment in the reconfigurable optical add-drop multiplexer layer.

Abstract: The present invention is related to heteroaryl compounds as MEK inhibitors. The invention includes heteroaryl compounds of formula I, their tautomers and pharmaceutically acceptable salts, combinations with suitable medicament and pharmaceutical compositions thereof. The present invention also includes process of preparation of the said compounds and intended use in therapy of them.

Abstract: Provided in accordance with the herein described exemplary embodiments are piezo micro-machined ultrasonic transducers (pMUTs) each having a first electrode that includes a first electrode portion and a second electrode portion. The second electrode portion is separately operable from the first electrode portion. A second electrode is spaced apart from the first electrode and defines a space between the first electrode and the second electrode. A piezoelectric material is disposed in the space. Also provided are arrays of pMUTs wherein individual pMUTs have first electrode portions operably associated with array rows and second electrode portions operably associated with array columns.

Abstract: Capacitors that can be formed fully on an integrated circuit (IC) chip are described in this disclosure. An IC chip includes a metal-oxide-silicone (MOS) capacitor formed from a MOS transistor having a drain terminal, a source terminal, a gate terminal, and a body terminal. The drain terminal and the source terminal are not electrically connected to any other node, and the gate terminal and the body terminal form respective first and second terminals of the MOS capacitor. The IC chip also includes an electrical conductor coupled to one of the gate terminal or the body terminal of the MOS transistor and configured to deliver a voltage to operate the MOS capacitor in an accumulation mode.

Abstract: Integrated circuits having shielded micro-electromechanical system (MEMS) devices and method for fabricating shielded MEMS devices are provided. In an example, an integrated circuit having a shielded MEMS device includes a substrate, a ground plane including conductive material over the substrate, and a dielectric layer over the ground plane. The integrated circuit further includes a MEMS device over the ground plane. Also, the integrated circuit includes a conductive pillar through the dielectric layer and in contact with the ground plane. The integrated circuit includes a metallic thin film over the MEMS device and in contact with the conductive pillar, wherein the metallic thin film, the conductive pillar and the ground plane form an electromagnetic shielding structure surrounding the MEMS device. Further, the integrated circuit includes an acoustic shielding structure over the substrate and adjacent the electromagnetic shielding structure.

Abstract: A Microelectromechanical System (MEMS) device which includes a piezoelectric stack on a substrate separated by a dielectric layer is disclosed. The piezoelectric stack includes first and second piezoelectric layers with a first electrode below the first piezoelectric layer and a contact pad and a second electrode between the first and second piezoelectric layers. A first contact extends through the piezoelectric layers and contact pad to the first electrode and a second contact extends through the second piezoelectric layer to the second electrode. The contact pad prevents an interface to form between the first and second piezoelectric layers in the contact opening, thus preventing corrosion of the piezoelectric layers during contact formation process.

Abstract: Capacitors that can be formed fully on an integrated circuit (IC) chip are described in this disclosure. An IC chip includes a metal-oxide-silicone (MOS) capacitor formed from a MOS transistor having a drain terminal, a source terminal, a gate terminal, and a body terminal. The drain terminal and the source terminal are not electrically connected to any other node, and the gate terminal and the body terminal form respective first and second terminals of the MOS capacitor. The IC chip also includes an electrical conductor coupled to one of the gate terminal or the body terminal of the MOS transistor and configured to deliver a voltage to operate the MOS capacitor in an accumulation mode.

Abstract: In an aspect of the disclosure, a method and an apparatus are provided. The apparatus may be a memory. The memory may include a first memory portion configured to store a first bit and generate a first data bit output. The first data bit output may be a function of the first bit when a first read enable is active. The memory may also include a second memory portion configured to store a second bit and generate a second data bit output. The second data bit output may be a function of the second bit when a second read enable is active. The memory may include a switch configured to select between the first and second bits for a read operation based on the first and second data bit outputs.

Abstract: Methods of treating cancers comprising administering a fibroblast growth factor receptor 1 (FGFR1) extracellular domain (ECD) and/or an FGFR1 ECD fusion molecule are provided. Methods of treating cancers comprising administering a fibroblast growth factor receptor 1 (FGFR1) extracellular domain (ECD) and/or an FGFR1 ECD fusion molecule and at least one anti-angiogenic agent are provided.