Patents by Inventor Ralf Otremba

Ralf Otremba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Top side cooling for GaN power device
    Patent number: 9881862
    Abstract: A packaged semiconductor includes an electrically insulating encapsulant having opposite facing first and second planar sides. A thermally conductive substrate is partially embedded in the encapsulant such that an outer side of the substrate is exposed at the first side of the encapsulant and an inner side of the substrate is contained within the encapsulant. A GaN based power semiconductor device is completely embedded in the encapsulant and includes: a main side having electrically conductive device terminals, and a rear side that faces away from the main side and is mounted on the inner side the substrate. A plurality of electrically conductive leads is partially embedded in the encapsulant and electrically connected to the device terminals. Vertical portions of the leads extend away from the substrate towards the second side of the encapsulant.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: January 30, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Klaus Schiess
  • Semiconductor device and method for producing the same
    Patent number: 9875935
    Abstract: A method for producing a semiconductor device is provided. The method includes providing a semiconductor substrate, providing at least one semiconductor device on the substrate, having a back face opposite the semiconductor substrate and a front face towards the semiconductor substrate, providing a contact layer on the back face of the semiconductor device, bonding the contact layer to an auxiliary carrier, and separating the at least one semiconductor device from the substrate. Further, a semiconductor device produced according to the method and an intermediate product are provided.
    Type: Grant
    Filed: March 8, 2013
    Date of Patent: January 23, 2018
    Assignee: Infineon Technologies Austria AG
    Inventors: Anton Mauder, Ralf Otremba, Hans-Joachim Schulze
  • Semiconductor power package and method of manufacturing the same
    Patent number: 9837288
    Abstract: A semiconductor power package includes a pre-molded chip housing and an electrically conducting chip carrier cast-in-place in the pre-molded chip housing. The semiconductor power package further includes a power semiconductor chip bonded on the electrically conducting chip carrier. A covering material is provided to embed the power semiconductor chip. The covering material has an elastic modulus less than an elastic modulus of a material of the pre-molded chip housing and/or a thermal conductivity greater than a thermal conductivity of the material of the pre-molded chip housing and/or a temperature stability greater than a temperature stability of the pre-molded chip housing.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: December 5, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Thomas Basler, Edward Fuergut, Christian Kasztelan, Ralf Otremba
  • Chip carrier structure, chip package and method of manufacturing the same
    Patent number: 9824958
    Abstract: Various embodiments provide a chip carrier structure. The chip carrier structure may include a structured metallic chip carrier; encapsulating material at least partially filling the structure; wherein the main surfaces of the metallic chip carrier are free from the encapsulating material.
    Type: Grant
    Filed: March 5, 2013
    Date of Patent: November 21, 2017
    Assignee: INFINEON TECHNOLOGIES AUSTRIA AG
    Inventors: Ralf Otremba, Josef Hoeglauer, Juergen Schredl, Xaver Schloegel, Klaus Schiess
  • Semiconductor package with top side cooling heat sink thermal pathway
    Patent number: 9812373
    Abstract: An electronic module includes a semiconductor package including a semiconductor chip and an electrically insulating encapsulation body encapsulating the semiconductor chip, the encapsulation body completely covering a second main face and four side faces of the semiconductor chip, wherein a first main face of the semiconductor chip that is opposite the first main face is exposed from the encapsulation body, a heat spreader attached to the semiconductor package, the heat spreader completely covering the first main face of the semiconductor chip, and an electrically insulating layer disposed on the heat spreader remote from the semiconductor package. The electrically insulating layer is completely separated from the semiconductor chip.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: November 7, 2017
    Assignee: Infineon Technologies AG
    Inventors: Christian Fachmann, Ralf Otremba, Klaus Schiess, Franz Stueckler
  • Device Including a Semiconductor Chip Monolithically Integrated with a Driver Circuit in a Semiconductor Material
    Publication number: 20170317001
    Abstract: A device includes a driver circuit, a first semiconductor chip monolithically integrated with the driver circuit in a first semiconductor material, and a second semiconductor chip integrated in a second semiconductor material. The second semiconductor material is a compound semiconductor.
    Type: Application
    Filed: July 11, 2017
    Publication date: November 2, 2017
    Inventors: Ralf Otremba, Klaus Schiess, Oliver Haeberlen, Matteo-Alessandro Kutschak
  • Transistor arrangement with semiconductor chips between two substrates
    Patent number: 9806029
    Abstract: An electronic device comprising a first substrate, a second substrate, a first semiconductor chip comprising a transistor, comprising a first mounting surface bonded to the first substrate and comprising a second mounting surface bonded to the second substrate, and a second semiconductor chip comprising a first mounting surface bonded to the first substrate and comprising a second mounting surface bonded to the second substrate, wherein the first semiconductor chip comprises a via electrically coupling a first transistor terminal at its first mounting surface with a second transistor terminal at its second mounting surface.
    Type: Grant
    Filed: October 2, 2013
    Date of Patent: October 31, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Josef Hoeglauer, Chooi Mei Chong
  • Power semiconductor device including a cooling material
    Patent number: 9793255
    Abstract: A power semiconductor device includes a wiring structure adjoining at least one side of a semiconductor body and comprising at least one electrically conductive compound. The power semiconductor device further includes a cooling material in the wiring structure. The cooling material is characterized by a change in structure by means of absorption of energy at a temperature TC ranging between 150° C. and 400° C.
    Type: Grant
    Filed: January 13, 2015
    Date of Patent: October 17, 2017
    Assignee: Infineon Technologies AG
    Inventors: Joachim Mahler, Ralf Otremba, Hans-Joachim Schulze, Guenther Ruhl, Hans-Joerg Timme
  • Lateral element isolation device
    Patent number: 9786584
    Abstract: Representative implementations of devices and techniques provide isolation between a carrier and a component mounted to the carrier. A multi-layer device having lateral elements provides electrical isolation at a preset isolation voltage while maintaining a preselected thermal conductivity between the component and the carrier.
    Type: Grant
    Filed: September 4, 2012
    Date of Patent: October 10, 2017
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Josef Hoeglauer, Juergen Schredl, Xaver Schloegel, Klaus Schiess
  • Half Bridge Circuit, Method of Operating a Half Bridge Circuit and a Half Bridge Circuit Package
    Publication number: 20170288654
    Abstract: A half bridge circuit includes an input connection configured to supply an electric input, an output connection configured to supply an electric output to a load to be connected to the output connection, a switch and a diode arranged between the input connection and the output connection and a voltage limiting inductance arranged in series between the switch and the diode. The voltage limiting inductance is configured to limit, upon switching the switch, a maximum voltage across the switch to below a breakdown voltage of the switch. A corresponding method of operating the half bridge circuit and package are also described.
    Type: Application
    Filed: April 3, 2017
    Publication date: October 5, 2017
    Inventors: Ralf Otremba, Josef Hoeglauer, Gerhard Noebauer
  • Redirecting solder material to visually inspectable package surface
    Publication number: 20170278762
    Abstract: A package comprising an electronic chip, a laminate type encapsulant in and/or on which the electronic chip is mounted, a solderable electric contact on a solder surface of the package, and a solder flow path on and/or in the package which is configured so that, upon soldering the electric contact with a mounting base, part of solder material flows along the solder flow path towards a surface of the package at which the solder material is optically inspectable after completion of the solder connection between the mounting base and the electric contact.
    Type: Application
    Filed: March 23, 2017
    Publication date: September 28, 2017
    Inventors: Angela KESSLER, Oliver HAEBERLEN, Matteo-Alessandro KUTSCHAK, Ralf OTREMBA, Petteri PALM, Boris PLIKAT, Thorsten SCHARF, Klaus SCHIESS, Fabian SCHNOY, Erich SYRI
  • Compound semiconductor device including a multilevel carrier
    Patent number: 9754862
    Abstract: A device includes a carrier having a first carrier section on a first level and a second carrier section on a second level different from the first level. The device further includes a compound semiconductor chip arranged over the first carrier section and a control semiconductor chip arranged over the second carrier section. The control semiconductor chip is configured to control the compound semiconductor chip. An encapsulation material covers the compound semiconductor chip and the control semiconductor chip.
    Type: Grant
    Filed: March 30, 2016
    Date of Patent: September 5, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Klaus Schiess
  • Semiconductor device having sensing functionality
    Patent number: 9754854
    Abstract: A semiconductor package includes a power semiconductor chip having a control electrode, a first load electrode and a second load electrode. The package also includes a first terminal conductor electrically coupled to the control electrode, a second terminal conductor electrically coupled to the first load electrode and a third terminal conductor electrically coupled to the second load electrode. Further, the package includes a temperature sensor electrically coupled to at least two of the first, second and third terminal conductor.
    Type: Grant
    Filed: October 11, 2012
    Date of Patent: September 5, 2017
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Ralf Otremba, Marco Seibt
  • Electronic device and method of manufacturing the same
    Patent number: 9748116
    Abstract: Various embodiments provide an electronic device, wherein the electronic device comprises a mounting surface configured to mount the electronic device to an external structure and having a first size; a backside electrode having a second size and having arranged thereon a die electrically connected to the backside electrode; wherein the first size is at least three times the second size.
    Type: Grant
    Filed: July 1, 2016
    Date of Patent: August 29, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Ulrich Froehler, Felix Grawert, Ernst Katzmaier, Uwe Kirchner, Rene Mente, Andreas Schloegl, Uwe Wahl
  • Semiconductor devices including control and load leads of opposite directions
    Patent number: 9748166
    Abstract: A device includes a carrier and a semiconductor chip arranged over a surface of the carrier. The semiconductor chip includes a control electrode and a load electrode. A first lead is electrically coupled to the control electrode and extends away from the control electrode in a first direction. A second lead is electrically coupled to the load electrode and extends away from the load electrode in a second direction opposite the first direction.
    Type: Grant
    Filed: March 23, 2016
    Date of Patent: August 29, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Klaus Schiess
  • Device including multiple semiconductor chips and multiple carriers
    Patent number: 9735078
    Abstract: A device includes a first semiconductor chip that is arranged over a first carrier and includes a first electrical contact. The device further includes a second semiconductor chip arranged over a second carrier and including a second electrical contact arranged over a surface of the second semiconductor chip facing the second carrier. The second carrier is electrically coupled to the first electrical contact and the second electrical contact.
    Type: Grant
    Filed: April 16, 2014
    Date of Patent: August 15, 2017
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Klaus Schiess, Oliver Haeberlen, Matteo-Alessandro Kutschak
  • Printed Circuit Boards Having a Dielectric Layer Which Includes a Polymer and Methods of Manufacturing Such Printed Circuit Boards
    Publication number: 20170208684
    Abstract: A printed circuit board includes an electrically conductive layer and a dielectric layer including a polymer. The polymer includes at least one of a carbon layer structure and a carbon-like layer structure.
    Type: Application
    Filed: March 31, 2017
    Publication date: July 20, 2017
    Inventors: Joachim Mahler, Ralf Otremba
  • Electronic Component and Switch Circuit
    Publication number: 20170207306
    Abstract: In an embodiment, an electronic component includes a compound semiconductor transistor device having a first current electrode, a second current electrode and a control electrode, a die pad, a first lead, a second lead and a third lead. The first lead, the second lead and the third lead are spaced at a distance from the die pad. The control electrode is coupled to the first lead, the first current electrode is coupled to the die pad and the second current electrode is coupled to the second lead. The third lead is coupled to the compound semiconductor transistor device and provides a source sensing functionality.
    Type: Application
    Filed: January 18, 2016
    Publication date: July 20, 2017
    Inventors: Ralf Otremba, Klaus Schiess
  • Method for manufacturing a silicon carbide device and a silicon carbide device
    Patent number: 9704718
    Abstract: A method for manufacturing a silicon carbide device includes providing a silicon carbide wafer and manufacturing a mask layer on top of the silicon carbide wafer. Further, the method includes structuring the mask layer at an edge of a silicon carbide device to be manufactured, so that the mask layer includes a bevel at the edge of the silicon carbide device to be manufactured. Additionally, the method includes etching the mask layer and the silicon carbide wafer by a mutual etching process, so that the bevel of the mask layer is reproduced at the edge of the silicon carbide device.
    Type: Grant
    Filed: March 22, 2013
    Date of Patent: July 11, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Anton Mauder, Ralf Otremba, Jens Konrath
  • SEMICONDUCTOR DEVICES WITH IMPROVED THERMAL AND ELECTRICAL PERFORMANCE
    Publication number: 20170179009
    Abstract: A device may include a carrier, a semiconductor chip arranged over a first surface of the carrier, and an encapsulation body comprising six side surfaces and encapsulating the semiconductor chip. A second surface of the carrier opposite to the first surface of the carrier is exposed from the encapsulation body. The device may further include electrical contact elements electrically coupled to the semiconductor chip and protruding out of the encapsulation body exclusively through two opposing side surfaces of the encapsulation body which have the smallest surface areas of all the side surfaces of the encapsulation body, and an electrically insulating layer arranged over the exposed second surface of the carrier.
    Type: Application
    Filed: December 13, 2016
    Publication date: June 22, 2017
    Inventors: Ralf Otremba, Felix Grawert, Amirul Afiq Hud, Uwe Kirchner, Teck Sim Lee, Guenther Lohmann, Hwee Yin Low, Edward Fuergut, Bernd Schmoelzer, Fabian Schnoy, Franz Stueckler