Patents by Inventor Ralf Otremba

Ralf Otremba has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor chip package comprising side wall marking
    Publication number: 20170148743
    Abstract: The semiconductor chip package comprises a semiconductor chip, and an encapsulation body encapsulating the semiconductor chip, wherein the encapsulation body comprises a semiconductor chip; an encapsulation body encapsulating the semiconductor chip, wherein the encapsulation body comprises two opposing main faces and side faces which connect the two main faces with each other, wherein the side face have a smaller surface area than the main faces, respectively, and wherein a marking is provided on at least one of the side faces.
    Type: Application
    Filed: November 24, 2016
    Publication date: May 25, 2017
    Inventors: Ralf OTREMBA, Teck Sim LEE, Amirul Afiq HUD, Fabian SCHNOY, Felix GRAWERT, Uwe KIRCHNER, Bernd SCHMOELZER, Franz STUECKLER
  • Printed circuit boards and methods of manufacturing thereof
    Patent number: 9648735
    Abstract: A printed circuit board includes an electrically conductive layer and a dielectric layer including a polymer, wherein the polymer includes metallic particles.
    Type: Grant
    Filed: June 3, 2015
    Date of Patent: May 9, 2017
    Assignee: Infineon Technologies AG
    Inventors: Joachim Mahler, Ralf Otremba
  • Semiconductor housing with rear-side structuring
    Patent number: 9627292
    Abstract: A semiconductor housing includes a fixing mechanism and at least one side having structurings. A method for producing a semiconductor device is provided in which a thermally conductive paste is applied on the at least one side of the semiconductor housing and/or of a heat sink. The semiconductor housing is fixed to the heat sink by means of the fixing mechanism. A pressure is exerted on the thermally conductive paste by means of the fixing mechanism and the thermally conductive paste is diverted by means of diversion channels depending on the pressure exerted.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: April 18, 2017
    Assignee: Infineon Technologies AG
    Inventors: Ralf Otremba, Josef Hoeglauer, Xaver Schloegel, Juergen Schredl
  • Electronic component
    Patent number: 9620467
    Abstract: In an embodiment, a semiconductor device includes a lateral transistor device having an upper metallization layer. The upper metallization layer includes n elongated pad regions. Adjacent ones of the n elongated pad regions are coupled to different current electrodes of the lateral transistor device. The n elongated pad regions bound n?1 active regions of the lateral transistor where n?3.
    Type: Grant
    Filed: September 16, 2015
    Date of Patent: April 11, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Oliver Haeberlen, Ralf Otremba, Gerhard Prechtl, Klaus Schiess
  • Method of manufacturing an electronic component
    Patent number: 9620472
    Abstract: A method of manufacturing an electronic component includes applying solder paste to at least one electrically conductive portion of a package, applying a high-voltage depletion-mode transistor onto the solder paste, applying a low-voltage enhancement-mode transistor onto the solder paste, applying solder paste onto the high-voltage depletion-mode transistor, applying solder paste onto the low-voltage enhancement-mode transistor, applying an electrically conductive member onto the solder paste on the high-voltage depletion-mode transistor and onto the solder paste on the low-voltage enhancement-mode transistor to form an assembly, and heat treating the assembly to produce an electrical connection between the high-voltage depletion-mode transistor and the low-voltage enhancement-mode transistor via the electrically conductive member.
    Type: Grant
    Filed: August 31, 2016
    Date of Patent: April 11, 2017
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Klaus Schiess, Oliver Häberlen
  • Functionalized interface structure
    Publication number: 20170098598
    Abstract: An electronic component, the electronic component comprising an electrically conductive carrier, an electronic chip on the carrier, an encapsulant encapsulating part of the carrier and the electronic chip, and an electrically insulating and thermally conductive interface structure covering an exposed surface portion of the carrier and a connected surface portion of the encapsulant and being functionalized for promoting heat dissipation via the interface structure on a heat dissipation body.
    Type: Application
    Filed: September 21, 2016
    Publication date: April 6, 2017
    Inventors: Ralf OTREMBA, Edward Fuergut, Christian Kasztelan, Hsieh Ting Kuek, Teck Sim Lee, Sanjay Kumar Nurugan, Lee Shuang Wang
  • Circuit arrangement and method for manufacturing the same
    Patent number: 9595487
    Abstract: Various embodiments may provide a circuit arrangement. The circuit arrangement may include a carrier having at least one electrically conductive line; a plurality of discrete encapsulated integrated circuits arranged on the carrier; wherein a first integrated circuit of the plurality of integrated circuits is in electrical contact with a second integrated circuit of the plurality of integrated circuits to form a first current path bypassing the carrier; and wherein the first integrated circuit of the plurality of integrated circuits is in electrical contact with the second integrated circuit of the plurality of integrated circuits to form a second current path via the at least one electrically conductive line.
    Type: Grant
    Filed: June 25, 2013
    Date of Patent: March 14, 2017
    Assignee: INFINEON TECHNOLOGIES AG
    Inventors: Ralf Otremba, Klaus Schiess, Anton Mauder
  • Semiconductor device with bypass functionality and method thereof
    Patent number: 9589904
    Abstract: A device includes a semiconductor chip and a bypass layer electrically coupled to a contact region of the semiconductor chip. The bypass layer is configured to change from behaving as an insulator to behaving as a conductor in response to a condition of the semiconductor chip.
    Type: Grant
    Filed: February 14, 2013
    Date of Patent: March 7, 2017
    Assignee: Infineon Technologies Austria AG
    Inventor: Ralf Otremba
  • Method of Manufacturing a Multi-Chip Semiconductor Power Device
    Publication number: 20170047315
    Abstract: A method of manufacturing a semiconductor device includes mounting a first semiconductor power chip on a first carrier, mounting a second semiconductor power chip on a second carrier, bonding a contact clip to the first semiconductor power chip and to the second semiconductor power chip, and mounting a third semiconductor chip over the contact clip.
    Type: Application
    Filed: October 28, 2016
    Publication date: February 16, 2017
    Inventors: Ralf Otremba, Josef Hoeglauer, Xaver Schloegel, Chooi Mei Chong
  • Electronic device and method of manufacturing the same
    Publication number: 20170005025
    Abstract: Various embodiments provide an electronic device, wherein the electronic device comprises a mounting surface configured to mount the electronic device to an external structure and having a first size; a backside electrode having a second size and having arranged thereon a die electrically connected to the backside electrode; wherein the first size is at least three times the second size.
    Type: Application
    Filed: July 1, 2016
    Publication date: January 5, 2017
    Inventors: Ralf OTREMBA, Ulrich FROEHLER, Felix GRAWERT, Ernst KATZMAIER, Uwe KIRCHNER, Rene MENTE, Andreas SCHLOEGL, Uwe WAHL
  • Electronic device and method of manufacturing the same
    Publication number: 20160379919
    Abstract: Various embodiments provide an electronic device, wherein the electronic device comprises a carrier body; a plurality of pins, a die comprising a switched terminal; wherein the switched terminal is attached onto and electrically connected to one of the plurality of pins; and wherein the die is configured in such a way that the switched terminal is electrically connected to a high electrical potential.
    Type: Application
    Filed: June 21, 2016
    Publication date: December 29, 2016
    Inventors: Ralf OTREMBA, Ulrich FROEHLER, Felix GRAWERT
  • Method of Manufacturing an Electronic Component
    Publication number: 20160372439
    Abstract: A method of manufacturing an electronic component includes applying solder paste to at least one electrically conductive portion of a package, applying a high-voltage depletion-mode transistor onto the solder paste, applying a low-voltage enhancement-mode transistor onto the solder paste, applying solder paste onto the high-voltage depletion-mode transistor, applying solder paste onto the low-voltage enhancement-mode transistor, applying an electrically conductive member onto the solder paste on the high-voltage depletion-mode transistor and onto the solder paste on the low-voltage enhancement-mode transistor to form an assembly, and heat treating the assembly to produce an electrical connection between the high-voltage depletion-mode transistor and the low-voltage enhancement-mode transistor via the electrically conductive member.
    Type: Application
    Filed: August 31, 2016
    Publication date: December 22, 2016
    Inventors: Ralf Otremba, Klaus Schiess, Oliver Häberlen
  • Switching circuit
    Patent number: 9525063
    Abstract: In an embodiment, a switching circuit includes input drain, source and gate nodes, a high voltage depletion mode transistor including a current path coupled in series with a current path of a low voltage enhancement mode transistor, and an overheating detection circuit for detecting overheating of the switching circuit.
    Type: Grant
    Filed: October 30, 2013
    Date of Patent: December 20, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Klaus Schiess, Rainald Sander
  • Power semiconductor housing with redundant functionality
    Patent number: 9524941
    Abstract: In various embodiments, a power semiconductor housing having an integrated circuit is provided. The integrated circuit may include: a first gate pad and a second gate pad; and a first gate contact and a second gate contact; wherein the first gate pad is electrically connected to the first gate contact; wherein the second gate pad is electrically connected to the second gate contact. The integrated circuit may further include a drain-contact surface, wherein the drain-contact surface is connected to a drain contact; and a second drain contact, which is electrically connected to the drain-contact surface of the integrated circuit.
    Type: Grant
    Filed: September 25, 2013
    Date of Patent: December 20, 2016
    Assignee: INFINEON TECHNOLOGIES AG
    Inventor: Ralf Otremba
  • Electronic Devices with Increased Creepage Distances
    Publication number: 20160365296
    Abstract: A device includes an encapsulation material and a first lead and a second lead protruding out of a surface of the encapsulation material. A recess extends into the surface of the encapsulation material. An elevation is arranged on the surface of the encapsulation material. The first lead protrudes out of the elevation.
    Type: Application
    Filed: June 8, 2016
    Publication date: December 15, 2016
    Inventors: Ralf Otremba, Edward Fuergut, Christian Kasztelan, Hsieh Ting Kuek, Teck Sim Lee, Sanjay Kumar Murugan, Lee Shuang Wang
  • Semiconductor Power Package and Method of Manufacturing the Same
    Publication number: 20160358838
    Abstract: A semiconductor power package includes a pre-molded chip housing and an electrically conducting chip carrier cast-in-place in the pre-molded chip housing. The semiconductor power package further includes a power semiconductor chip bonded on the electrically conducting chip carrier. A covering material is provided to embed the power semiconductor chip. The covering material has an elastic modulus less than an elastic modulus of a material of the pre-molded chip housing and/or a thermal conductivity greater than a thermal conductivity of the material of the pre-molded chip housing and/or a temperature stability greater than a temperature stability of the pre-molded chip housing.
    Type: Application
    Filed: June 1, 2016
    Publication date: December 8, 2016
    Inventors: Thomas Basler, Edward Fuergut, Christian Kasztelan, Ralf Otremba
  • Multi-chip semiconductor power device
    Patent number: 9515060
    Abstract: A semiconductor device includes a first semiconductor power chip mounted over a first carrier and a second semiconductor power chip mounted over a second carrier. The semiconductor device further includes a contact clip mounted over the first semiconductor power chip and on the second semiconductor power chip. A semiconductor logic chip is mounted over the contact clip.
    Type: Grant
    Filed: March 20, 2013
    Date of Patent: December 6, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Josef Hoeglauer, Xaver Schloegel, Chooi Mei Chong
  • Device Including a Logic Semiconductor Chip Having a Contact Electrode for Clip Bonding
    Publication number: 20160315033
    Abstract: A device includes a logic semiconductor chip having a contact electrode. The contact electrode is configured to be electrically coupled to a contact clip based on a clip bonding technique.
    Type: Application
    Filed: April 21, 2016
    Publication date: October 27, 2016
    Inventors: Ralf Otremba, Josef Hoeglauer, Aliaksandr Subotski
  • Semiconductor packages and methods of formation thereof
    Patent number: 9478484
    Abstract: In accordance with an embodiment of the present invention, a semiconductor device includes a lead frame having a die paddle and a lead. A chip is disposed over the die paddle of the lead frame. The semiconductor device further includes a clip, which is disposed over the chip. The clip couples a pad on the chip to the lead of the lead frame. The clip also includes a heat sink.
    Type: Grant
    Filed: October 19, 2012
    Date of Patent: October 25, 2016
    Assignee: Infineon Technologies Austria AG
    Inventors: Ralf Otremba, Klaus Schiess, Chee Voon Tan
  • Compound Semiconductor Device Including a Multilevel Carrier
    Publication number: 20160293543
    Abstract: A device includes a carrier having a first carrier section on a first level and a second carrier section on a second level different from the first level. The device further includes a compound semiconductor chip arranged over the first carrier section and a control semiconductor chip arranged over the second carrier section. The control semiconductor chip is configured to control the compound semiconductor chip. An encapsulation material covers the compound semiconductor chip and the control semiconductor chip.
    Type: Application
    Filed: March 30, 2016
    Publication date: October 6, 2016
    Inventors: Ralf Otremba, Klaus Schiess