Abstract: The disclosed process includes the successive stages of providing a substrate comprising a dielectric layer; forming a first layer of block copolymers on a part of the dielectric layer, so that the dielectric layer exhibits free zones with a random spatial distribution; etching the free zones, so as to structure the dielectric layer; removing the first layer of block copolymers; forming a first electrode on the structured dielectric layer; forming a memory layer, of resistive memory type, on the first electrode; forming a second electrode on the memory layer; forming a second layer of block copolymers on a part of the second electrode, so that the second electrode exhibits free zones with a random spatial distribution; etching the free zones, so as to structure the second electrode; and removing the second layer of block copolymers.

Abstract: A method for functionalising a substrate intended for the self-assembly of a block copolymer, includes depositing on the surface of a substrate a layer of a first polymer material, the first polymer having a first chemical affinity with respect to the block copolymer; grafting one part only of the first polymer material layer onto the surface of the substrate; printing, using a mould, patterns in a sacrificial layer arranged above the grafted part of the first polymer material layer; transferring the patterns of the sacrificial layer into the grafted part of the first polymer material layer, until the substrate is reached; and removing at least one part of the sacrificial layer by wet etching, so as to uncover the grafted part of the first polymer material layer.

Abstract: A method for the directed self-assembly of a block copolymer by graphoepitaxy, includes forming a guide pattern, the guide pattern having a cavity with a bottom and side walls; forming a functionalisation layer on the guide pattern that has a first portion and a second portion disposed, respectively, on the bottom and side walls of the cavity; forming a protective layer on the first and second portions of the functionalisation layer; etching the protective layer and the second portion of the functionalisation layer such that a portion of the protective layer is retained and the side walls of the cavity are exposed, the retained portion of the protective layer having a thickness of less than 15 nm; selectively etching the portion of the protective layer relative to the first portion of the functionalisation layer and to the guide pattern; and depositing a block copolymer in the cavity.

Abstract: A method for forming a functionalised guide pattern for the self-assembly of a block copolymer by graphoepitaxy, includes forming a guide pattern made of a first material having a first chemical affinity for the block copolymer, the guide pattern having a cavity with a bottom and side walls; grafting a functionalisation layer made of a second polymeric material having a second chemical affinity for the block copolymer, the functionalisation layer having a first portion grafted onto the bottom of the cavity and a second portion grafted onto the side walls of the cavity; selectively etching the second portion of the functionalisation layer relative to the first portion of the functionalisation layer, the etching including a step of exposure to an ion beam following a direction that intersects the second portion of the functionalisation layer, such that the ion beam does not reach the first portion of the functionalisation layer.

Abstract: A method for forming a functionalised assembly guide intended for the self-assembly of a block copolymer by graphoepitaxy, includes forming on the surface of a substrate a neutralisation layer made of a first material having a first neutral chemical affinity with regard to the block copolymer; forming on the neutralisation layer a first mask including at least one recess; depositing on the neutralisation layer a second material having a second preferential chemical affinity for one of the copolymer blocks, in such a way as to fill the at least one recess of the first mask; and selectively etching the first mask relative to the first and second materials, thereby forming at least one guide pattern made of the second material arranged on the neutralisation layer.

Abstract: There is provided a method for making a device including at least a strained semiconductor structure configured to form at least a transistor channel, including: forming, on a semiconductor layer, a sacrificial gate block and source and drain blocks on either side of the block, the semiconductor layer being a strained surface semiconductor layer disposed on an underlying insulating layer, with the underlying layer being disposed on an etch-stop layer; removing the block to form a cavity revealing a region of the strained surface layer configured to form the transistor channel; and etching, in the cavity, one or more portions of the region to define one or more semiconductor blocks and holes on either side, respectively, of the one or more blocks, the etching of holes extending into the underlying layer to form one or more galleries therein, etching of the galleries being stopped by the etch-stop layer.

Abstract: A method for forming a chemical guiding structure intended for self-assembly of a block copolymer by chemoepitaxy, where the method includes forming on a substrate a functionalisation layer made of a first polymer material having a first chemical affinity with respect to the block copolymer; forming on the substrate guiding patterns made of a second polymer material having a second chemical affinity with respect to the block copolymer, different from the first chemical affinity, and wherein the guiding to patterns have a critical dimension of less than 12.5 nm and are formed by means of a mask comprising spacers.

Abstract: Realisation of a device comprising a transistor channel strained semiconductor structure, comprising: a) the formation, on a strained semiconductor layer, of a sacrificial gate block and of source and drain blocks on either side of the sacrificial gate block, b) removal of the sacrificial gate block so as to form a cavity, c) etching, in the cavity, of one or more portions of the region so as to define at least a semiconductor block and slots on either side of the semiconductor block.

Abstract: The invention concerns a manufacturing method for nanolithography masks from a PS-b-PMMA block copolymer film deposited on a surface to be etched, said copolymer film comprising PMMA nanodomains orientated perpendicularly to the surface to be etched, said method being characterized in that it comprises the following steps: partially irradiating said copolymer film to form a first irradiated area and a second non-irradiated area in said copolymer film, then treating said copolymer film in a developer solvent to selectively remove at least said PMMA nanodomains of said first irradiated area of said copolymer film.

Abstract: A method for making patterns on the surface of a substrate by graphoepitaxy, includes depositing a layer of resin on the surface of the substrate; making patterns in the resin on the surface of a substrate; curing the patterns in the resin by producing a layer of amorphous carbon on the surface of the patterns in the resin; depositing a layer of statistical copolymer after curing the patterns in the resin; grafting the layer of statistical copolymer onto the patterns in the resin by annealing; and depositing a layer of a block copolymer into the spaces defined by the patterns in the resin after curing the patterns and the grafting of the layer of statistical copolymer.

Abstract: A method for making patterns on a substrate, includes forming an assembly guide on first and second areas of the substrate, the assembly guide having, compared to a reference surface, openings with an opening ratio in the first area greater than that of the second area; depositing a block copolymer layer on the substrate to entirely fill the assembly guide and form an over-thickness on the reference surface; assembling the block copolymer, resulting in an organised portion of the block copolymer layer inside the openings; thinning uniformly the block copolymer layer, until a thickness corresponding to the organised portion of the block copolymer layer is reached; eliminating one of the phases of the assembled block copolymer, resulting in a plurality of initial patterns extending into the layer of block copolymer; and transferring the initial patterns of the block copolymer layer into the substrate to form the final patterns.

Abstract: The invention relates to a surface preparation method using a combination of at least two polymers, which are the same or different, which are grafted hierarchically or multiply on a surface, and also to the use of this preparation method, more particularly in applications for controlling the surface energy of a substrate. The invention may allow a block polymer to be structured with a minimum of defects.

Abstract: A field-effect transistor including an active zone comprises a source, a channel, a drain and a control gate, which is positioned level with the channel, allowing a current to flow through the channel between the source and drain along an x-axis, the channel comprising: a first edge of separation with the source; and a second edge of separation with the drain; the channel being compressively or tensilely strained, wherein the channel includes a localized perforation or a set of localized perforations along at least the first and/or second edge of the channel so as to also create at least one shear strain in the channel. A process for fabricating the transistor is provided.

Abstract: A method for making patterns on a substrate, includes forming an assembly guide on first and second areas of the substrate, the assembly guide having, compared to a reference surface, openings with an opening ratio in the first area greater than that of the second area; depositing a block copolymer layer on the substrate to entirely fill the assembly guide and form an over-thickness on the reference surface; assembling the block copolymer, resulting in an organised portion of the block copolymer layer inside the openings; thinning uniformly the block copolymer layer, until a thickness corresponding to the organised portion of the block copolymer layer is reached; eliminating one of the phases of the assembled block copolymer, resulting in a plurality of initial patterns extending into the layer of block copolymer; and transferring the initial patterns of the block copolymer layer into the substrate to form the final patterns.

Abstract: The invention concerns a manufacturing method for nanolithography masks from a PS-b-PMMA block copolymer film deposited on a surface to be etched, said copolymer film comprising PMMA nanodomains orientated perpendicularly to the surface to be etched, said method being characterized in that it comprises the following steps: partially irradiating said copolymer film to form a first irradiated area and a second non-irradiated area in said copolymer film, then treating said copolymer film in a developer solvent to selectively remove at least said PMMA nanodomains of said first irradiated area of said copolymer film.

Abstract: The present invention relates to a process for producing nanostructured films obtained from block copolymers exhibiting a dispersity index of between 1.1 and 2, limits included, without nanostructuring defects, on a surface, in order for this treated surface to be able to be used as masks for applications in microelectronics.

Abstract: A process for fabricating one transistor, comprising a semiconductor region, comprising a source region, a drain region, and a channel region covered with a gate, comprises: production of an primary etching mask on the surface of the semiconductor region, said mask containing at least one primary aperture; depositing in said primary aperture a block copolymer containing, in alternation, at least first polymer domains and second polymer domains; removing either a series of first polymer domains or a series of second polymer domains in order to create a secondary mask containing secondary apertures; etching said active region through said secondary apertures in order to define nanoscale self-aligned semiconductor features; producing said gate on the surface of said self-aligned semiconductor features.

Abstract: The present invention relates to a process for producing nanostructured films obtained from block copolymers exhibiting a dispersity index of between 1.1 and 2, limits included, without nanostructuring defects, on a surface, in order for this treated surface to be able to be used as masks for applications in microelectronics.

Abstract: The present invention relates to a process for controlling the period of a nanostructured assemblage comprising a blend of block copolymers which is deposited on a surface or in a mold. Block copolymers are characterized by the possession of at least one of the constituent monomers respectively of each of the blocks of the block copolymers identical but exhibit different molecular weights. The control process is targeted at obtaining thicknesses of films or objects, with few nanostructuring defects, which are sufficiently great for the treated surface to be able to be used as masks for applications in microelectronics or for the objects resulting therefrom to exhibit previously unpublished mechanical, acoustic or optical characteristics.

Abstract: The invention relates to a surface preparation method using a combination of at least two polymers, which are the same or different, which are grafted hierarchically or multiply on a surface, and also to the use of this preparation method, more particularly in applications for controlling the surface energy of a substrate. The invention may allow a block polymer to be structured with a minimum of defects.