Abstract: A method of removing an oxide layer is provided. A metal layer is deposited over an oxide layer formed at a top surface of a germanium substrate. A metal oxide layer is deposited over the metal layer. The metal oxide layer includes a same metal material as the metal layer. The metal layer and the oxide layer are reacted and combined with the metal oxide layer to form a dielectric layer during an anneal process. During the anneal process, the oxide layer is reacted with the metal layer and removed.

Abstract: A method of forming a semiconductor device (100) includes depositing a metal oxide (104) over the substrate (102). The depositing includes combining a first metal and oxygen to form the metal oxide having grains and further adding a catalyst during the combining. The catalyst causes the grains to be bigger than would occur in the absence of the catalyst. A conductive layer (202) is formed over the metal oxide.

Abstract: A method for forming a packaged semiconductor device includes attaching a first major surface of a semiconductor die to a plurality of protrusions extending from a package substrate. A top surface of each protrusion has a die attach material, and the plurality of protrusions define an open region between the first major surface of the semiconductor die and the package substrate. Interconnects are formed between a second major surface of the semiconductor die and the package substrate in which the second major surface opposite the first major surface. An encapsulant material is formed over the semiconductor die and the interconnects.

Abstract: A method of removing an oxide layer is provided. A metal layer is deposited over an oxide layer formed at a top surface of a germanium substrate. A metal oxide layer is deposited over the metal layer. The metal oxide layer includes a same metal material as the metal layer. The metal layer and the oxide layer are reacted and combined with the metal oxide layer to form a dielectric layer during an anneal process. During the anneal process, the oxide layer is reacted with the metal layer and removed.

Abstract: A semiconductor device includes a leadframe having a flag and a plurality of bond terminals. A semiconductor die is attached to the leadframe at the flag. A bond pad is formed on the semiconductor die. A top surface layer of the bond pad includes copper having a predetermined grain orientation. A bond wire includes a first end and a second end. The bond wire is attached to the bond pad at the first end and attached to one of the bond terminals in the plurality at the second end.

Abstract: A method for forming a metal oxide layer on a wafer. In some embodiments, the method includes forming a layer of a metal oxyhalide on a wafer followed by an anneal of the wafer which removes halogens from the layer to form a layer of metal oxide. A semiconductor device may be formed from the wafer.

Abstract: A method of forming a semiconductor device (100) includes depositing a metal oxide (104) over the substrate (102). The depositing includes combining a first metal and oxygen to form the metal oxide having grains and further adding a catalyst during the combining. The catalyst causes the grains to be bigger than would occur in the absence of the catalyst. A conductive layer (202) is formed over the metal oxide.

Abstract: A method of forming a semiconductor device (100) includes depositing a metal oxide (104) over the substrate (102). The depositing includes combining a first metal and oxygen to form the metal oxide having grains and further adding a catalyst during the combining. The catalyst causes the grains to be bigger than would occur in the absence of the catalyst. A conductive layer (202) is formed over the metal oxide.

Abstract: A method for forming a packaged semiconductor device includes attaching a first major surface of a semiconductor die to a plurality of protrusions extending from a package substrate. A top surface of each protrusion has a die attach material, and the plurality of protrusions define an open region between the first major surface of the semiconductor die and the package substrate. Interconnects are formed between a second major surface of the semiconductor die and the package substrate in which the second major surface opposite the first major surface. An encapsulant material is formed over the semiconductor die and the interconnects.

Abstract: A method of forming a semiconductor device (100) includes depositing a metal oxide (104) over the substrate (102). The depositing includes combining a first metal and oxygen to form the metal oxide having grains and further adding a catalyst during the combining. The catalyst causes the grains to be bigger than would occur in the absence of the catalyst. A conductive layer (202) is formed over the metal oxide.

Abstract: A method for forming a packaged semiconductor device includes attaching a first major surface of a semiconductor die to a plurality of protrusions extending from a package substrate. A top surface of each protrusion has a die attach material, and the plurality of protrusions define an open region between the first major surface of the semiconductor die and the package substrate. Interconnects are formed between a second major surface of the semiconductor die and the package substrate in which the second major surface opposite the first major surface. An encapsulant material is formed over the semiconductor die and the interconnects.

Abstract: A method of removing metal oxide from electrically conductive contacts of a packaged semiconductor device includes mixing a solution including vinegar and nitric acid, applying the solution to the contacts for a time sufficient to remove the metal oxide from the contacts, and rinsing the solution from the contacts.

Abstract: A method of forming a semiconductor device (100) includes depositing a metal oxide (104) over the substrate (102). The depositing includes combining a first metal and oxygen to form the metal oxide having grains and further adding a catalyst during the combining. The catalyst causes the grains to be bigger than would occur in the absence of the catalyst. A conductive layer (202) is formed over the metal oxide.

Abstract: A semiconductor structure is disclosed, wherein for a certain percentage of a plurality of bonding pads, the bonding pad metal may include a plurality of grains, wherein the plurality of grains may include a bonding grain. The bonding grain may have a width substantially the same as the width of the wire bonded to the bonding pad such that no grain boundaries are present below the wire bond.

Abstract: A coating layer for use in copper integrated circuit interconnect and other conductive structures hinders and decreases oxide growth on surfaces of such conductive structures. The coating layer includes an amorphous copper containing layer deposited on a crystalline copper substrate, such as utilized for a lead frame and a bonding wire. Additional amorphous layers may be interposed between the amorphous copper containing layer and the copper substrate, such as an amorphous tantalum nitride layer and an amorphous titanium nitride layer.

Abstract: A method for forming a packaged semiconductor device includes attaching a first major surface of a semiconductor die to a plurality of protrusions extending from a package substrate. A top surface of each protrusion has a die attach material, and the plurality of protrusions define an open region between the first major surface of the semiconductor die and the package substrate. Interconnects are formed between a second major surface of the semiconductor die and the package substrate in which the second major surface opposite the first major surface. An encapsulant material is formed over the semiconductor die and the interconnects.

Abstract: A semiconductor structure is disclosed, wherein for a certain percentage of a plurality of bonding pads, the bonding pad metal may include a plurality of grains, wherein the plurality of grains may include a bonding grain. The bonding grain may have a width substantially the same as the width of the wire bonded to the bonding pad such that no grain boundaries are present below the wire bond.

Abstract: A coating layer for use in copper integrated circuit interconnect and other conductive structures hinders and decreases oxide growth on surfaces of such conductive structures. The coating layer includes an amorphous copper containing layer deposited on a crystalline copper substrate, such as utilized for a lead frame and a bonding wire. Additional amorphous layers may be interposed between the amorphous copper containing layer and the copper substrate, such as an amorphous tantalum nitride layer and an amorphous titanium nitride layer.

Abstract: Methods and systems are disclosed for selectively forming metal layers on lead frames after die attachment to improve electrical connections for areas of interest on lead frames, such as for example, lead fingers and down-bond areas. By selectively forming metal layers on areas of interest after die attachment, the disclosed embodiments help to eliminate anomalies and associated defects for the lead frames that may be caused by the die attachment process. A variety of techniques can be utilized for selectively forming one or more metal layers, and a variety of metal materials can be used (e.g., nickel, palladium, gold, silver, etc.). Further, cleaning can also be performed with respect to the areas of interest prior to selectively forming the one or more metal layers on areas of interest for the leaf frame.

Abstract: A semiconductor fabrication method includes forming a gate dielectric stack on a semiconductor substrate and annealing the gate dielectric stack. Forming the stack may include depositing a first layer of a metal-oxide dielectric on the substrate, forming a refractory metal silicon nitride on the first layer, and depositing a second layer of the metal-oxide dielectric on the refractory metal silicon nitride. Depositing the first layer may include depositing a metal-oxide dielectric, such as HfO2, using atomic layer deposition. Forming the refractory metal silicon nitride film may include forming a film of tantalum silicon nitride using a physical vapor deposition process. Annealing the gate dielectric stack may include annealing the gate dielectric stack in an oxygen-bearing ambient at approximately 750 C for 10 minutes or less. In one embodiment, annealing the dielectric stack includes annealing the dielectric stack for approximately 60 seconds at a temperature of approximately 500 C.