Abstract: Methods and systems are disclosed for selectively forming metal layers on lead frames after die attachment to improve electrical connections for areas of interest on lead frames, such as for example, lead fingers and down-bond areas. By selectively forming metal layers on areas of interest after die attachment, the disclosed embodiments help to eliminate anomalies and associated defects for the lead frames that may be caused by the die attachment process. A variety of techniques can be utilized for selectively forming one or more metal layers, and a variety of metal materials can be used (e.g., nickel, palladium, gold, silver, etc.). Further, cleaning can also be performed with respect to the areas of interest prior to selectively forming the one or more metal layers on areas of interest for the leaf frame.

Abstract: A surface is placed into a deposition chamber. A tin layer is formed on the surface, in which forming the tin layer includes providing a precursor into the deposition chamber for a first time period, wherein the precursor comprises one of tetrakis (dimethylamino) tin (TDMASn) or tin tetrachloride (SnCl4), providing an inert gas into the deposition chamber for a second time period, providing a hydrogen reactant into the deposition chamber for a third time period, and providing the inert gas into the deposition chamber for a fourth time period. The first, second, third, and fourth time periods form one atomic layer deposition (ALD) cycle. The surface may be an exposed surface of a lead free metal.

Abstract: A semiconductor fabrication method includes forming a gate dielectric stack on a semiconductor substrate and annealing the gate dielectric stack. Forming the stack may include depositing a first layer of a metal-oxide dielectric on the substrate, forming a refractory metal silicon nitride on the first layer, and depositing a second layer of the metal-oxide dielectric on the refractory metal silicon nitride. Depositing the first layer may include depositing a metal-oxide dielectric, such as HfO2, using atomic layer deposition. Forming the refractory metal silicon nitride film may include forming a film of tantalum silicon nitride using a physical vapor deposition process. Annealing the gate dielectric stack may include annealing the gate dielectric stack in an oxygen-bearing ambient at approximately 750 C for 10 minutes or less. In one embodiment, annealing the dielectric stack includes annealing the dielectric stack for approximately 60 seconds at a temperature of approximately 500 C.

Abstract: A packaged electronic component and method of forming. The packaged electronic component is formed with a lead frame. The lead frame includes at least one silver structure. The silver structure attracts sulfur so as to inhibit sulfur contamination on the rest of the lead frame. In one example, the silver of the at least one silver structure has an average grain size thickness of one micron or less. In one embodiment, a sulfur removal process can be performed to remove sulfur from the silver structure.

Abstract: A method of testing a contact structure including exposing a gold layer of at least one contact structure of a support structure to a solution including glacial acetic acid and nitric acid; and determining a porosity of the gold layer of at least one contact structure after the exposing.

Abstract: A method of testing a contact structure including exposing a gold layer of at least one contact structure of a support structure to a solution including glacial acetic acid and nitric acid; and determining a porosity of the gold layer of at least one contact structure after the exposing.

Abstract: A method of making a semiconductor device includes making a gate dielectric with an overlying gate electrode. The semiconductor device is made over a semiconductor layer. A high-k dielectric comprising hafnium zirconate is deposited over the semiconductor layer. The high-k dielectric is annealed at a temperature between 650 degrees Celsius and 850 degrees Celsius in an ambient comprising hydrogen and nitrogen. The gate electrode is formed on the high-k dielectric. The high-k dielectric function is for use in the gate dielectric. One affect is to improve the transistor performance while retaining or even improving the level of gate leakage.

Abstract: A stack located over a substrate. The stack includes a layer between a dielectric layer and a metal layer. The layer includes a halogen and a metal. In one embodiment, the halogen is fluorine. In one embodiment, the stack is a control electrode stack for a transistor. In one example the control electrode stack is a gate stack for a MOSFET. In one example, the layer includes aluminum fluoride.

Abstract: A gate electrode (202) for a transistor including a metal gate structure (207) containing zirconium and a polycrystalline silicon cap (209) located there over. The metal gate structure (207) is located over a gate dielectric (205). The zirconium inhibits diffusion of silicon from the cap to the metal gate structure and gate dielectric. In one embodiment, the gate dielectric is a high K dielectric.

Abstract: A stack located over a substrate. The stack includes a layer between a dielectric layer and a metal layer. The layer includes a halogen and a metal. In one embodiment, the halogen is fluorine. In one embodiment, the stack is a control electrode stack for a transistor. In one example the control electrode stack is a gate stack for a MOSFET. In one example, the layer includes aluminum fluoride.

Abstract: A mixture of materials can be used within a layer of an electronic device to improve electrical and physical properties of the layer. In one set of embodiments, the layer can be a dielectric layer, such as a gate dielectric layer or a capacitor dielectric layer. The dielectric layer can include O, and two or more dissimilar metallic elements. In one specific embodiment, two dissimilar elements may have the same single oxidation state and be miscible within each other. In one embodiment, the dielectric layer can include an alloy of (HfO2)(1-x)(ZrO2)x, wherein x is between 0 and 1. Each of Hf and Zr has a single oxidation state of +4. Other combinations are possible. Improved electrical and physical properties can include better control over grain size, distribution of grain sizes, thickness of the layer across a substrate, improved carrier mobility, threshold voltage stability, or any combination thereof.

Abstract: A transistor device has a gate dielectric with at least two layers in which one is hafnium oxide and the other is a metal oxide different from hafnium oxide. Both the hafnium oxide and the metal oxide also have a high dielectric constant. The metal oxide provides an interface with the hafnium oxide that operates as a barrier for contaminant penetration. Of particular concern is boron penetration from a polysilicon gate through hafnium oxide to a semiconductor substrate. The hafnium oxide will often have grain boundaries in its crystalline structure that provide a path for boron atoms. The metal oxide has a different structure than that of the hafnium oxide so that those paths for boron in the hafnium oxide are blocked by the metal oxide. Thus, a high dielectric constant is provided while preventing boron penetration from the gate electrode to the substrate.

Abstract: A transistor device has a gate dielectric with at least two layers in which one is hafnium oxide and the other is a metal oxide different from hafnium oxide. Both the hafnium oxide and the metal oxide also have a high dielectric constant. The metal oxide provides an interface with the hafnium oxide that operates as a barrier for contaminant penetration. Of particular concern is boron penetration from a polysilicon gate through hafnium oxide to a semiconductor substrate. The hafnium oxide will often have grain boundaries in its crystalline structure that provide a path for boron atoms. The metal oxide has a different structure than that of the hafnium oxide so that those paths for boron in the hafnium oxide are blocked by the metal oxide. Thus, a high dielectric constant is provided while preventing boron penetration from the gate electrode to the substrate.

Abstract: A method for forming a semiconductor device is disclosed in which a metal oxide gate dielectric layer is formed over a substrate. A gate electrode is then formed over the metal oxide layer thereby exposing a portion of the metal oxide layer. The exposed portion of the metal oxide gate dielectric layer is then chemically reduced to a metal or a metal hydride. The metal or metal hydride is then removed with a conventional wet etch or wet/dry etch combination. The metal oxide layer may include a metal element such as zirconium, tantalum, hafnium, titanium, or lanthanum and may further include an additional element such as silicon or nitrogen. Reducing the metal oxide layer may includes annealing the metal oxide gate dielectric layer in an ambient with an oxygen partial pressure that is less than a critical limit for oxygen desorption at a given temperature.

Abstract: A finished structure (100) includes a semiconductive region (102), a first oxide layer (106), a second oxide layer (108), and a conductive layer (110). The first oxide layer (106) lies between the semiconductive region (102) and the second oxide layer (108); and the second oxide layer (108) lies between the first oxide layer (106) and the conductive layer (110). The first oxide layer (106) includes at least a portion that is amorphous or includes a first element, a second element, and a third element. In the latter, the first element is a metallic element, and each of the first, second, and third elements are different from each other. A process for forming a structure (100) includes forming a first layer (106) near a semiconductive region (102), forming a second layer (108) after forming the first layer (106), and forming a third layer (110) after forming the second layer (108). The first oxide layer (106) includes a metallic element and oxygen. The third layer (110) is a non-insulating layer.

Abstract: A method for forming a semiconductor device is disclosed in which a metal oxide gate dielectric layer is formed over a substrate. A gate electrode is then formed over the metal oxide layer thereby exposing a portion of the metal oxide layer. The exposed portion of the metal oxide gate dielectric layer is then chemically reduced to a metal or a metal hydride. The metal or metal hydride is then removed with a conventional wet etch or wet/dry etch combination. The metal oxide layer may include a metal element such as zirconium, tantalum, hafnium, titanium, or lanthanum and may further include an additional element such as silicon or nitrogen. Reducing the metal oxide layer may includes annealing the metal oxide gate dielectric layer in an ambient with an oxygen partial pressure that is less than a critical limit for oxygen desorption at a given temperature.

Abstract: A method for forming an oxynitride gate dielectric layer (202, 204) begins by providing a semiconductor substrate (200). This semiconductor substrate is cleaned via process steps (10-28). Optional nitridation and oxidation are performed via steps (50 and 60) to form a thin interface layer (202). Bulk oxynitride gate deposition occurs via a step (70) to form a bulk gate dielectric material (204) having custom tailored oxygen and nitrogen profile and concentration. A step (10) is then utilized to in situ cap this bulk dielectric layer (204) with a polysilicon or amorphous silicon layer (208). The layer (208) ensures that the custom tailors oxygen and nitrogen profile and concentration of the underlying gate dielectric (204) is preserved even in the presence of subsequent wafer exposure to oxygen ambients.

Abstract: A first metal-containing material (22) is formed over a semiconductor device substrate (10). A second metal-containing material (32) is formed over the first metal containing material (22). The combination of the second metal-containing material (32) formed over the first metal-containing material (22) forms a metal stack (34). The metal stack (34) is annealed and a post-anneal stress of the metal stack (34) is less than an individual post-anneal stress of either one of the first conductive film (22) or the second conductive film (32).

Abstract: A method for insitu performing a cleaning operation along with a physical sputtering operation begins by placing a wafer (26) into a chamber (12). A plasma (30) is generated within the chamber (12) using an inert, noble, or reducing gas. The gas is ionized to form ions (32) within the plasma (30). Power is provided to various components (16, 22, and 24) within the chamber (12) to ensure that the ions (32) are accelerated towards the wafer (26) during first stages of wafer processing. This acceleration of the ions (32) towards the wafer (26) will clean a surface of the wafer (26). Following this cleaning operation, power supplied within the chamber (12) is altered to accelerate the ions (32) into a reverse direction so that the ions (32) impact a sputter target (20). Due to ionic bombardment of the target (20), a material is sputtered onto a clean surface of the wafer (26) in an insitu manner.

Abstract: A method for forming an improved copper barrier layer begins by providing a silicon-containing layer (10). A physical vapor deposition process is then used to form a thin tantalum nitride amorphous layer (12). A thin amorphous titanium nitride layer (14) is then deposited over the amorphous tantalum nitride layer. A collective thickness of the tantalum nitride and titanium nitride layers 12 and 14 is roughly 400 angstroms or less. A copper material 16 is then deposited on top of the amorphous titanium nitride wherein the composite tantalum nitride layer 12 and titanium nitride layer 14 effectively prevents copper from diffusion from the layer 16 to the layer 10.