Patents by Inventor Ramakanth Alapati
Ramakanth Alapati has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8598043Abstract: The invention includes methods of forming isolation regions for semiconductor constructions. A hard mask can be formed and patterned over a semiconductor substrate, with the patterned hard mask exposing a region of the substrate. Such exposed region can be etched to form a first opening having a first width. The first opening is narrowed with a conformal layer of carbon-containing material. The conformal layer is punched through to expose substrate along a bottom of the narrowed opening. The exposed substrate is removed to form a second opening which joins to the first opening, and which has a second width less than the first width. The carbon-containing material is then removed from within the first opening, and electrically insulative material is formed within the first and second openings. The electrically insulative material can substantially fill the first opening, and leave a void within the second opening.Type: GrantFiled: September 20, 2010Date of Patent: December 3, 2013Assignee: Micron Technology Inc.Inventors: Ramakanth Alapati, Ardavan Niroomand, Gurtej S. Sandhu, Luan C. Tran
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Patent number: 8598632Abstract: An integrated circuit having differently-sized features wherein the smaller features have a pitch multiplied relationship with the larger features, which are of such size as to be formed by conventional lithography.Type: GrantFiled: June 22, 2012Date of Patent: December 3, 2013Assignee: Round Rock Research LLCInventors: Luan Tran, William T. Rericha, John Lee, Ramakanth Alapati, Sheron Honarkhah, Shuang Meng, Puneet Sharma, Jingyi Bai, Zhiping Yin, Paul Morgan, Mirzafer K. Abatchev, Gurtej S. Sandhu, D. Mark Durcan
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Publication number: 20130277854Abstract: A method of forming an integrated circuit device includes providing a substrate including an active device, forming a through silicon via into the substrate, forming a device contact to the active device, forming a conductive layer over the through silicon via and the device contact, and forming a connecting via structure for electrically connecting the conductive layer with the through silicon via. An integrated circuit device includes a through silicon via formed into a substrate silicon material, a conductive layer formed over the through silicon via, and a connecting via structure formed between the conductive layer and the through silicon via for electrically connecting the conductive layer with the through silicon via. The connecting via structure comprises a first series of via bars intersected with a second series of via bars.Type: ApplicationFiled: April 23, 2012Publication date: October 24, 2013Applicant: GLOBALFOUNDRIES INC.Inventors: Chun Yu Wong, Ramakanth Alapati, Teck Jung Tang
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Patent number: 8431456Abstract: Some embodiments include formation of polymer spacers along sacrificial material, removal of the sacrificial material, and utilization of the polymer spacers as masks during fabrication of integrated circuitry. The polymer spacer masks may, for example, be utilized to pattern flash gates of a flash memory array. In some embodiments, the polymer is simultaneously formed across large sacrificial structures and small sacrificial structures. The polymer is thicker across the large sacrificial structures than across the small sacrificial structures, and such difference in thickness is utilized to fabricate high density structures and low-density structures with a single photomask.Type: GrantFiled: May 31, 2012Date of Patent: April 30, 2013Assignee: Micron Technology, Inc.Inventors: Ramakanth Alapati, Ardavan Niroomand, Gurtej S. Sandhu
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Patent number: 8338959Abstract: A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further comprises depositing an oxide material over the plurality of mandrels by an atomic layer deposition (ALD) process. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces. The method further comprises selectively etching photoresist material.Type: GrantFiled: September 12, 2011Date of Patent: December 25, 2012Assignee: Micron Technology, Inc.Inventors: Ardavan Niroomand, Baosuo Zhou, Ramakanth Alapati
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Publication number: 20120256309Abstract: An integrated circuit having differently-sized features wherein the smaller features have a pitch multiplied relationship with the larger features, which are of such size as to be formed by conventional lithography.Type: ApplicationFiled: June 22, 2012Publication date: October 11, 2012Inventors: Luan Tran, William T. Rericha, John Lee, Ramakanth Alapati, Sheron Honarkhah, Shuang Meng, Puneet Sharma, Jingyi (Jenny) Bai, Zhiping Yin, Paul Morgan, Mirzafer K. Abatchev, Gurtej S. Sandhu, D. Mark Durcan
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Publication number: 20120238077Abstract: Some embodiments include formation of polymer spacers along sacrificial material, removal of the sacrificial material, and utilization of the polymer spacers as masks during fabrication of integrated circuitry. The polymer spacer masks may, for example, be utilized to pattern flash gates of a flash memory array. In some embodiments, the polymer is simultaneously formed across large sacrificial structures and small sacrificial structures. The polymer is thicker across the large sacrificial structures than across the small sacrificial structures, and such difference in thickness is utilized to fabricate high density structures and low-density structures with a single photomask.Type: ApplicationFiled: May 31, 2012Publication date: September 20, 2012Applicant: MICRON TECHNOLOGY, INC.Inventors: Ramakanth Alapati, Ardavan Niroomand, Gurtej S. Sandhu
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Patent number: 8207576Abstract: Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC.Type: GrantFiled: January 31, 2007Date of Patent: June 26, 2012Assignee: Round Rock Research, LLCInventors: Luan Tran, William T Rericha, John Lee, Ramakanth Alapati, Sheron Honarkhah, Shuang Meng, Puneet Sharma, Jingyi Bai, Zhiping Yin, Paul Morgan, Mirzafer K Abatchev, Gurtej S Sandhu, D. Mark Durcan
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Patent number: 8207570Abstract: Some embodiments include formation of polymer spacers along sacrificial material, removal of the sacrificial material, and utilization of the polymer spacers as masks during fabrication of integrated circuitry. The polymer spacer masks may, for example, be utilized to pattern flash gates of a flash memory array. In some embodiments, the polymer is simultaneously formed across large sacrificial structures and small sacrificial structures. The polymer is thicker across the large sacrificial structures than across the small sacrificial structures, and such difference in thickness is utilized to fabricate high density structures and low-density structures with a single photomask.Type: GrantFiled: August 6, 2010Date of Patent: June 26, 2012Assignee: Micron Technology, Inc.Inventors: Ramakanth Alapati, Ardavan Niroomand, Gurtej S. Sandhu
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Patent number: 8143167Abstract: Trench isolation structures and methods to form same for use in the manufacture of semiconductor devices are described. The trench isolation structures are formed using several processing schemes that utilize disclosed dry etching processes to form a significant depth ? between an array trench depth and a periphery trench depth. One etching method creates a trench delta depth utilizing a single dry etch step, while two other etching methods create a trench ? depth by utilizing three dry etch steps.Type: GrantFiled: March 3, 2009Date of Patent: March 27, 2012Assignee: Micron Technology, Inc.Inventors: Xiaolong Fang, Ramakanth Alapati, Tuman E. Allen
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Patent number: 8119535Abstract: Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern and conventional photolithography used to form the relatively large features of the second pattern. Pitch multiplication is accomplished by patterning a photoresist and then etching that pattern into an amorphous carbon layer. Sidewall spacers are then formed on the sidewalls of the amorphous carbon. The amorphous carbon is removed, leaving behind the sidewall spacers, which define the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited around the spacers to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is then is transferred to the BARC.Type: GrantFiled: December 11, 2009Date of Patent: February 21, 2012Assignee: Round Rock Research, LLCInventors: Luan Tran, William T Rericha, John Lee, Ramakanth Alapati, Sheron Honarkhah, Shuang Meng, Puneet Sharma, Jingyi Bai, Zhiping Yin, Paul Morgan, Mirzafer K Abatchev, Gurtej S Sandhu, D. Mark Durcan
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Publication number: 20110316114Abstract: A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further comprises depositing an oxide material over the plurality of mandrels by an atomic layer deposition (ALD) process. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces. The method further comprises selectively etching photoresist material.Type: ApplicationFiled: September 12, 2011Publication date: December 29, 2011Applicant: Micron Technology, Inc.Inventors: Ardavan Niroomand, Baosuo Zhou, Ramakanth Alapati
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Patent number: 8048812Abstract: Differently-sized features of an integrated circuit are formed by etching a substrate using a mask which is formed by combining two separately formed patterns. Pitch multiplication is used to form the relatively small features of the first pattern. Pitch multiplication is accomplished by patterning an amorphous carbon layer. Sidewall spacers are then formed on the amorphous carbon sidewalls which are then removed; the sidewall spacers defining the first mask pattern. A bottom anti-reflective coating (BARC) is then deposited to form a planar surface and a photoresist layer is formed over the BARC. The photoresist is next patterned by conventional photolithography to form the second pattern, which is transferred to the BARC. The combined pattern is transferred to an underlying amorphous silicon layer. The combined pattern is then transferred to the silicon oxide layer and then to an amorphous carbon mask layer. The combined mask pattern, is then etched into the underlying substrate.Type: GrantFiled: April 28, 2010Date of Patent: November 1, 2011Assignee: Round Rock Research, LLCInventors: Luan Tran, William T. Rericha, John Lee, Ramakanth Alapati, Sheron Honarkhah, Shuang Meng, Puneet Sharma, Jingyi Bai, Zhiping Yin, Paul Morgan, Mirzafer K. Abatchev, Gurtej S. Sandhu, D. Mark Durcan
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Patent number: 8030217Abstract: A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels. The method further comprises depositing an oxide material over the plurality of mandrels by an atomic layer deposition (ALD) process. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces. The method further comprises selectively etching photoresist material.Type: GrantFiled: April 30, 2010Date of Patent: October 4, 2011Assignee: Micron Technology, Inc.Inventors: Ardavan Niroomand, Baosuo Zhou, Ramakanth Alapati
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Patent number: 7902074Abstract: A method for fabricating a semiconductor device comprises patterning a layer of photoresist material to form a plurality of mandrels in a device array region. The method further comprises depositing an oxide material over the plurality of mandrels and over a device peripheral region. The method further comprises forming a pattern of photoresist material over the oxide material in the device peripheral region. The method further comprises anisotropically etching the oxide material from exposed horizontal surfaces in the device array region. The method further comprises selectively etching photoresist material from the device array region and from the device peripheral region.Type: GrantFiled: April 7, 2006Date of Patent: March 8, 2011Assignee: Micron Technology, Inc.Inventors: Ardavan Niroomand, Baosuo Zhou, Ramakanth Alapati
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Publication number: 20110008970Abstract: The invention includes methods of forming isolation regions for semiconductor constructions. A hard mask can be formed and patterned over a semiconductor substrate, with the patterned hard mask exposing a region of the substrate. Such exposed region can be etched to form a first opening having a first width. The first opening is narrowed with a conformal layer of carbon-containing material. The conformal layer is punched through to expose substrate along a bottom of the narrowed opening. The exposed substrate is removed to form a second opening which joins to the first opening, and which has a second width less than the first width. The carbon-containing material is then removed from within the first opening, and electrically insulative material is formed within the first and second openings The electrically insulative material can substantially fill the first opening, and leave a void within the second opening.Type: ApplicationFiled: September 20, 2010Publication date: January 13, 2011Inventors: Ramakanth Alapati, Ardavan Niroomand, Gurtej S. Sandhu, Luan C. Tran
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Patent number: 7867843Abstract: A process may include forming a polysilicon pinnacle above and on a polysilicon island and further forming a floating gate from the polysilicon pinnacle and polysilicon island. The floating gate can bear an inverted T-shape. The floating gate can also be disposed above an isolated semiconductive substrate such as in a shallow-trench isolation semiconductive substrate. Electronic devices may include the floating gate as part of a field effect transistor.Type: GrantFiled: December 22, 2006Date of Patent: January 11, 2011Assignee: Intel CorporationInventors: Ramakanth Alapati, Ardavan Niroomand
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Publication number: 20100295114Abstract: Some embodiments include formation of polymer spacers along sacrificial material, removal of the sacrificial material, and utilization of the polymer spacers as masks during fabrication of integrated circuitry. The polymer spacer masks may, for example, be utilized to pattern flash gates of a flash memory array. In some embodiments, the polymer is simultaneously formed across large sacrificial structures and small sacrificial structures. The polymer is thicker across the large sacrificial structures than across the small sacrificial structures, and such difference in thickness is utilized to fabricate high density structures and low-density structures with a single photomask.Type: ApplicationFiled: August 6, 2010Publication date: November 25, 2010Applicant: MICRON TECHNOLOGY, INC.Inventors: Ramakanth Alapati, Ardavan Niroomand, Gurtej S. Sandhu
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Patent number: 7799694Abstract: The invention includes methods of forming isolation regions for semiconductor constructions. A hard mask can be formed and patterned over a semiconductor substrate, with the patterned hard mask exposing a region of the substrate. Such exposed region can be etched to form a first opening having a first width. The first opening is narrowed with a conformal layer of carbon-containing material. The conformal layer is punched through to expose substrate along a bottom of the narrowed opening. The exposed substrate is removed to form a second opening which joins to the first opening, and which has a second width less than the first width. The carbon-containing material is then removed from within the first opening, and electrically insulative material is formed within the first and second openings. The electrically insulative material can substantially fill the first opening, and leave a void within the second opening.Type: GrantFiled: April 11, 2006Date of Patent: September 21, 2010Assignee: Micron Technology, Inc.Inventors: Ramakanth Alapati, Ardavan Niroomand, Gurtej S. Sandhu, Luan C. Tran
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Patent number: 7790360Abstract: Some embodiments include formation of polymer spacers along sacrificial material, removal of the sacrificial material, and utilization of the polymer spacers as masks during fabrication of integrated circuitry. The polymer spacer masks may, for example, be utilized to pattern flash gates of a flash memory array. In some embodiments, the polymer is simultaneously formed across large sacrificial structures and small sacrificial structures. The polymer is thicker across the large sacrificial structures than across the small sacrificial structures, and such difference in thickness is utilized to fabricate high density structures and low-density structures with a single photomask.Type: GrantFiled: March 5, 2007Date of Patent: September 7, 2010Assignee: Micron Technology, Inc.Inventors: Ramakanth Alapati, Ardavan Niroomand, Gurtej S. Sandhu