Patents by Inventor Ramamurthy Krithivas

Ramamurthy Krithivas has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160283433
    Abstract: In one embodiment, a node includes at least one core to independently execute instructions; a first host device to receive information from the at least one core and to include the information in a first packet of a first communication protocol; a selection logic coupled to the first host device to receive the first packet and to provide the first packet to a conversion logic or a first interface to communicate with a first device via a first interconnect of the first communication protocol; the conversion logic to receive the first packet under selection of the selection logic and to encapsulate the first packet into a second packet of a second communication protocol; and a second interface coupled to the conversion logic to receive the second packet and to communicate the second packet to a second device via a second interconnect of the second communication protocol. Other embodiments are described and claimed.
    Type: Application
    Filed: March 26, 2015
    Publication date: September 29, 2016
    Inventors: Mohan K. Nair, Brent D. Thomas, Ramamurthy Krithivas
  • Publication number: 20160274941
    Abstract: The present disclosure is directed to hardware-based inter-device resource sharing. For example, a remote orchestrator (RO) may provide instructions to cause a device to make at least one hardware resource available to other devices. An RO module in the device may interact with the RO and may configure a configuration module in the device based on instructions received from the RO. The configuration module may set a device configuration when the device transitions from a power off state to a power on state. The device may also comprise a processing module to process data based on the device configuration, interface technology (IT) and at least one hardware resource. The interface technology may allow the processing module and the at least one hardware resource to interact. The RO module may configure the IT to allow the at least one hardware resource to operate locally or remotely based on the instructions.
    Type: Application
    Filed: March 16, 2015
    Publication date: September 22, 2016
    Applicant: Intel Corporation
    Inventors: RAMAMURTHY KRITHIVAS, BALAJI PARTHASARATHY
  • Publication number: 20160179383
    Abstract: Apparatus, systems, and methods to implement a virtual serial presence detect operation for pooled memory are described. In one embodiment, a controller comprises logic to receive a request to establish a composed computing device, define a plurality of virtual memory devices to be associated with a composed computing device, allocate memory from a shared pool of physical memory to the plurality of virtual memory devices, create a plurality of virtual serial detects (vSPDs) for the plurality of virtual memory devices, and store the plurality of vSPDs in a linked list in an operational memory device. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: December 22, 2014
    Publication date: June 23, 2016
    Applicant: Intel Corporation
    Inventors: RAMAMURTHY KRITHIVAS, ESWARAMOORTHI NALLUSAMY, MARK A. SCHMISSEUR
  • Publication number: 20160179411
    Abstract: Examples may include techniques to provide redundant array of independent disks (RAID) services using a shared pool of configurable computing resources. Information for a data service being provided using the shared pool of configurable computing resources may be received. Logical servers hosting logical volume managers (LVMs) may be composed from at least a portion of the shared pool of configurable computing resources. In some examples, the hosted LVMs are capable of each providing a RAID service based, at least in part, on the received information for the data service.
    Type: Application
    Filed: December 23, 2014
    Publication date: June 23, 2016
    Applicant: Intel Corporation
    Inventors: Patrick Connor, Scott P. Dubal, Ramamurthy Krithivas, Chris Pavlas
  • Publication number: 20160147291
    Abstract: In an embodiment, a processor includes a first chip of a multi-chip package (MCP). The first chip includes at least one core and first chip temperature control (TC) logic to assert a first power adjustment signal at a second chip of the MCP responsive to an indication that a first chip temperature of the first chip exceeds a first threshold. The processor also includes a conduit that includes a bi-directional pin to couple the first chip to the second chip within the MCP. The conduit is to transport the first power adjustment signal from the first chip to the second chip and the first power adjustment signal is to cause an adjustment of a second chip power consumption of the second chip. Other embodiments are described and claimed.
    Type: Application
    Filed: November 26, 2014
    Publication date: May 26, 2016
    Inventors: Tessil Thomas, Phani Kumar Kandula, Ramamurthy Krithivas, Howard Chin, Ian M. Steiner, Vivek Garg
  • Publication number: 20160087847
    Abstract: Mechanisms to enable management controllers to learn the control plane hierarchy in data center environments. The data center is configured in a physical hierarchy including multiple pods, racks, trays, and sleds and associated switches. Management controllers at various levels in a control plane hierarchy and associated with switches in the physical hierarchy are configured to add their IP addresses to DHCP (Dynamic Host Control Protocol) responses that are generated by a DCHP server in response to DCHP requests for IP address requests initiated by DHCP clients including manageability controllers, compute nodes and storage nodes in the data center. As the DCHP response traverses each of multiple switches along a forwarding path from the DCHP server to the DHCP client, an IP address of the manageability controller associated with the switch is inserted. Upon receipt at the DHCP client, the inserted IP addresses are extracted and used to automate learning of the control plane hierarchy.
    Type: Application
    Filed: September 24, 2014
    Publication date: March 24, 2016
    Applicant: INTEL CORPORATION
    Inventors: Ramamurthy Krithivas, Narayan Ranganathan, Mohan J. Kumar, John C. Leung
  • Patent number: 9098302
    Abstract: Methods and apparatus are disclosed to improve system boot speed. A disclosed example method includes associating a first serial peripheral interface (SPI) with a baseboard management controller (BMC), copying an image from the first SPI to a volatile memory in response to receiving power at the BMC, and in response to receiving an access request associated with the first SPI, providing access to the image stored in the volatile memory.
    Type: Grant
    Filed: June 28, 2012
    Date of Patent: August 4, 2015
    Assignee: Intel Corporation
    Inventors: Robert Swanson, Mallik Bulusu, Palsamy Sakthikumar, Ramamurthy Krithivas, James Steven Burns
  • Publication number: 20150095515
    Abstract: A first computational device receives a response generated by a second computational device for a third computational device. A target that is suitable for use by the third computational device is determined. The response is transmitted with an address of the target to the third computational device.
    Type: Application
    Filed: September 27, 2013
    Publication date: April 2, 2015
    Inventors: Ramamurthy Krithivas, Jacek Reniecki, Daniel P. Daly, Madhusudhan Rangarajan
  • Publication number: 20140189197
    Abstract: Methods and apparatus related to sharing Serial Peripheral Interface (SPI) flash memory in a multi-node server SoC (System on Chip) platform environment are described. In one embodiment, multi-port non-volatile memory is shared by a plurality of System on Chip (SoC) devices. Each of the plurality of SoC devices comprises controller logic to control access to the multi-port non-volatile memory and/or to translate a host referenced address of a memory access request to a linear address space and a physical address space of the multi-port non-volatile memory. Other embodiments are also disclosed and claimed.
    Type: Application
    Filed: December 27, 2012
    Publication date: July 3, 2014
    Inventors: RAMAMURTHY KRITHIVAS, PALSAMY SAKTHIKUMAR
  • Patent number: 8631150
    Abstract: A management request from a management client to perform an operation on a storage element includes an instance identifier identifying the storage element. A translator translates the instance identifier to a storage identifier that uniquely identifies the storage element. The method identifying the operation and the storage identifier is encapsulated in a storage command and forwarded to the storage element.
    Type: Grant
    Filed: June 21, 2006
    Date of Patent: January 14, 2014
    Assignee: Intel Corporation
    Inventor: Ramamurthy Krithivas
  • Publication number: 20140006764
    Abstract: Methods and apparatus are disclosed to improve system boot speed. A disclosed example method includes associating a first serial peripheral interface (SPI) with a baseboard management controller (BMC), copying an image from the first SPI to a volatile memory in response to receiving power at the BMC, and in response to receiving an access request associated with the first SPI, providing access to the image stored in the volatile memory.
    Type: Application
    Filed: June 28, 2012
    Publication date: January 2, 2014
    Inventors: Robert Swanson, Mallik Bulusu, Palsamy Sakthikumar, Ramamurthy Krithivas, James Steven Burns
  • Patent number: 8086833
    Abstract: A BIOS includes a core and multiple modules. The modules include both those that are platform specific and those that are not platform specific. Each module has a standard interface that allows the core (or other module) to call the module. A platform vendor constructs a BIOS by selecting modules from one or more vendors, which when executed can select modules that are suitable for the platform the BIOS resides in.
    Type: Grant
    Filed: September 8, 2008
    Date of Patent: December 27, 2011
    Assignee: Intel Corporation
    Inventors: William A. Stevens, Jr., Andrew J. Fish, Kirk D. Brannock, Robert P. Hale, Ramamurthy Krithivas
  • Patent number: 7664892
    Abstract: Provided are a method, system, and program for managing data read operations of a read command such as a read command packaged in an Internet Small Computer System Interface packet. In one embodiment, a network adapter has a microengine which obtains read target data from a cache coupled to the network adapter to respond to a read command packaged in a packet sent by an initiator over a network. If the network adapter cache does not have the target data addressed by the read command, the read command is forwarded to a target controller coupled to a storage unit to process the read command.
    Type: Grant
    Filed: February 1, 2008
    Date of Patent: February 16, 2010
    Assignee: Intel Corporation
    Inventor: Ramamurthy Krithivas
  • Patent number: 7516252
    Abstract: Some embodiments include apparatus and method to allocate ports of host bus adapters in computer systems to multiple operating systems in the computer systems. Other embodiments are described and claimed.
    Type: Grant
    Filed: June 8, 2005
    Date of Patent: April 7, 2009
    Assignee: Intel Corporation
    Inventor: Ramamurthy Krithivas
  • Publication number: 20090006832
    Abstract: A BIOS includes a core and multiple modules. The modules include both those that are platform specific and those that are not platform specific. Each module has a standard interface that allows the core (or other module) to call the module. A platform vendor constructs a BIOS by selecting modules from one or more vendors, which when executed can select modules that are suitable for the platform the BIOS resides in.
    Type: Application
    Filed: September 8, 2008
    Publication date: January 1, 2009
    Inventors: Willliam A. Stevens, JR., Andrew J. Fish, Kirk D. Brannock, Robert P. Hale, Ramamurthy Krithivas
  • Patent number: 7454603
    Abstract: A BIOS includes a core and multiple modules. The modules include both those that are platform specific and those that are not platform specific. Each module has a standard interface that allows the core (or other module) to call the module. A platform vendor constructs a BIOS by selecting modules from one or more vendors, which when executed can select modules that are suitable for the platform the BIOS resides in.
    Type: Grant
    Filed: February 11, 2002
    Date of Patent: November 18, 2008
    Assignee: Intel Corporation
    Inventors: William A. Stevens, Jr., Andrew J. Fish, Kirk D. Brannock, Robert P. Hale, Ramamurthy Krithivas
  • Publication number: 20080126578
    Abstract: Provided are a method, system, and program for managing data read operations of a read command such as a read command packaged in an Internet Small Computer System Interface packet. In one embodiment, a network adapter has a microengine which obtains read target data from a cache coupled to the network adapter to respond to a read command packaged in a packet sent by an initiator over a network. If the network adapter cache does not have the target data addressed by the read command, the read command is forwarded to a target controller coupled to a storage unit to process the read command.
    Type: Application
    Filed: February 1, 2008
    Publication date: May 29, 2008
    Inventor: Ramamurthy KRITHIVAS
  • Publication number: 20080098321
    Abstract: An in-band mechanism for discovery of device management capabilities is provided. The in-band discovery mechanism is similar to an out-of-band discovery mechanism and uses a non-proprietary mechanism. A management provider may query the management capabilities of devices and may register devices that may only be managed in-band with a directory agent.
    Type: Application
    Filed: October 19, 2006
    Publication date: April 24, 2008
    Inventor: Ramamurthy Krithivas
  • Patent number: 7349999
    Abstract: Provided are a method, system, and program for managing data read operations of a read command such as a read command packaged in an Internet Small Computer System Interface packet. In one embodiment, a network adapter has a microengine which obtains read target data from a cache coupled to the network adapter to respond to a read command packaged in a packet sent by an initiator over a network. If the network adapter cache does not have the target data addressed by the read command, the read command is forwarded to a target controller coupled to a storage unit to process the read command.
    Type: Grant
    Filed: December 29, 2003
    Date of Patent: March 25, 2008
    Assignee: Intel Corporation
    Inventor: Ramamurthy Krithivas
  • Publication number: 20070299951
    Abstract: A management request from a management client to perform an operation on a storage element includes an instance identifier identifying the storage element. A translator translates the instance identifier to a storage identifier that uniquely identifies the storage element. The method identifying the operation and the storage identifier is encapsulated in a storage command and forwarded to the storage element.
    Type: Application
    Filed: June 21, 2006
    Publication date: December 27, 2007
    Inventor: Ramamurthy Krithivas