Patents by Inventor Ramanathan Muthiah

Ramanathan Muthiah has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220179742
    Abstract: Systems and methods for host-assisted storage device error correction are described. A host may first encode host data with a forward error correction code (ECC) and send the encoded host data to the storage device. The storage device may further encode the host data using its own ECC. The host may also provide the forward ECC parity information to be stored on the storage device in a different location than the host data. When the host data is read by the storage device, the storage device will decode with its ECC. If the storage device ECC decode is incomplete and the bit error rate is below the recoverable error threshold of the forward error correction, the partially-recovered host data will be sent to the host. The host will complete decode using the forward ECC and parity data. Forward ECC may be selectively applied to important host data.
    Type: Application
    Filed: February 16, 2021
    Publication date: June 9, 2022
    Inventors: Akhilesh Yadav, Ramanathan Muthiah
  • Publication number: 20220182694
    Abstract: Devices and methods are disclosed that transcode a media file to generate a transcoded file that is based on a codec preference of a client device. The transcoded file can then be used to replace the media file or added as an additional stream to the media file. The transcoded file is transmitted to the client device. The client device can request the media file with a list of prioritized codecs so that the transcoded file is transcoded using a codec from the list based on the priority of the codec.
    Type: Application
    Filed: November 23, 2021
    Publication date: June 9, 2022
    Inventor: Ramanathan Muthiah
  • Publication number: 20220179585
    Abstract: Example storage systems, storage devices, and methods provide management of idle time compute tasks from host systems. Storage devices may receive host storage commands for reading and writing host data and host compute commands for executing host compute tasks. Some host compute commands may include a scheduling tag. The storage device may operate in a storage processing state and an idle state and may selectively execute delayed host compute tasks during the idle state.
    Type: Application
    Filed: February 16, 2021
    Publication date: June 9, 2022
    Inventor: Ramanathan Muthiah
  • Publication number: 20220171970
    Abstract: A storage system and method for event-driven data stitching in surveillance systems are provided. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to track an object in a plurality of video streams; determine which video frames in each of the plurality of video streams contain the object; create a separate video stream from the video frames that contain the object; and store the created separate video stream in the memory. Other embodiments are provided.
    Type: Application
    Filed: February 18, 2021
    Publication date: June 2, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Akhilesh Yadav, Ramanathan Muthiah
  • Patent number: 11347420
    Abstract: Aspects of a multi-protocol storage device including a memory and a controller are provided which allow for endurance and other storage requirements of a host to be maintained for different logical regions of memory without disruption due to protocol switching. The memory includes blocks that are each associated with a storage attribute such as high endurance, performance, or protection. While operating in a first mode such as NVMe, the controller receives a mapping of storage attributes to different logical regions and stores the mapping in memory. The controller also associates blocks to logical addresses based on the mapping. When the controller switches to a second mode such as SD in response to a host command, the controller reads the mapping from memory and similarly associates blocks to logical addresses based on the mapping in the second mode. Storage attributes thus remain applicable across modes when mapping and storing data.
    Type: Grant
    Filed: June 8, 2020
    Date of Patent: May 31, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Ramanathan Muthiah, Dinesh Kumar Agarwal, Hitesh Golechchha
  • Patent number: 11343531
    Abstract: A storage system and method for object monitoring/anticipation in surveillance systems are provided. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to identify positions of an object in a plurality of frames of video data provided by a video capture device; determine a rate of movement of the object based on the identified positions; and based on the determined rate of movement of the object, provide a suggestion to the video capture device to dynamically modify an encoding bit rate of the video data to improve video quality of the object. Other embodiments are provided.
    Type: Grant
    Filed: June 17, 2020
    Date of Patent: May 24, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventor: Ramanathan Muthiah
  • Patent number: 11340986
    Abstract: Systems and methods for host-assisted storage device error correction are described. A host may first encode host data with a forward error correction code (ECC) and send the encoded host data to the storage device. The storage device may further encode the host data using its own ECC. The host may also provide the forward ECC parity information to be stored on the storage device in a different location than the host data. When the host data is read by the storage device, the storage device will decode with its ECC. If the storage device ECC decode is incomplete and the bit error rate is below the recoverable error threshold of the forward error correction, the partially-recovered host data will be sent to the host. The host will complete decode using the forward ECC and parity data. Forward ECC may be selectively applied to important host data.
    Type: Grant
    Filed: February 16, 2021
    Date of Patent: May 24, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Akhilesh Yadav, Ramanathan Muthiah
  • Publication number: 20220155998
    Abstract: A storage system and method for token provisioning for faster data access are provided. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to receive a write command from a host to write data in the memory; write the data in the memory at a starting physical address; provide the host with a token indicating the starting physical address; receive a read command and the token from the host; and read the data stored in the memory at the starting physical address as indicated by the token. Other embodiments are provided.
    Type: Application
    Filed: February 17, 2021
    Publication date: May 19, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventor: Ramanathan Muthiah
  • Patent number: 11328511
    Abstract: A storage system and method for improved playback analysis are provided. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to identify a plurality of frames in video data stored in the memory that differ from surrounding frames by more than a threshold amount; receive a request from a host for quick playback of the video data; and send the plurality of frames to the host. Other embodiments are provided.
    Type: Grant
    Filed: March 13, 2020
    Date of Patent: May 10, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Ramanathan Muthiah, Judah Gamliel Hahn
  • Publication number: 20220138545
    Abstract: Various embodiments of this disclosure are directed to a mixed digital and analog domain approach to computational storage or memory applications. The mixed approach enables certain compute operations to be advantageously performed in the analog domain, achieving power saving. In some embodiments, an analog compute core is implemented based on a first set of memory elements that are made available with a second set of memory elements for digital data storage. A controller coupled to both sets of memory elements is able to selectively direct computational tasks to either the analog compute core or a digital processor coupled with the controller, based on one or more parameters including power, precision, and workload. In certain embodiments involving neural network tasks, the controller is configured to route certain tasks to the analog compute core based on neural network based factors such as network layer positioning and input signal type.
    Type: Application
    Filed: February 11, 2021
    Publication date: May 5, 2022
    Inventors: Ramanathan Muthiah, Ramkumar Ramamurthy
  • Publication number: 20220129388
    Abstract: A non-volatile storage system includes a memory controller connected to an integrated memory assembly. The integrated memory assembly includes a memory die comprising non-volatile memory cells and a control die bonded to the memory die. The memory controller receives commands from a host, performs logical address to physical address translation (“address translation”) operations for the commands, and instructs the integrated memory assembly to perform one or more operations in support of the command. The control die also includes the ability to perform the address translation. When performing a command from the host, the memory controller can choose to perform the necessary address translation or instruct the control die to perform the address translation. When the control die performs the address translation, the resulting physical address is used by the control die to perform one or more operations in support of the command.
    Type: Application
    Filed: February 17, 2021
    Publication date: April 28, 2022
    Applicant: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Rakesh Balakrishnan, Eldhose Peter, Akhilesh Yadav, Ramanathan Muthiah, Vimal Kumar Jain
  • Publication number: 20220113904
    Abstract: A storage system and method for device-determined, application-specific dynamic command clustering are provided. In one embodiment, the storage system comprises a memory and a controller. The controller is configured to analyze commands received from a host to detect a pattern of a plurality of commands; inform the host of the pattern; receive, from the host, a single command comprising an identifier associated with the plurality of commands; and in response to receiving the single command from the host, executing the plurality of commands. Other embodiments are provided.
    Type: Application
    Filed: February 17, 2021
    Publication date: April 14, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventors: Ramanathan Muthiah, Narendhiran Chinnaanangur Ravimohan, Balaji Thraksha Venkataramanan, Ramkumar Ramamurthy
  • Patent number: 11301168
    Abstract: A storage system and method for user-defined data archiving are provided. In one embodiment, the method comprises: receiving a write command from a host; determining whether the storage system received an indicator from the host indicating that data of the write command is archive data; in response to determining that the storage system received the indicator, storing the data in the multi-level memory cells; and in response to determining that the storage system did not receive the indicator, storing the data in the single-level memory cells. Other embodiments are provided.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: April 12, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventors: Laxmi Bhoopali, Ramanathan Muthiah, Kshitij Gupta, Niraj Srimal
  • Patent number: 11294579
    Abstract: Aspects of a multi-protocol storage device including a controller are provided which handle mode switches after a shutdown resulting in a large amount of unfinished work by phasing the work during and after initialization. The controller operates in a first mode such as an SD mode and a second mode such as a NVMe mode. In the event of a shutdown in the second mode resulting in unfinished work, the controller initializes in the first mode. During initialization, the controller determines whether a completion time for the unfinished work exceeds an initialization time in the first mode. When the completion time exceeds the initialization time, the controller performs a first portion of the work during initialization and postpones performance of at least a second portion of the unfinished work until after initialization. As a result, initialization timeouts in the first mode due to the unfinished work may be avoided.
    Type: Grant
    Filed: June 18, 2020
    Date of Patent: April 5, 2022
    Assignee: WESTERN DIGITAL TECHNOLOGIES, INC.
    Inventors: Ramanathan Muthiah, Hitesh Golechchha, Dinesh Kumar Agarwal
  • Patent number: 11288007
    Abstract: Virtual physical erase of a memory of a data storage device. One example data storage device may include a flash memory. The data storage device further may include an electronic processor that may be configured to store a first portion of data in the flash memory, and receive a physical erase request from an access device. The electronic processor may be further configured to identify a first block of the flash memory and a memory fragment of the first block where the first portion of data is stored in the flash memory. The electronic processor may be further configured to, in response to receiving the physical erase request, program one or more cells corresponding to the memory fragment to an increased voltage state so as to obfuscate the first portion of data that is stored in the flash memory.
    Type: Grant
    Filed: May 16, 2019
    Date of Patent: March 29, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventor: Ramanathan Muthiah
  • Patent number: 11284125
    Abstract: A self-data-generating storage system and method for use therewith are provided. In one embodiment, a controller of the storage system is configured to receive a single video frame of video footage from a host; generate a plurality of video frames from an interpolation of the single video frame; and store the single video frame and the generated plurality of video frames in the memory. Other embodiments are provided.
    Type: Grant
    Filed: June 11, 2020
    Date of Patent: March 22, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventor: Ramanathan Muthiah
  • Publication number: 20220083256
    Abstract: Aspects of a storage device including a memory and a controller are provided which optimize read look ahead (RLA) performance based on zone configurations or stored metadata. The controller stores in memory information previously received from a host, including a zone configuration or other information from which metadata associated with subsequent data to be pre-fetched in RLA may be determined. When the stored information includes the zone configuration, the controller reads data from memory in response to a host command and limits pre-fetching of subsequent data from the memory based on the zone configuration. When the stored information includes metadata, the controller reads the metadata associated with subsequent data from the memory, and limits pre-fetching of the subsequent data based on the metadata. Thus, resources of the storage device that are typically used for RLA may instead be used for other operations, improving the efficiency of the storage device.
    Type: Application
    Filed: February 19, 2021
    Publication date: March 17, 2022
    Inventor: Ramanathan Muthiah
  • Publication number: 20220083268
    Abstract: A storage system and method for time-based data retrieval are provided. In one embodiment, a controller of the storage system is configured to receive time information from a host; receive a write command from the host, wherein the write command comprises a logical block address; and create a time-to-logical-block-address map from the time information and the logical block address received from the host. Other embodiments are provided.
    Type: Application
    Filed: February 16, 2021
    Publication date: March 17, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventor: Ramanathan Muthiah
  • Publication number: 20220086455
    Abstract: A storage system and method for storage management in multi-channel, variable-bit-rate systems are provided. In one embodiment, a host is provided comprising a first interface configured for communication with a storage system; a second interface configured for communication with a video capture device; and a processor. The processor is configured to receive an internal latency estimate from the storage system; use the internal latency estimate from the storage system to determine whether a rate of data generation by the video capture device exceeds a storage rate of the storage system; and in response to determining that the rate of data generation by the video capture device exceeds the storage rate of the storage system, instruct the video capture device to lower its rate of data generation. Other embodiments are provided.
    Type: Application
    Filed: February 16, 2021
    Publication date: March 17, 2022
    Applicant: Western Digital Technologies, Inc.
    Inventor: Ramanathan Muthiah
  • Patent number: 11262928
    Abstract: A storage system and method for enabling partial defragmentation are provided. In one embodiment, a storage system comprises a memory and a controller. The controller is configured to receive an indication from a host that the host will be reading from a portion of the memory in a burst mode; determine whether a fragmentation level of the portion of the memory is above a threshold; and in response to determining that the fragmentation level of the portion of the memory is above the threshold, perform a defragmentation of the portion of the memory prior to reading data stored in the portion of the memory. Other embodiments are provided.
    Type: Grant
    Filed: June 12, 2020
    Date of Patent: March 1, 2022
    Assignee: Western Digital Technologies, Inc.
    Inventor: Ramanathan Muthiah