Abstract: Methods and apparatus for predicting a future estimated host read access rate for variable bit rate (VBR) data streams that include Program Clock Reference (PCR) indicators or other playback clock synchronization values. The VBR data stream may be encoded, for example, as a Motion Picture Experts Group (MPEG)-transport stream (TS). In some examples, a data storage device with a non-volatile memory (NVM) array parses an MPEG-TS VBR data stream retrieved from the NVM array to identify PCRs. Using the PCRs, the device estimates the future host data access rate for additional portions of MPEG-TS VBR data not yet requested by the host. The data storage device may then adaptively adjust background (e.g. overhead) management operations such as garbage collection based on the future host data access rate.

Abstract: A storage system and method for media-based fast-fail configuration are provided. In one embodiment, the storage system aggregates elapsed time spent handling errors in parts of a media frame read from the memory of the storage system. The storage system compares the aggregated elapsed time to a threshold representing a total acceptable latency. If the aggregated elapsed time does not exceed the threshold, the storage system handles error(s) in other part(s) of the media frame read from the memory. However, if the aggregated elapsed time exceeds the threshold, the storage system sends an error to a host without handling error(s) in other part(s) of the media frame read from the memory. Other embodiments are provided.

Abstract: A storage system, host, and method for extended and imaginary logical-to-physical address mapping are provided. In one embodiment, a host maps logical block addresses of a plurality of random data to a sequential set of imaginary logical addresses that extend beyond a logical capacity of a memory in a storage system. The host sends a request to the storage system to write the plurality of random data in the sequential set of imaginary logical addresses. Other embodiments are provided.

Abstract: Devices and methods are disclosed that receive a request from a client device for a media file, determine compatibility of the media file with the requesting client device, and, if appropriate, transcode the media file into a compatible form which is then transmitted to the requesting client device. To determine whether a media file is compatible with the client request, the storage device can analyze a portion of the requested media file and compare that information with parameters of the client request. Transcoded data can be stored alongside the original file as a new file, stored in place of the original file, or stored in the same container as the original file so that the new file includes both the original version and the transcoded version of the media file.

Abstract: A storage system and method for multiprotocol handling are provided. In one embodiment, a computing device is provided comprising a plurality of communication channels configured to communicate with a storage system, wherein a first communication channel has a faster data transfer speed than a second communication channel. The computing device also comprises a processor configured to determine a priority level of a command; send the command with an indication of its priority level to the storage system; in response to the command being a high-priority command, use the first communication channel for transferring data for the command; and in response to the command being a low-priority command, use the second communication channel for transferring data for the command. Other embodiments are provided.

Abstract: A host and method for interleaving data in a storage system for enhanced quality of service are provided. In one embodiment, a host is provided comprising an interface configured to communicate with a storage system comprising a memory. The processor is configured to determine a skip length for interleaving data to be stored in the storage system; interleave data according to the determined skip length; and send the interleaved data to the storage system for storage. Other embodiments are provided.

Abstract: A storage system and method for storing scalable video are provided. In one embodiment, a storage system is presented comprising a memory and a controller. The controller is configured to receive, from a host, video data and a plurality of profiles for the video data; receive, from the host, usage information on each of the plurality of profiles; and store the plurality of profiles in the memory, wherein a profile that is used more frequently is stored in a higher endurance and/or high protection portion of the memory than a profile that is used less frequently. Other embodiments are provided.

Abstract: In some embodiments, an apparatus includes a memory configured to store data and a controller coupled to the memory. The controller is configured to receive, from a computing device coupled to the apparatus, one or more frames of a digital video. The controller is also configured to analyze one or more components of the memory. The controller is further configured to determine a set of states for the one or more components of the memory based on the analysis of the one or more components of the memory. The controller is further configured to determine a first encoding rate for the digital video from a plurality of encoding rates based on the set of states for the one or more components of the memory. The controller is further configured to encode the digital video based on the first encoding rate and to store the encoded digital video in the memory.

Abstract: A storage system and method for improved playback analysis are provided. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to identify a plurality of frames in video data stored in the memory that differ from surrounding frames by more than a threshold amount; receive a request from a host for quick playback of the video data; and send the plurality of frames to the host. Other embodiments are provided.

Abstract: A storage system and method for caching a single mapping entry for a random read command are provided. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to determine whether a read command received from a host is a random read command, wherein the read command comprises a logical address; and in response to determining that the read command received from the host is a random read command, caching only an associated logical-to-physical address map entry from a logical-to-physical address map stored in the memory instead of caching a larger segment of the logical-to-physical address map that contains the entry and other entries. Other embodiments are provided.

Abstract: A storage system and method for automatic data phasing are disclosed. In one embodiment, a storage system is configured to receive, from a host, data to be written in the memory and an indication of an expected lifespan of the data; and determine whether to perform a garbage collection operation on the data based on the expected lifespan of the data. Other embodiments are provided.

Abstract: A storage system and method for optimized surveillance search are provided. In one embodiment, a storage system is provided comprising a memory and a controller. The controller is configured to: receive, from a host, an image of an object and a logical block address range of video data stored in the memory; search for the image of the object in video data in the logical block address range; and provide the host with possible hits from the search. Other embodiments are provided.

Abstract: Aspects of a storage device including a memory and a controller are provided which allow for data associated with a media stream and having high entropy to be stored in healthier memory locations, with improved data protection, and with more optimal NAND parameters than for data having low entropy. After receiving data associated with a media stream, the controller identifies an entropy level of the data. When the entropy level meets an entropy threshold, the controller stores the data in a first block of the memory associated with a lower BER, and/or with a higher write latency or a first, more discrete voltage. Alternatively, when the entropy level does not meet the entropy threshold, the controller stores the data in a second block of the memory associated with a higher BER, and/or with a lower write latency or a second, less discrete voltage.

Abstract: A solid state drive system and method receives read commands, write commands, and/or file system updates. The solid state drive system then determines the latency estimate for performing each of those commands asynchronously. The solid state drive system may utilize internal processes to determine the latency estimate. The latency estimate may include random access latency, block erase time, outstanding workload latency, garbage collection time, metadata write time, etc. The latency estimate is then returned to the host device. The host device may utilize the latency estimate to workload balance solid state drive systems.

Abstract: In some embodiments, an apparatus includes a memory configured to store data and a controller coupled to the memory. The controller is configured to receive, from a computing device coupled to the apparatus, one or more frames of a digital video. The controller is also configured to analyze one or more components of the memory. The controller is further configured to determine a set of states for the one or more components of the memory based on the analysis of the one or more components of the memory. The controller is further configured to determine a first encoding rate for the digital video from a plurality of encoding rates based on the set of states for the one or more components of the memory. The controller is further configured to encode the digital video based on the first encoding rate and to store the encoded digital video in the memory.

Abstract: A storage system and method for enabling a direct accessible boot block in a memory die are disclosed. In one embodiment, a storage system is provided comprising a NAND memory, a volatile memory, a processor, and a NAND controller. The NAND controller is configured to perform the following in response to receiving a command from the processor at power-up: read bootloader code from the NAND memory; and execute the bootloader code, wherein execution of the bootloader code causes initialization code to be read from the NAND memory and stored in the volatile memory. Other embodiments are provided.

Abstract: A storage system and method for interleaving data for enhanced quality of service are provided. In one embodiment, a storage system is presented comprising a memory and a controller. The controller is configured to determine a skip length for interleaving data received from a host; interleave the data according to the determined skip length; store the interleaved data in the memory; and update a logical-to-physical address table to reflect the interleaved data. Other embodiments are provided.

Abstract: A memory controller includes, in one embodiment, a memory interface and a dynamic stripe length manager circuit configured to receive a first weighted health factor associated with a first memory block of the memory, determine a first collective stripe length of the first memory block based on the first weighted health factor, set a first number of zones in the first memory block based on the first collective stripe length, monitor the memory to detect a trigger event that triggers a calculation of a second collective stripe length of the first memory block, the second collective stripe length being larger than the first collective stripe length, receive a second weighted health factor associated with the first memory block, determine the second collective stripe length based on the second weighted health factor, and set a second number of zones in the first memory block based on the second collective stripe length.

Abstract: A host and method for interleaving data in a storage system for enhanced quality of service are provided. In one embodiment, a host is provided comprising an interface configured to communicate with a storage system comprising a memory. The processor is configured to determine a skip length for interleaving data to be stored in the storage system; interleave data according to the determined skip length; and send the interleaved data to the storage system for storage. Other embodiments are provided.

Abstract: A memory controller includes, in one embodiment, a memory interface and a dynamic stripe length manager circuit configured to receive a first weighted health factor associated with a first memory block of the memory, determine a first collective stripe length of the first memory block based on the first weighted health factor, set a first number of zones in the first memory block based on the first collective stripe length, monitor the memory to detect a trigger event that triggers a calculation of a second collective stripe length of the first memory block, the second collective stripe length being larger than the first collective stripe length, receive a second weighted health factor associated with the first memory block, determine the second collective stripe length based on the second weighted health factor, and set a second number of zones in the first memory block based on the second collective stripe length.